Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 07/27/2026. Claims 1, 4-6, 10-11, 16 and 19-20 have been amended. Claims 2 and 17 have been canceled. Claims 21-22 have been added. Claims 1, 3-16 and 18-22 are pending on this application.
Response to Arguments
3. Applicant’s arguments with respect to amended independent claims 1, 6, and 16 have been fully considered and are persuasive. The rejections from previous office action have been withdraw.
4. Applicant’s arguments with respect to amended independent claim 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Dong et al. Pub. No. 2015/0109158 in view of Jackson U.S. patent No. 5,329,282.
Regarding claim 11. Fig. 6 of Dong et al. discloses an apparatus (600) comprising: combination circuitry (AMP1 and AMP2 having combination of input signals from U, DAC1 ILSB1, DAC2 ILSB2) having an input (input from U, from DAC1, from DAC2) and an output (output of X2); analog-to-digital converter circuitry (FLASH1) having an input (input of FLASH1), a first output (V1 to DAC4), and a second output (feedback V1 to ILSB1, DAC2 ILSB2) for one or more least significant bits (at least one significant bit from bits output of FLASH1), the input of the ADC circuitry (input of FLASH1) coupled to the output (X2) of the combination circuitry (AMP1, AMP2 ); first digital-to-analog converter (DAC) circuitry (DAC4) having an input and an output (input and output of DAC4), the input of the first DAC (input of DAC4) coupled to the first output of the ADC circuitry (FLASH1); amplifier circuitry (AMP3) having an input coupled to the output of the first DAC circuitry (output of DAC4); and second DAC circuitry (DAC1 ILSB1) having an input (input of DAC1 ILSB1) and an output (output of DAC1 ILSB1) , the input of the second DAC (input of DAC1 ILSB1) coupled to the second output of the ADC circuitry (second output of FLASH1), the output of the second DAC (output of DAC1 ILSB1) coupled to the input (input of AMP1) of the combination circuitry (AMP1 and AMP2).
However, Dong et al. do not disclose the first output (first V1) for one or more most significant bits, and the second output (second V1) for one or more least significant bits.
Fig. 3 of Jackson discloses a delta-sigma ADC comprising: analog-to-digital converter circuitry (34) having an input (input of 34), a first output (output of MSB) for one or more most significant bits (MSBs), and a second output (output of LSB) for one or more least significant bits (LSBs).
Dong et al. and Jackson are common subject matter delta-sigma ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Jackson into Dong et al. for the purpose of including the LSB in the feedback path. Because the LSB is included, quicker resolution of Vin is achieved when the signal level is relatively small, while maintaining the improvement of ADC for larger signal levels. When the signal level falls below that which may be represented by the LSB, then the SNR improves over ADC. One result of the improved performance is that ADC has much better rejection of tones which are a result of insufficient resolution of the input signal. In ADC, the MSB and the LSB were used. However, another bit besides the LSB may be used as the second bit. Also, more than two bits may be used. The only requirement is that the second bit (and other bits, if used) not be the MSB or the (MSB-1) bit in order to reduce the linearity requirements of DAC (Col. 5 lines 7-23 of Jackson).
Regarding claim 12. Dong et al. and Jackson applied to claim 11, Fig. 6 of Dong et al. further discloses wherein the input (input from U, from DAC1, from DAC2) of the combination circuitry (AMP1 and AMP2) is a first input (input from DAC1 ILSB1) , the combination circuitry AMP1 and AMP2) further having a second input (U input) , and the apparatus (Fig. 2) further comprises: delay circuitry (602) having a first terminal and a second termina (first and second terminal of 602), the first terminal of the delay circuitry (first terminal of 602) is coupled to the second input (U) of the combination circuitry (AMP1 and AMP2); and a resistor (R32) having a first terminal and a second termina (first and second terminal of R32)l, the first terminal of the resistor (first terminal of R31) is coupled to the second terminal of the delay circuitry (second terminal of 602), the second terminal of the resistor (second terminal of R32) is coupled to the output of the first DAC circuitry (output o fDAC4) and the input of the amplifier circuitry (AMP3).
Regarding claim 13. Dong et al. and Jackson applied to claim 11, Fig. 6 of Dong et al. further discloses wherein the combination circuitry (AMP and AMP2) is addition circuitry (addition input signals from U, DAC1 and DAC2).
7. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Dong et al. and Jackson applied to claim 11 above in view of Nikai et al. Pub. No. 2003/0006926.
Dong et al. and Jackson applied to claim 11, Fig. 6 of Dong et al. further discloses Fig. 6 of Zhao et al. applied to claim 11 above further discloses wherein the amplifier circuitry (AMP) further has an output terminal (output terminal of AMP3), and the apparatus (600) further comprises: inter-stage gain circuitry (AMP4) having an input (input of AMP4) coupled to the output of the amplifier circuitry (AMP3);
However, Dong et al. do not disclose a latch having an input coupled to the output of the ADC circuitry and the input of the first DAC circuitry.
Fig. 1 of Nikai et al. discloses an apparatus for pipelined ADC comprising: a latch (LATCH) CIRCUIT 7) having an input (input of 7) coupled to the output of the ADC circuitry (A/D 9) and the input of the DAC circuitry (D/A 10).
Dong et al., Jackson and Nikai et al. are common subject matter ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Nikai et al. into Dong et al. for the purpose of providing an analog-to-digital conversion circuit whose conversion speed is increased while keeping high conversion accuracy without complicating the circuit structure and increasing the circuit scale (paragraph 0099 of Nikai et al.).
8. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Dong et al. and Jackson applied to claims 11 above in view of Manganaro et al. Pub. No. 2022/0224347.
Regarding claim 15. Dong et al. and Jackson applied to claim 11, Fig. 6 of Dong et al. further discloses wherein the amplifier circuitry (AMP3) further has an output terminal (output terminal of AMP3) , further comprising filter circuitry (C3, R23) includes: a capacitor (C3) having a first terminal and a second terminal (first and second terminals of C3) ; and a resistor (R34) having a first terminal and a second terminal (first and second terminal of R34) , the first terminal of the resistor (first terminal of R34) is coupled to the output of the DAC circuitry (output of DAC4) , the input of the amplifier circuitry (input of AMP3) , and the first terminal of the capacitor (first terminal of C3).
However, Dong et al. do not disclose the second terminal of the resistor R34 is coupled to the output of the amplifier circuitry and the second terminal of the capacitor.
Fig. 2 of Manganaro et al. discloses an apparatus for pipelined ADC comprising: a filter circuitry (224) including: a capacitor (capacitor of 224) having a first terminal and a second terminal (first and second terminals of capacitor of 224); and a resistor (resistor of 224) having a first terminal and a second terminal (first and second terminal of resistor of 224) the first terminal of the resistor (first terminal of resistor of 224) is coupled to the output terminal of the DAC circuitry (DAC 216), the input of the first amplifier circuitry (input of amplifier of 224) , and the first terminal of the capacitor (first terminal of capacitor of 224) , the second terminal of the resistor (second terminal of resistor of 224) is coupled to the output of the first amplifier circuitry (output of amplifier of 224), and the second terminal of the capacitor (second terminal of capacitor of 224).
Dong et al, Jackson. and Manganaro et al. are common subject matter ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Manganaro et al. into Dong et al. for the purpose of providing filter to sufficiently suppress the DAC output images caused by the synchronous clocked operation, in practice, a higher-order filter, such as a second, or third order filter is often preferred or even required (paragraph 0029 of Manganaro et al.).
Allowable Subject Matter
9. Claims 1,3-10, and 16-22 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 1, in addition to other elements in the claim, prior art considered individual or combination does not teach: a second amplifier circuitry having an input coupled to the output of the first amplifier and an output coupled to the second input of the combination circuitry.
With respect to claim 6, in addition to other elements in the claim, prior art considered individual or combination does not teach: second amplifier circuitry having an input and an output, the input of the second amplifier circuitry coupled to the output of the first amplifier circuitry, the output of the second amplifier circuitry coupled to the first input of the combination circuitry.
With respect to claim 16, in addition to other elements in the claim, prior art considered individual or combination does not teach: second amplifier circuitry having an input coupled to the output of the first amplifier circuitry, and an output coupled to the input of the combination circuitry.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
08/15/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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