DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is in response to communication filed on 07/31/2024. Claims 1 – 20 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kozlov et al. Pub. No. 2022/0045687.
Fig. 5 of Kozlov et al. discloses a pipelined ADC having a CT filter 108, an amplifier circuitry 118, ADC 104, DAC 106 and combination circuitry 520.
Fig. 8 of Kozlov et al. disclose a diagram of CT filter 108 having resistor R1.
Fig. 13 discloses a diagram of amplifier circuitry 118 having first and second gain stages.
Regarding claim 1. Fig. 5 of Kozlov et al. discloses an apparatus (400) comprising: combination circuitry (520) having a first input (202 input) , a second input (d(t) input) , and an output (output of 520); analog-to-digital converter (ADC) circuitry (ADC1 104) having an input and an output (input and output of 104), the input of the ADC circuitry (input of 104) coupled to the output of the combination circuitry (output of 520) ; digital-to-analog converter (DAC) circuitry (DAC1 106) having an input and an output (input and output of 106) , the input of the DAC (input of 106) coupled to the output of the ADC circuitry (output of 104) ; a resistor (108; see Fig. 8 for discloses R1 of 108 circuit) having a first terminal and a second terminal (first and second terminals of R1 in Fig. 8), the first terminal of the resistor (first terminal of R1 in Fig. 8) coupled to the first input (202 input) of the combination circuitry (520) ; amplifier circuitry (118) having an input coupled to the output of the DAC circuitry (output of 106) and the second terminal of the resistor (second terminal of R1 in Fig. 8).
Regarding claim 4. The apparatus of claim 1, Fig. 13 wherein the amplifier circuitry (118) further has an output (output of the first gain stage in118), and the apparatus (Fig. 5) further comprising inter-stage gain circuitry (second gain stage circuitry in 118) having an input (input of second gain stage in 118) coupled to the output of the amplifier circuitry (output of first gain stage in 118).
5. Claims 6 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi et al. Pub. No. 2009/0033534.
Regarding claim 6. Fig. 9 of Kobayashi et al. discloses an apparatus (210) comprising: combination circuitry (combination circuitry of SW20 and SW10 at input terminal of first stage 10) having an input and an output (input and output of summing node of feedback and Vin); analog-to-digital converter (ADC) circuitry (A/D 12) having an input and an output (input and output of 12) , the input of the ADC circuitry (output of 12) coupled to the output of the combination circuitry (output of summing node of feedback and Vin); digital-to-analog converter (DAC) circuitry (D/A 14) having an input and an output (input and output of 14), the input of the DAC (input of 14) coupled to the output of the ADC circuitry (output of 12); first amplifier circuitry (18) having an input (16) and an output (output of 18), the input (16) of the first amplifier circuitry (18) coupled to the output of the DAC circuitry (14); and second amplifier circuitry (21, 28) having an input (input of 21) and an output (output of 28) , the input of the second amplifier circuitry (input of 21) coupled to the output of the first amplifier circuitry (output of 18), the output of the second amplifier circuitry (output of 28) coupled to the input of the combination circuitry (input of summing node of feedback and Vin).
6. Claims 11-13 and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. Pub. No. 2017/0170839.
Regarding claim 11. Fig. 2 of Zhao et al. disclose an apparatus for pipelined ADC comprising: combination circuitry (combining terminal of S1) having an input (input and output of combining terminal of S1) and an output (output of combining terminal of S1); analog-to-digital circuitry (converter (Flash ADC) 208) having an input (input of 208), a first output (firs V1) , and a second output (second V1), the input of the ADC circuitry (input of 208) coupled (via 202) to the output of the combination circuitry (output of terminal S1); first digital-to-analog converter (DAC) circuitry (DAC2A 210) having an input and an output (input and output of 210) , the input of the first DAC 210) coupled to the first output of the ADC circuitry (first V1) ; amplifier circuitry (204) having an input (input of 204) coupled to the output of the DAC circuitry (output of 210) ; and second DAC circuitry (DAC1 214) having an input and an output (input and output of 214) , the input of the second DAC (input of 214) coupled to the second output (second V1) of the ADC circuitry (208), the output of the second DAC (output of 214) coupled to the input of the combination circuitry (input of combining terminal of S1).
Regarding claim 12. The apparatus of claim 11, Fig. 2 further discloses wherein the input of the combination circuitry (input of combining terminal S1) is a first input (input from 214), the combination circuitry (combining terminal of S1) further having a second input (R1U input) , and the apparatus (Fig. 2) further comprises: delay circuitry (Delay 212) having a first terminal and a second terminal (first and second terminals of 212) , the first terminal of the delay circuitry (first terminal of 212) is coupled (202) to the second input (R1U input) of the combination circuitry (combining terminal of S1); and a resistor (R21) having a first terminal and a second terminal (first and second terminals of R21), the first terminal of the resistor (first terminal of R21) is coupled to the second terminal of the delay circuitry (second terminal of 212) , the second terminal of the resistor (second terminal of R21) is coupled to the output of the first DAC circuitry (210) and the input of the amplifier circuitry (input of 204).
Regarding claim 13. The apparatus of claim 11, wherein the combination circuitry (combination of S1 terminal) is addition circuitry (summing node of S1 terminal).
Regarding claim 16. Fig. 2 of Zhao et al. discloses an apparatus for pipelined ADC comprising: first inter-stage gain circuitry (202, 212, R21, 208, 210, 214, 204) including: combination circuitry (combination terminal of S1) having an input (input of combination of S1) and an output (output of S1) ; analog-to-digital converter (ADC) circuitry (FLASH1 ADC 208) having an input and an output (input and output of 208), the input of the ADC circuitry (input of 208) coupled (202) to the output of the combination circuitry (output of S1) ; digital-to-analog converter (DAC) circuitry (DAC2A 210) having an input and an output (input and output of 210), the input of the DAC (input of 210) coupled to the output (V1 output) of the ADC circuitry (208); and amplifier circuitry (204) having an input and an output (input and output of 204), the input of the amplifier circuitry (input of 204) coupled to the output of the DAC circuitry (output of 210) ; and second inter-stage gain circuitry (206, FLASH2 ADC, DAC2, DAC3) having an input (input of 206) coupled to the output of the amplifier circuitry (output of 204).
Regarding claim 17. The apparatus of claim 16, Fig. 2 further discloses wherein the amplifier circuitry (204) is first amplifier circuitry (204) , the first amplifier circuitry (204) further has an output (output of 204) , and the apparatus (Fig. 2) further comprises second amplifier circuitry (206) having an input (input of 206) coupled to the output of the first amplifier circuitry (output of 204) and the input of the second inter-stage gain circuitry (input of 206, FLASH2 ADC, DAC2, DAC3).
Regarding claim 18. The apparatus of claim 16, Fig. 2 further discloses wherein the DAC circuitry (210) is first DAC circuitry (210) , the output of the ADC circuitry (208) is a first output (First V1 output) , the ADC circuitry (208) further has a second output (second V1 output) , and the apparatus (Fig. 2) further comprises second DAC circuitry (DAC1 214) having an input (input of 214) coupled to the second output of the ADC circuitry (second V1 output of 208).
Regarding claim 19. The apparatus of claim 16, Fig. 2 further discloses wherein the input of the combination circuitry (input of combination terminal S1) is a first input (input from 214) , the combination circuitry (combination terminal of S1) further having a second input (R1U input), and the apparatus (Fig. 2) further comprises: delay circuitry (delay 212) having a first terminal and a second terminal (first and second terminal of 212), the first terminal of the delay circuitry (first terminal of 212) is coupled (via 202) to the second input (R1U input) of the combination circuitry (combination of S1 terminal); and a resistor (R21) having a first terminal and a second terminal (first and second terminals of R21), the first terminal of the resistor (first terminal of R21) is coupled to the second terminal of the delay circuitry (second terminal of 212) , the second terminal of the resistor (second terminal of R21) is coupled to the output of the DAC circuitry (output of 210) and the input of the amplifier circuitry (input of 204).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over by Kozlov et al. applied to claim 1 above in view of Zhao et al. Pub. No. 2017/0170839.
Fig. 2 of Kozlov et al. applied to claim 1 above further discloses wherein the amplifier circuitry (118) is first amplifier circuitry (118), the first amplifier circuitry (118) further has an output (output of 118).
However, Kozlov et al. do not discloses the apparatus further comprises second amplifier circuitry having an input and an output, wherein the input of the second amplifier circuitry is coupled to the output of the first amplifier circuitry, and the output of the second amplifier circuitry is coupled to the second input of the combination circuitry.
Fig. 9 of Kobayashi et al. discloses an apparatus (210) comprising: combination circuitry (combination circuitry of feedback SW20 and SW10 Vin at combination terminal of 10) having an input and an output (input and output of combination input terminal of stage 10 of feedback and Vin); the apparatus (210) further comprises: a first amplifier (18), second amplifier circuitry (21, 28) having an input and an output (input and output of 21 and 28), wherein the input of the second amplifier circuitry (input of 21) is coupled to the output of the first amplifier circuitry (output of 18) , and the output of the second amplifier circuitry (output of 28) is coupled to a second input (feedback input of SW20) of the combination circuitry (combination circuitry of SW20 and SW10 at input terminal of 10).
Kozlov et al. and Kobayashi et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Kobayashi et al. into Kozlov et al. for the purpose of providing an offset compensation voltage used to compensate for at least part of an offset voltage added to the analog signal sampled by the sub-A-D converter circuit is supplied to at least one capacitor (paragraph 0008 of Kobayashi et al.).
9. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over by Kozlov et al. applied to claim 1 above in view of Zhao et al. Pub. No. 2017/0170839.
Regarding claim 3. Kozlov et al. applied to claim 1 above, Fig. 5 of Kozlov et al. further discloses wherein the DAC circuitry (106) is first DAC circuitry (DAC1), the output of the ADC circuitry (104) is a first output (output of 104).
However, Kozlov et al. do not disclose the ADC circuitry (104) further has a second output, and the apparatus further comprises second DAC circuitry having an input and an output, the input of the second DAC circuitry is coupled to the second output of the ADC circuitry, and the output of the second DAC circuitry is coupled to the second input of the combination circuitry.
Fig. 2 of Zhao et al. discloses an apparatus of pipelined ADC comprising DAC circuitry (DAC2A 210) is first DAC circuitry (DAC2A), the output of the ADC circuitry (FlashH1 ADC 208) is a first output (first output V1 of 208); the ADC circuitry (208) further has a second output (second output V1 of 208), and the apparatus (Fig. 2) further comprises second DAC circuitry (DAC1 214) having an input and an output (input and output of 214), the input of the second DAC circuitry (input of 214) is coupled to the second output of the ADC circuitry (second output V1 of 208) , and the output of the second DAC circuitry (output of 214) is coupled at a second input (S1 input) of a combination circuitry (combining input node of R1U and S1).
Kozlov et al. and Zhao et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Zhao et al. into Kozlov et al. for the purpose of providing MASH ADCs rely on the cancellation of quantization noise, which requires accurate matching between analog and digital transfer functions (paragraph 0022 of Zhao et al.).
10. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over by Kozlov et al. applied to claim 1 above in view of Shibata et al. U.S. patent No. 10,171,102.
Kozlov et al. applied to claim 1 above do not discloses wherein the amplifier circuitry further has an output, and the apparatus further comprises: delay circuitry having a first terminal and a second terminal, the first terminal of the delay circuitry coupled to the first input of the combination circuitry and the second terminal of the delay circuitry coupled to the first terminal of the resistor; and filter circuitry having a first terminal and a second terminal, the first terminal of the filter circuitry is coupled to the output of the DAC circuitry, the second terminal of the resistor, and the input of the amplifier circuitry, the second terminal of the filter circuitry is coupled to the output of the amplifier circuitry.
Fig. 6 of Shibata et al. discloses an apparatus for pipelined ADC comprising an amplifier circuitry (304) further has an output (output of 304) , and the apparatus (Fig. 6) further comprises: delay circuitry (610) having a first terminal and a second terminal (first and second terminal 610), the first terminal of the delay circuitry (first terminal of 610) coupled to a first input (input of summing node of gm and Resistor) of the combination circuitry (combination circuitry of gm and resistor at summing node) and the second terminal of the delay circuitry (second terminal of 610) coupled to a first terminal of the resistor (first terminal of R621) ; and filter circuitry (C 602, R 602) having a first terminal (first and a second terminal (first and second terminal of C 602, R 602), the first terminal of the filter circuitry (first terminal of C 602, R 602) is coupled to the output of a DAC circuitry (308), the second terminal of the resistor (second terminal of R612) , and an input of the amplifier circuitry (input of 304), the second terminal of the filter circuitry (second terminal of C 602, R606) is coupled to the output of the amplifier circuitry (output of 304).
Kozlov et al. and Shibata et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Shibata et al. into Kozlov et al. for the purpose of providing filtering the averaged voltage signal by one or more filtering circuit networks; filtering circuit networks can provide passive and/or active filtering to improve performance of the CT multi-stage ADC (Col. 8 lines 41-45 of Shibata et al.).
11. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. applied to claim 6 above in view of Zhao et al. Pub. No. 2017/0170839.
Fig. 9 of Kobayashi et al. applied to claim 6 above further discloses wherein the input of the combination circuitry (summing node of feedback and Vin) is a first input (Vin input) , the combination circuitry (summing node of feedback and Vin) further having a second input (feedback input).
However, Kobayashi et al. do not disclose and the apparatus (210) further comprises: delay circuitry having a first terminal and a second terminal, the first terminal of the delay circuitry is coupled to the second input of the combination circuitry; and a resistor having a first terminal and a second terminal, the first terminal of the resistor is coupled to the second terminal of the delay circuitry, the second terminal of the resistor is coupled to the output of the DAC circuitry and the input of the first amplifier circuitry.
Fig. 2 of Zhao et al. discloses an apparatus for pipelined ADC comprising: delay circuitry (212) having a first terminal and a second terminal (first and second terminals of 212) , the first terminal of the delay circuitry (first terminal of 212) is coupled (202) to the second input of the combination circuitry (summing node of feedback and Vin); and a resistor (R21) having a first terminal and a second terminal (first and second terminal of R21) , the first terminal of the resistor (first terminal of R21) is coupled to the second terminal of the delay circuitry (second terminal of 212) , the second terminal of the resistor (second terminal of R21) is coupled to the output of the DAC circuitry (DAC2A 210) and the input of the first amplifier circuitry (input of 204).
Kobayashi et al. and Zhao et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Zhao et al. into Kobayashi et al. for the purpose of providing DAC timing mismatch error measurement and calibration are particularly suitable for high speed, continuous-time, high precision applications where MASH ADCs are used (Paragraph 0087 of Zhao et al.).
12. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. applied to claim 6 above in view of Oshima et al. Pub. No. 2018/0302102.
Fig. 9 of Kobayashi et al. applied to claim 6 above discloses the combination circuit (summing node of feedback and Vin); but do not disclose the combination circuitry is subtraction circuitry.
Fig. 2 of Oshima et al. disclosed an apparatus for pipelined ADC comprising: a combination circuitry (AS11) is subtraction circuitry (subtraction circuit of AS11).
Kobayashi et al. and Oshima et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Zhao et al. into Kobayashi et al. for the purpose of providing analog adder/subtracter outputs a differential signal between an external input signal and an output signal of the digital/analog converter circuit DAC to the analog integrator unit to provide MASH sigma-delta type ADC (paragraph 0042 of Oshima et al.); thus in the MASH type sigma-delta ADC, it is possible to attain a high resolution thereof as long as the quantization error Q.sub.1 can be canceled (paragraph 0049 of Oshima et al.).
13. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. applied to claim 6 above in view of Nikai et al. Pub. No. 2003/0006926.
Kobayashi et al. applied to claim 6 above further discloses inter-stage gain circuitry (inter-stage gain 21) having an input (input of 21) coupled to the output of the first amplifier circuitry (18) and the input of the second amplifier circuitry (input of 28). However, Kobayashi et al. do not disclose a latch having an input coupled to the output of the ADC circuitry and the input of the DAC circuitry.
Fig. 1 of Nikai et al. discloses an apparatus for pipelined ADC comprising: a latch (LATCH) CIRCUIT 7) having an input (input of 7) coupled to the output of the ADC circuitry (A/D 9) and the input of the DAC circuitry (D/A 10).
Kobayashi et al. and Nikai et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Nikai et al. into Kobayashi et al. for the purpose of providing an analog-to-digital conversion circuit whose conversion speed is increased while keeping high conversion accuracy without complicating the circuit structure and increasing the circuit scale (paragraph 0099 of Nikai et al.).
14. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. applied to claim 6 above in view of Manganaro et al. Pub. No. 2022/0224347.
Kobayashi et al. applied to claim 6 above do not discloses a filter circuitry including: a capacitor having a first terminal and a second terminal; and a resistor having a first terminal and a second terminal, the first terminal of the resistor is coupled to the output terminal of the DAC circuitry, the input of the first amplifier circuitry, and the first terminal of the capacitor, the second terminal of the resistor is coupled to the output of the first amplifier circuitry, the input of the second amplifier circuitry, and the second terminal of the capacitor.
Fig. 2 of Manganaro et al. discloses an apparatus for pipelined ADC comprising: a filter circuitry (224) including: a capacitor (capacitor of 224) having a first terminal and a second terminal (first and second terminals of capacitor of 224); and a resistor (resistor of 224) having a first terminal and a second terminal (first and second terminal of resistor of 224) the first terminal of the resistor (first terminal of resistor of 224) is coupled to the output terminal of the DAC circuitry (DAC 216), the input of the first amplifier circuitry (input of amplifier of 224) , and the first terminal of the capacitor (first terminal of capacitor of 224) , the second terminal of the resistor (second terminal of resistor) is coupled to the output of the first amplifier circuitry (output of amplifier of 224) , the input of the second amplifier circuitry (second input of amplifier of 224) , and the second terminal of the capacitor (second terminal of capacitor of 224).
Kobayashi et al. and Manganaro et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Manganaro et al. into Kobayashi et al. for the purpose of providing filter to sufficiently suppress the DAC output images caused by the synchronous clocked operation, in practice, a higher-order filter, such as a second, or third order filter is often preferred or even required (paragraph 0029 of Manganaro et al.).
15. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. applied to claim 11 above in view of Nikai et al. Pub. No. 2003/0006926.
Fig. 2 of Zhao et al. applied to claim 11 above further discloses wherein the amplifier circuitry (204) further has an output terminal (output terminal of 204), and the apparatus (Fig. 2) further comprises: inter-stage gain circuitry (206) having an input (input of 206) coupled to the output of the amplifier circuitry (output of 204);
However, Zhao et al. do not disclose a latch having an input coupled to the output of the ADC circuitry and the input of the first DAC circuitry.
Fig. 1 of Nikai et al. discloses an apparatus for pipelined ADC comprising: a latch (LATCH) CIRCUIT 7) having an input (input of 7) coupled to the output of the ADC circuitry (A/D 9) and the input of the DAC circuitry (D/A 10).
Zhao et al. and Nikai et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Nikai et al. into Zhao et al. for the purpose of providing an analog-to-digital conversion circuit whose conversion speed is increased while keeping high conversion accuracy without complicating the circuit structure and increasing the circuit scale (paragraph 0099 of Nikai et al.).
16. Claims 15 and 20 rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. applied to claims 11 and 16 above in view of Manganaro et al. Pub. No. 2022/0224347.
Regarding claim 15. Fig. 2 of Zhao et al. applied to claim 11 above further discloses wherein the amplifier circuitry (204) further has an output terminal (output terminal of 204) , further comprising filter circuitry (C2, R23) includes: a capacitor (C2) having a first terminal and a second terminal (first and second terminals of C2) ; and a resistor (R23) having a first terminal and a second terminal (first and second terminal of R23) , the first terminal of the resistor (first terminal of R23) is coupled to the output of the DAC circuitry (output of 210) , the input of the amplifier circuitry (input of 204) , and the first terminal of the capacitor (first terminal of C2).
However, Zhao et al. do not disclose the second terminal of the resistor is coupled to the output of the amplifier circuitry and the second terminal of the capacitor.
Fig. 2 of Manganaro et al. discloses an apparatus for pipelined ADC comprising: a filter circuitry (224) including: a capacitor (capacitor of 224) having a first terminal and a second terminal (first and second terminals of capacitor of 224); and a resistor (resistor of 224) having a first terminal and a second terminal (first and second terminal of resistor of 224) the first terminal of the resistor (first terminal of resistor of 224) is coupled to the output terminal of the DAC circuitry (DAC 216), the input of the first amplifier circuitry (input of amplifier of 224) , and the first terminal of the capacitor (first terminal of capacitor of 224) , the second terminal of the resistor (second terminal of resistor of 224) is coupled to the output of the first amplifier circuitry (output of amplifier of 224), and the second terminal of the capacitor (second terminal of capacitor of 224).
Zhao et al. and Manganaro et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Manganaro et al. into Zhao et al. for the purpose of providing filter to sufficiently suppress the DAC output images caused by the synchronous clocked operation, in practice, a higher-order filter, such as a second, or third order filter is often preferred or even required (paragraph 0029 of Manganaro et al.).
Regarding claim 20. Fig. 2 of Zhao et al. applied to claim 16 above further discloses further comprising filter circuitry (C2, R23) includes: a capacitor (C2) having a first terminal and a second terminal (first and second terminal of C2); and a resistor (R23) having a first terminal and a second terminal (first and second terminal of R23) , the first terminal of the resistor (first terminal of R23) is coupled to the output of the DAC circuitry (210) , the input of the amplifier circuitry ( input of 204), and the first terminal of the capacitor (first terminal of C2).
However, Zhao et al. the second terminal of the resistor is coupled to the output of the amplifier circuitry, the input of the second inter-stage gain circuitry, and the second terminal of the capacitor.
Fig. 2 of Manganaro et al. discloses an apparatus for pipelined ADC comprising: a filter circuitry (224) including: a capacitor (capacitor of 224) having a first terminal and a second terminal (first and second terminals of capacitor of 224); and a resistor (resistor of 224) having a first terminal and a second terminal (first and second terminal of resistor of 224) the first terminal of the resistor (first terminal of resistor of 224) is coupled to the output terminal of the DAC circuitry (DAC 216), the input of the first amplifier circuitry (input of amplifier of 224) , and the first terminal of the capacitor (first terminal of capacitor of 224), the second terminal of the resistor (second terminal of Resistor of 224) is coupled to the output of the amplifier circuitry (output of amplifier of 224) , the input of the second inter-stage gain circuitry (input of second stage 220) , and the second terminal of the capacitor (second terminal of capacitor of 224).
Zhao et al. and Manganaro et al. are common subject matter pipelined ADC apparatus; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Manganaro et al. into Zhao et al. for the purpose of providing filter to sufficiently suppress the DAC output images caused by the synchronous clocked operation, in practice, a higher-order filter, such as a second, or third order filter is often preferred or even required (paragraph 0029 of Manganaro et al.).
Contact Information
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
02/20/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845