Office Action Predictor
Last updated: April 16, 2026
Application No. 18/790,610

UNIVERSAL SERIAL BUS TYPE C CABLE PERFORMANCE

Non-Final OA §103
Filed
Jul 31, 2024
Examiner
MYERS, PAUL R
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Dell Products L.P.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
91%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
606 granted / 768 resolved
+23.9% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
19 currently pending
Career history
787
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
64.7%
+24.7% vs TC avg
§102
13.0%
-27.0% vs TC avg
§112
8.0%
-32.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 768 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 7, 9-11, 15, 17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Randazzo et al PN 2023/0187922 in view of Moritomo et al PN 2020/0004308. In regards to claims 1, 9, 17: Randazzo et al a power system comprising: a power supply (Batt 108 figure 1 (the examiner notes all figures and the specification identifies the battery as 108 and the cable as 102 while figure 2 identifies the battery as 102)) to provide a current to an output terminal (OUT into cable 102) of the power system; and a power delivery integrated circuit (PD IC) (electronic fuse 110) coupled to the power supply (108), the PD IC to: initiate a first voltage (voltage into Sense_P) ([0062] “For example, the system 100 may monitor electrical characteristics (e.g., current, voltage, or the like) between a power supply 108 and a load 106, and may protect the load 106 from overcurrent conditions that otherwise may cause damage to the load 106.”) across a first resistor (shunt resistor Rsht ) of a first information handling system; monitor a second voltage (voltage out of shunt resistor Sense_N) at a voltage pin (OUT) of a power cable (102), wherein the power cable (102) is connected between the power system and a load (load 106); compare the second voltage at the voltage pin to a threshold voltage level ([0009] “In some embodiments, the current may be immediately switched off if the current exceeds a threshold that is associated with immediate action (e.g., a threshold that represents current not be exceeded for any duration of time).” Randazzo et al teaches measuring “e.g., current, voltage, or the like” when measuring current the measurement would be compared to a current threshold, when measuring voltage the measurement would be compared to a voltage threshold); and in response to the second voltage being greater than the threshold voltage level, perform a power source fault operation ([0065] “When an overload condition occurs, the electronic fuse 110 limits the output current to a safe value, which in some embodiments may be defined by a user. If the overload condition persists, the electronic fuse 110 may control a switching element 104 to go into a non-conductive or open state, thereby electrically disconnecting the load 106 from the power supply 108.”). Randazzo et al does not state the power system includes a power adapter or that the load is an information handling system. Moritomo et al teaches a power adapter ([0034] “ It is assumed that the power transmission apparatus is equipped in an AC adapter that receives a power supply from an AC power supply unit and supplies power to the power receiving apparatus, the power transmission apparatus may be equipped in an information processing apparatus such as a personal computer as well.”) that includes an over voltage/over current detection unit 106 that is connected to a terminal of a power cable ([0003] “A device compliant with USB Power Delivery (“USB-PD” hereinafter) can supply a maximum of 100 W of power over a USB cable, from a power transmission apparatus such as a USB host device or an AC adapter to a power receiving apparatus on the power receiving side.”) that supplies power to an information processing unit ([0055] “For example, if the power receiving apparatus 20 is a digital camera, the central control unit 207 controls an image capturing unit, an image processing circuit, and the like (not shown) using ROM storing programs, RAM used as a work area, and the like. However, this processing is not the main focus of the present invention, and thus details thereof will be omitted here”). Moritomo et al also teaches detecting overvoltage (voltage above a threshold [0044] “The detecting unit 106 is configured to be capable of detecting an error when the output state of the VBUS power, output by the power transmission apparatus 10, is in a state of overvoltage or of overcurrent”). Moritomo et al further teaches fault operation ([0008] “When the detection circuit detects an error, the output of the power source is stopped”) Moritomo et al even teaches a detection resistor ([0044] “For example, the detecting unit 106 may be constituted by a detection resistor or an instrument amplifier so as to be capable of detecting an overcurrent state for VBUS”. Moritomo et al however does not expressly state measuring the voltage into the resistor and voltage out of the resistor for determine overvoltage/overcurrent. It would been obvious to either measure the voltage across the ”detection resistor” of Moritomo et al as in Randazzo et al because this is how over voltage is measured or to include a power adapter and allow the load to be a information handling system in Randazzo et al as in Moritomo et al because power adapters and information processing systems are ubiquitous. In regards to claims 2, 10: both Randazzo et al and Moritomo et al teach shutting down the power source which in Moritomo et al is an adapter. In regards to claims 3, 11: Moritomo et al teaches a notifying unit ([0047] “For example, if the notifying unit 107 includes a light-emitting element such as a light-emitting diode, an operating/non-operating state can be represented visually by lighting and extinguishing the light-emitting element, and a state different from both the operating/non-operating states can be represented by flashing the light-emitting element. The notifying means of the notifying unit 107 is not limited to a light-emitting diode, and may be any means capable of notifying the user.”). In regards to claims 7, 15, 19: Moritomo et al teaches detecting a plugging/connection ([0041] “The PD communication control unit 102 is configured to be capable of detecting a connection with an external device using the CC1 terminal and the CC2 terminal, and communicating with the external device on the basis of the USB Power Delivery standard (“USB-PD standard” hereinafter)”). Moritomo et al teaches applying a voltage across a second resistor (pull-up resistor 104 or 105) and monitoring voltages at pins CC1 and CC2 (by monitoring unit 109 [0048] “The monitoring unit 109 monitors the voltage values at the CC1 terminal and the CC2 terminal”). Determining if the power cable connection is good if the voltage is in the range of .85V to 2.45V and not good if it is outside that range. [0049] “For example, if the resistance value of the first variable resistance element 104 and the second variable resistance element 105 is set on the basis of an instruction from the resistance control unit 108 so that Rp′=5.1 kΩ, at least one of the CC1 terminal and the CC2 terminal will be at 2.5 V, which is outside the connection determination range of from 0.85 V to 2.45 V”) in accordance with the USB-PD standard. Claim(s) 4-5, 12-13, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Randazzo et al PN 2023/0187922 in view of Moritomo et al PN 2020/0004308 as applied to claim 1 above, and further in view of Oba et al PN 6,343,498. In regards to claims 4, 12, 18: Neither Randazzo et al nor Moritomo et al teach the reason for the fault only detecting the fault. Moritomo et al does teach changing resistances in the CC lines but these are not the cause of the fault. Oba et al teaches (Column 1 line 50 et seq. “However, a poor connection (failure in connection) at a connection point between the control portion 10 and the sensor portion 20 may cause a fault due to an increase of a resistance of the line.”). It would have been obvious to detect the fault for any reason including an increase of resistance in the line because this would have prevented limiting the faults detected. In regards to claims 5, 13: Oba et al teaches a small break (“failure in connection”). Claim(s) 6, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Randazzo et al PN 2023/0187922 in view of Moritomo et al PN 2020/0004308 as applied to claim 1 above, and further in view of Fukumori PN 2006/0190747. In regards to claims 6, 14: Moritomo et al teaches detecting the fault and notifying the fault. Neither Randazzo et al nor Moritomo et al teach storing the power fault condition. Fukumori teaches ([0069] “The MP, concerning to the control at power failure and recovery, carries out blocking process to shift the objective portion to the blocked condition, process to judge and store the power failure condition, recovery process to release the blocked condition and recover normal condition, and so forth”). It would have been obvious to store failure conditions because this would have allowed for failure analysis. Claim(s) 8, 16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Randazzo et al PN 2023/0187922 in view of Moritomo et al PN 2020/0004308 as applied to claim 9 above, and further in view of Shofner, II PN 2019/0341709. In regards to claims 8, 16, 20: Moritomo et al teaches on off and flashing states of the LED to indicate the status of the power on the cable. Moritomo et al does not teach different colours indicating status. Shofner, II teaches ([0046] “FIGS. 15-16 show additional embodiments of the cable 2. The connector housing 16 may include a light 20, such as an LED light, that signals a status of the cable 2 during use. For example, the light 20 may illuminate in a plurality of colors based on a status of the cable (such as whether a sufficient charge is passing through the cable or whether a connection has been established)”). It would have been obvious to use a color indicating the cable status is good because this is a simple indication for people that are not color blind. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL R MYERS whose telephone number is (571)272-3639. The examiner can normally be reached telework M-F start 7-8 leave 4-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Paul R. MYERS/Primary Examiner, Art Unit 2176
Read full office action

Prosecution Timeline

Jul 31, 2024
Application Filed
Feb 06, 2026
Non-Final Rejection — §103
Mar 06, 2026
Interview Requested
Mar 16, 2026
Applicant Interview (Telephonic)
Mar 16, 2026
Examiner Interview Summary
Mar 30, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12591288
CONTROL METHOD FOR DETECTING SYSTEM, DETECTING SYSTEM AND VEHICLE
2y 5m to grant Granted Mar 31, 2026
Patent 12585477
AUTOMATED GENERATION AND EXECUTION OF APPLICATION PROGRAMMING INTERFACE CALLS
2y 5m to grant Granted Mar 24, 2026
Patent 12572487
I/O UNIT, MASTER UNIT, AND COMMUNICATIONS SYSTEM
2y 5m to grant Granted Mar 10, 2026
Patent 12561263
I/O UNIT
2y 5m to grant Granted Feb 24, 2026
Patent 12554307
PRESENCE DETECTION POWER EFFICIENCY IMPROVEMENTS
2y 5m to grant Granted Feb 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
91%
With Interview (+12.1%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 768 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in for Full Analysis

Enter your email to receive a magic link. No password needed.

Free tier: 3 strategy analyses per month