DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This Action is in response to communications filed 01/07/2026.
Claims 1, 5, 7, 10-13, 15, 17, and 20 have been amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Response to Arguments
In Remarks filed on 01/07/2026, Applicant substantially argues:
On Pages 13-14, the applied references, including Kim, Tan, and Kavalieros, fail to disclose the amended limitations of claim 1, and similarly amended claims 13 and 17, involving the plurality of columns of memory cells which comprise at least one column of access counters are formed on the same semiconductor die. As noted by the Applicant and discussed in the Interview Summary dated 12/22/2025, the references of record do not explicitly address the form of the semiconductor die as now claimed. Applicant’s arguments filed have been fully considered but are moot in view of the current rejection made in response to Applicant’s amendments.
On Pages 13-14, the applied references fail to disclose the limitations of dependent claims 2-12, 14-16, and 18-20 by virtue of dependency on respective independent claims 1, 13, and 17 for the reasons identified above. Applicant’s arguments filed have been fully considered but are moot in view of the current rejection made in response to Applicant’s amendments.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated January 7, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0205428) in view of Willcock (US 2018/0088850).
Regarding claim 1, Kim discloses, in the italicized portions, an apparatus comprising: a semiconductor die comprising: at least one memory array comprising: a plurality of columns of memory cells (Figure 2, Memory cell array 200, plurality of bitlines); and at least one column of access counters ([0049] The first memory cells 410 connected to each of the word lines WL1 to WLm may include preset counter memory cells C110 to C117 storing the number of times of access of the corresponding word lines WL1 to WLm of the data chips 110 to 117. For example, the counter memory cells C110 to C117 connected to the first word line WL1 may store the number of times of access for activating the memory cell row of the first word line WL1 of each of the data chips 110 to 117.); and a column decoder coupled to the at least one memory array and configured, based on at least one input signal, to individually select: a column of the plurality of columns of memory cells; and the at least one column of access counters ([0039] The column decoder 206 may select preset bit lines BL from among a plurality of bit lines BL of the memory cell array 200. The column decoder 206 may generate a column selection signal by decoding a burst address that is gradually increased by +1 based on the column address COL_ADDR in the burst mode, and connect the bit lines BL selected by the column selection signal to the I/O gating circuit 208. [0040] The I/O gating circuit 208 may include read data latches for storing read data of the bit lines BL selected by the column select signal, and a write driver for writing write data into the memory cell array 200.). Herein Kim teaches a memory device comprising a memory array including a plurality of banks wherein the banks include a plurality of word lines WL and bit lines BL, which are analogous to rows and columns. The memory array further includes memory cells storing access counters for respective rows. Additionally, Kim recites a column decoder generating column selection signals to respective columns based on the received access command. In this manner, a respective bit line, storing either data or the access counter, may be accessed for the corresponding word line, or row. The Examiner acknowledges Kim does not explicitly recite the elements of the memory array, column decoding circuitry, and the column of access counters as comprising a semiconductor die. Regarding this aspect of the limitation, Willcock discloses in Paragraphs [0029-30] “[0029] For example, the updated indicators may be written to a designated location in a column of memory cells corresponding to the appropriate data category. As such, the PIM circuitry used for storage of the indicators in the designated columns may be column oriented. Accordingly, the PIM circuitry may, in some embodiments, not support shifting of data to the right or left in the array, e.g., to limit impact of the PIM circuitry on the die area. The PIM circuitry on the DRAM device also may be controlled, e.g., by the controller, to change counts of the updated indicators in designated counters corresponding to the appropriate columns. [0030] In some embodiments, the counters may be formed as part of the array 130, e.g., as shown and described in connection with counters 136 in FIG. 1B, and may be selectably coupled to one of the plurality of designated subsets of memory cells. For example, the counters also may be oriented in columns, e.g., designated to the appropriate columns 122 in a corresponding DRAM array, which may enable efficient changes of counts by the column oriented PIM circuitry.” Herein Willcock explicitly identifies that access counters may be formed as a respective column in the memory array for tracking changes in access counts to the corresponding portion of the array. This is further depicted in Figure 1B wherein the counters are formed as part of the array 130. Additionally, Willcock Paragraph [0032] refers to the memory device 120-1 as being capable of being formed in the same chip or die as a single integrated circuit. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the column of access counters in the memory array on the same die as the memory array and column decoder circuitry in order to reduce system space requirements and reduce power consumption (Willcock [0019]). Kim and Willcock are analogous art because they are from the same field of endeavor of controlling memory array access.
Regarding claim 2, Kim further discloses the apparatus of claim 1, wherein: the column decoder is configured to select the column of the plurality of columns of memory cells based on a first input signal; and the column decoder is configured to select the at least one column of access counters based on a second input signal ([0039] The column decoder 206 may select preset bit lines BL from among a plurality of bit lines BL of the memory cell array 200. The column decoder 206 may generate a column selection signal by decoding a burst address that is gradually increased by +1 based on the column address COL_ADDR in the burst mode, and connect the bit lines BL selected by the column selection signal to the I/O gating circuit 208. [0049] The first memory cells 410 connected to each of the word lines WL1 to WLm may include preset counter memory cells C110 to C117 storing the number of times of access of the corresponding word lines WL1 to WLm of the data chips 110 to 117. For example, the counter memory cells C110 to C117 connected to the first word line WL1 may store the number of times of access for activating the memory cell row of the first word line WL1 of each of the data chips 110 to 117.). Here Kim explicitly notes the column decoder selects columns as directed by the column address submitted to it. In this manner, each column is represented by a distinct signal that constitutes a first input signal or second input signal as claimed for accessing memory cells storing either data or an access counter.
Claims 3, 13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Willcock and further in view of Tan et al. (US 2024/0361916).
Regarding claim 3, Kim and Willcock do not explicitly disclose the apparatus of claim 2, wherein the column decoder is configured to deselect the plurality of columns of memory cells based on the second input signal. Regarding this limitation, Tan discloses in Paragraph [0062] “Column decoder/bit line driver 408 can be configured to be controlled by the address signals from control logic 412 and select/deselect one or more columns of SCM cells in SCM cell array 404 by applying bit line voltages to the corresponding bit lines. Column decoder/bit line driver 408 can be further configured to drive the selected bit line(s).” Herein Tan explicitly notes the column decoder, in response to address signals supplied by the control logic, controls selecting and deselecting columns of the memory array. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that columns of cells are deselected in order to select another column of cells for access based on address signals sent to the column decoder as noted by Tan and therefore the decoder and drivers present in Kim may be modified to perform the same functions of selecting and deselecting columns to achieve the same known result of controlling access to the memory array. Kim, Willcock, and Tan are analogous art because they are from the same field of endeavor of controlling memory array access.
Regarding claim 13, Kim discloses, in the italicized portions, a method performed by a semiconductor die, the method comprising: receiving, at a column decoder coupled to at least memory array of the semiconductor die, at least one input signal; deselecting, at least partially by the column decoder, a plurality of columns of memory cells of the at least one memory array based on the at least one input signal; selecting, by the column decoder, a column of access counters of the at least one memory array based on the at least one input signal; and accessing, with an access counter driver, the selected column of access counters ([0039] The column decoder 206 may select preset bit lines BL from among a plurality of bit lines BL of the memory cell array 200. The column decoder 206 may generate a column selection signal by decoding a burst address that is gradually increased by +1 based on the column address COL_ADDR in the burst mode, and connect the bit lines BL selected by the column selection signal to the I/O gating circuit 208. [0040] The I/O gating circuit 208 may include read data latches for storing read data of the bit lines BL selected by the column select signal, and a write driver for writing write data into the memory cell array 200.). Herein Kim teaches a memory device comprising a memory array including a plurality of banks wherein the banks include a plurality of word lines WL and bit lines BL, which are analogous to rows and columns. The memory array further includes memory cells storing access counters for respective rows. Additionally, Kim recites a column decoder generating column selection signals to respective columns based on the received access command. In this manner, a respective bit line, storing either data or the access counter, may be accessed for the corresponding word line, or row. The Examiner acknowledges Kim does not explicitly recite the elements of the memory array, column decoding circuitry, and the column of access counters as comprising a semiconductor die. Regarding this aspect of the limitation, Willcock discloses in Paragraphs [0029-30] that access counters may be formed as a respective column in the memory array for tracking changes in access counts to the corresponding portion of the array. This is further depicted in Figure 1B wherein the counters are formed as part of the array 130. Additionally, Willcock Paragraph [0032] refers to the memory device 120-1 as being capable of being formed in the same chip or die as a single integrated circuit. Kim and Willcock do not explicitly disclose the limitation including deselecting, at least partially by the column decoder, a plurality of columns of memory cells based on at least one input signal. Regarding this limitation, Tan discloses in Paragraph [0062] “Column decoder/bit line driver 408 can be configured to be controlled by the address signals from control logic 412 and select/deselect one or more columns of SCM cells in SCM cell array 404 by applying bit line voltages to the corresponding bit lines. Column decoder/bit line driver 408 can be further configured to drive the selected bit line(s).” Herein Tan explicitly notes the column decoder, in response to address signals supplied by the control logic, controls selecting and deselecting columns of the memory array. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that columns of cells are deselected in order to select another column of cells for access based on address signals sent to the column decoder as noted by Tan and therefore the decoder and drivers present in Kim may be modified to perform the same functions of selecting and deselecting columns to achieve the same known result of controlling access to the memory array.
Regarding claim 15, Kim, Willcock, and Tan in combination further disclose the method of claim 13, further comprising: reading, with the access counter driver, usage-based-disturbance data from the selected column of access counters; transmitting, on input/output lines of the semiconductor die, the usage-based-disturbance data to an activation count update unit; updating, with the activation count update unit, the usage-based-disturbance data; transmitting, on the input/output lines, the updated usage-based-disturbance data to the access counter driver; and writing, with the access counter driver, the updated usage-based-disturbance data to the selected column of access counters (Kim [0039-40] and Tan [0062]). Herein Kim and Tan disclose the elements which access and transmit data between the control elements and memory array. These include respective row and column drivers to access the targeted word line and bit line, signal lines, and control logic which monitors the counters which may be formed on the same die as discussed by Willcock.
Regarding claim 16, Kim, Willcock, and Tan in combination further disclose the method of claim 15, further comprising: receiving, at the column decoder, a read or write command; selecting, by the column decoder, a column of the plurality of columns of memory cells responsive to the read or write command; and accessing, with a driver, the selected column of the plurality of columns of memory cells based on the read or write command (Kim [0038-39] and Tan [0062]). Herein both Kim and Tan disclose column decoders generated column selection signals to access target bit lines.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Willcock and further in view of Tan and still further in view of Ahmed et al. (US 2012/0117306).
Regarding claim 4, Kim discloses, in the italicized portions, the apparatus of claim 3, wherein: the first input signal is based on a read or write operation command ([0039]); and the second input signal is based on a precharge command. Herein Kim discloses accessing column locations based on read or write commands. Kim, Willcock, and Tan do not explicitly disclose a second input signal based on a precharge command. Regarding this aspect of the limitation, Ahmed discloses in Paragraphs [0024] and [0028] that bit lines are selected or deselected in response to access commands. Specifically, Paragraph [0028] recites the sense amplifier 203 processing a precharge operation to precharge a bit line prior to performing a sense operation. In this manner, in view of Kim wherein accessing bit lines either storing data or an access counter, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second input signal which selects a column of access counter may be in the form of a precharge command as is performed in Ahmed prior to accessing any bit line. Kim, Willcock, Tan, and Ahmed are analogous art because they are from the same field of endeavor of controlling memory array access.
Claims 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Willcock and further in view of Tan and still further in view of Kavalieros et al. (US 2019/0205273).
Regarding claim 5, Kim, Willcock, and Tan do not explicitly disclose the apparatus of claim 3, wherein the semiconductor die further comprises: multiple drivers coupled to the column decoder, the multiple drivers configured to: read data from the memory cells of the column selected by the column decoder; and write data to the memory cells of the column selected by the column decoder. The Examiner notes Willcock does disclose the form of the memory array and corresponding access circuitry on the same die, but not at the specific level of detail as claimed. Regarding this limitation involving the multiple drivers, Kavalieros discloses in Paragraph [0063] “Memory device 300 may further comprise circuitry AL.sub.1 302 and circuitry AL.sub.2 312 which, for example, are to provide memory access functionality such as that of access logic 112. By way of illustration and not limitation, AL.sub.1 302 may comprise a first column decoder and first row decoder to variously operate bit lines and word lines (respectively) of MA.sub.1 303. AL.sub.1 302 may further comprise sense amplifiers, driver circuits, pre-charge circuits and/or other such circuitry to enable data writes to and/or data reads from MA.sub.1 303. Similarly, AL.sub.2 312 may comprise a second column decoder and second row decoder (and in some embodiments, sense amplifiers, driver circuits, pre-charge circuits and/or the like) to variously communicate signals with memory cells of MA.sub.2 313.” Here Kavalieros discloses a plurality of supplementary circuits for accessing memory cells in the memory device. This includes multiple drivers to read from and write to data of the corresponding memory cells. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to supply the plurality of driver circuits as taught be Kavalieros in the memory device as disclosed by Kim in order to take advantage of the plurality of I/O path functionality for accessing the memory array (Kavalieros [0068]). Kim, Willcock, Tan, and Kavalieros are analogous art because they are from the same field of endeavor of controlling memory array access.
Regarding claim 6, Kim, Willcock, and Kavalieros in combination further disclose the apparatus of claim 5, wherein the column decoder is configured to couple, based on the first input signal, at least one of the multiple drivers to the selected column of the plurality of columns of memory cells (Kim [0039-40] and Kavalieros [0073]). As Kim discloses controlling read and write drivers to access target bit lines, Kavalieros additionally supports the coupling of at least one among a plurality of driver circuits to service an access command to the target bit line.
Regarding claim 7, Kim, Willcock, and Kavalieros in combination further disclose the semiconductor die of claim 6, wherein the memory device further comprises: an access counter driver coupled to the column decoder, the access counter driver configured to access the at least one column of access counters responsive to being selected by the column decoder (Kim [0039-40] and [0049]). Herein the column decoder and coupled driver for accessing the memory array are determined to be analogous to the access counter driver as the memory cells containing the access counters may be accessed by the control logic via the decoded signals. Furthermore, as previously indicated, Willcock discloses forming these elements on the same die.
Regarding claim 8, Kim, Willcock, and Kavalieros in combination further disclose the apparatus of claim 7, wherein the column decoder is configured to couple, based on the second input signal, the access counter driver to the at least one column of access counters (Kim [0039-40] and [0049] and Kavalieros [0073]). As similarly noted in the rejections of claims 6 and 7, the target bit line or column may be accessed by the driver via the signal generated by the column decoder.
Regarding claim 9, Kim, Willcock, and Kavalieros in combination further disclose the apparatus of claim 7, wherein the access counter driver is configured to access usage-based-disturbance data from the at least one column of access counters (Kim [0049]). Herein Kim identifies the memory cells store access counters for the corresponding word line which represents the number of times of access for activating the memory cell row of the word line. These activations are analogous to the usage-based-disturbance data as determined under the broadest reasonable interpretation of the term.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Willcock and further in view of Bhatia et al. (US 2015/0228312).
Regarding claim 10, Kim and Willcock in combination further disclose, in the italicized portions, the apparatus of claim 1, wherein the semiconductor die further comprises: an access counter driver coupled to the column decoder and configured to access the at least one column of access counters (Kim [0039-40] and Willcock [0029]); and a logic gate coupled to an inverter of the access counter driver and configured to provide a virtual ground for the inverter based on the at least one input signal. Herein Kim discloses the column decoder and coupled driver for accessing the memory array are determined to be analogous to the access counter driver as the memory cells containing the access counters may be accessed by the control logic via the decoded signals. Kim and Willcock do not explicitly disclose the logic gate coupled to an inverter of the driver and configured to provide a virtual ground for the inverter based on at least one input signal. Regarding this aspect of the limitation, Bhatia discloses in Paragraphs [0130-133] and accompanying Figure 14 the structure of the write driver including logic gates and inverters in order to couple ground to virtual ground. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement this structure in the driver to accessing the memory array in order to provide the functionality of assisting access to the memory array, when indicated by a signal, by adjusting the voltage supplied during the driver access. Kim, Willcock, and Bhatia are analogous art because they are from the same field of endeavor of controlling memory array access.
Regarding claim 11, Kim and Willcock in combination further disclose the apparatus of claim 10, wherein: the semiconductor die further comprises a logic portion coupled to the access counter driver via input/output lines (Figure 2, Control logic circuit 220), the logic portion comprising: a first data sense amplifier; a first write driver; and an activation count update unit coupled to the first data sense amplifier and the first write driver ([0036] and [0040] Control logic accessing bit lines via sense amplifiers), the activation count update unit configured to receive usage-based-disturbance data and increment the usage-based-disturbance data ([0040-42] Control logic circuit accessing memory cells storing access counters); the input/output lines and the first data sense amplifier are configured to deliver usage-based-disturbance data of the at least one column of access counters from the access counter driver to the activation count update unit; and the first write driver and the input/output lines are configured to deliver incremented usage-based-disturbance data to the at least one column of access counters, via the access counter driver, from the activation count update unit ([0036-42] Control logic provide control signals to send in the memory device including access commands such as read and write via the decoders and amplifiers). Herein Kim discloses the structure wherein processing in the memory device is managed by the control logic and includes accessing data stored in memory cells via addresses processed by the row and column decoders to identify the word line and bit line position of the target access. This would include reading from and writing to the memory cells storing the access counters. Furthermore, as previously indicated, Willcock discloses forming these elements on the same die.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Willcock and further in view of Bhatia and still further in view of Kavalieros.
Regarding claim 12, Kim, Willcock, and Bhatia do not explicitly disclose the apparatus of claim 11, wherein: the semiconductor die further comprises multiple drivers coupled to the column decoder and configured to access the selected column of the plurality of columns of memory cells; the logic portion is coupled to the multiple drivers via the input/output lines; the logic portion further comprises: a second data sense amplifier; a second write driver; and a data path coupled to the second data sense amplifier and the second write driver; the input/output lines, the second data sense amplifier, and the data path are configured to read data, via at least one driver of the multiple drivers, from the selected column of the plurality of columns of memory cells; and the data path, the second write driver, and the input/output lines are configured to write data, via at least one driver of the multiple drivers, to the selected column of the plurality of columns of memory cells. The Examiner notes, as presented in the rejection of claim 11, that the elements claimed are present in Kim including drivers to read and write data to the memory array, decoders to generate target addresses, sense amplifiers to sense and amplify data, and the corresponding I/O lines which transmit data between elements. Kim, Willcock, and Bhatia do not explicitly address the duplication of these elements wherein the duplicated elements perform similar functions. Regarding this aspect of the limitation, Kavalieros discloses in Paragraph [0063] that a memory device may have multiple circuits comprising the same elements performing similar functions to access different portions of the memory device. It would be obvious to one of ordinary skill in the art to implement the duplication of parts for performing similar functions as there is no evidence of new or unexpected results produced from using the multiple parts that would otherwise distinguish the limitations over the teachings of the art. Kim, Willcock, Bhatia, and Kavalieros are analogous art because they are from the same field of endeavor of controlling memory array access.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Willcock and further in view of Tan and still further in view of Bhatia.
Regarding claim 14, Kim, Willcock, and Tan do not explicitly disclose the method of claim 13, further comprising: generating a virtual ground to the access counter driver based on the at least one input signal. Kim does not explicitly disclose generating a virtual ground based on at least one input signal. Regarding this aspect of the limitation, Bhatia discloses in Paragraphs [0130-133] and accompanying Figure 14 the structure of the write driver including logic gates and inverters in order to couple ground to virtual ground. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement this structure in the driver to accessing the memory array in order to provide the functionality of assisting access to the memory array, when indicated by a signal, by adjusting the voltage supplied during the driver access. Kim, Willcock, Tan, and Bhatia are analogous art because they are from the same field of endeavor of controlling memory array access.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Willcock and further in view of Kavalieros.
Regarding claim 17, Kim discloses, in the italicized portions, an apparatus comprising: a semiconductor die comprising: at least one memory array comprising: a plurality of columns of memory cells; and at least one column of access counters (Figure 2, Memory cell 200, plurality of bitlines); multiple drivers configured to access the plurality of columns of memory cells; an access counter driver configured to access the at least one column of access counters; and a column decoder coupled to the at least one memory array, the multiple drivers, and the access counter driver, the column decoder configured, based on at least one input signal, to individually select: a column of the plurality of columns of memory cells; and the at least one column of access counters ([0039-40]). Herein Kim teaches a memory device comprising a memory array including a plurality of banks wherein the banks include a plurality of word lines WL and bit lines BL, which are analogous to rows and columns. The memory array further includes memory cells storing access counters for respective rows. Additionally, Kim recites a column decoder generating column selection signals to respective columns based on the received access command. In this manner, a respective bit line, storing either data or the access counter, may be accessed for the corresponding word line, or row. The Examiner acknowledges Kim does not explicitly recite the elements of the memory array, column decoding circuitry, and the column of access counters as comprising a semiconductor die. Regarding this aspect of the limitation, Willcock discloses in Paragraphs [0029-30] that access counters may be formed as a respective column in the memory array for tracking changes in access counts to the corresponding portion of the array. This is further depicted in Figure 1B wherein the counters are formed as part of the array 130. Additionally, Willcock Paragraph [0032] refers to the memory device 120-1 as being capable of being formed in the same chip or die as a single integrated circuit. Kim and Willcock do not explicitly disclose the presence of multiple drivers for accessing the plurality of columns of memory cells. Regarding this aspects of the limitation, Kavalieros discloses in Paragraph [0063] “Memory device 300 may further comprise circuitry AL.sub.1 302 and circuitry AL.sub.2 312 which, for example, are to provide memory access functionality such as that of access logic 112. By way of illustration and not limitation, AL.sub.1 302 may comprise a first column decoder and first row decoder to variously operate bit lines and word lines (respectively) of MA.sub.1 303. AL.sub.1 302 may further comprise sense amplifiers, driver circuits, pre-charge circuits and/or other such circuitry to enable data writes to and/or data reads from MA.sub.1 303. Similarly, AL.sub.2 312 may comprise a second column decoder and second row decoder (and in some embodiments, sense amplifiers, driver circuits, pre-charge circuits and/or the like) to variously communicate signals with memory cells of MA.sub.2 313.” Here Kavalieros discloses a plurality of supplementary circuits for accessing memory cells in the memory device. This includes multiple drivers to read from and write to data of the corresponding memory cells. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to supply the plurality of driver circuits as taught be Kavalieros in the memory device as disclosed by Kim in order to take advantage of the plurality of I/O path functionality for accessing the memory array (Kavalieros [0068]). Kim, Willcock, and Kavalieros are analogous art because they are from the same field of endeavor of controlling memory array access.
Regarding claim 18, Kim further discloses the apparatus of claim 17, wherein the access counter driver is configured to: read usage-based-disturbance data from the at least one column of access counters; and transmit the usage-based-disturbance data to an activation count update unit ([0039-42]). Herein Kim discloses the control logic circuit 220, determined analogous to the activation count update unit, accessing the counters stored in the memory array via the column decoder.
Regarding claim 19, Kim further discloses the apparatus of claim 18, wherein: the activation count update unit is selectively coupled with the access counter driver and configured to increment usage-based-disturbance data received from the access counter driver ([0039-42]). Herein Kim discloses the control logic maintaining the access counters stored in the memory cells which may be incremented based on the commands processed by the control logic and row and column decoders to indicate a particular memory cell has been accessed.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Willcock and further in view of Kavalieros and still further in view of Bhatia.
Regarding claim 20, Kim, Willcock, and Kavalieros do not explicitly disclose the apparatus of claim 19, wherein the semiconductor die further comprises: a logic gate coupled to an inverter of the access counter driver and configured to provide a virtual ground for the inverter based on the at least one input signal. Regarding this aspect of the limitation, Bhatia discloses in Paragraphs [0130-133] and accompanying Figure 14 the structure of the write driver including logic gates and inverters in order to couple ground to virtual ground. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement this structure in the driver to accessing the memory array in order to provide the functionality of assisting access to the memory array, when indicated by a signal, by adjusting the voltage supplied during the driver access. Kim, Willcock, Kavalieros, and Bhatia are analogous art because they are from the same field of endeavor of controlling memory array access.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wu et al. (US 2018/0366204) – Paragraph [0042] wherein maintaining column access counters is discussed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
Prosecution Insights