DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/06/26 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, 9-11, 13-14, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Herbert (US 2008/0164957; reference of record). NOTE: There is a drafting error in figure 2 of Herbert. A connecting line is missing between the left terminal of inductor L1, the left terminal of capacitor C1, the drain terminal of transistor T4a, and the gate terminal of transistor T4b.
Regarding claim 1, Herbert teaches an apparatus (figure 2) comprising:
first current source circuitry (Rt4) having a terminal (upper terminal);
second current source circuitry (Rt1, TS1) having a terminal (upper terminal);
a first transistor (T4a) having a first terminal, a second terminal, and a control terminal (see figure 2);
a second transistor (T4b) having a first terminal, a second terminal, and a control terminal (see figure 2), the first terminal of the second transistor (T4b) coupled to the terminal of the first current source circuitry (Rt4) and the first terminal of the first transistor (T4a);
a third transistor (T1a) having a first terminal, second terminal, and a control terminal (see figure 2);
a fourth transistor (T1b) having a first terminal, a second terminal, and a control terminal (see figure 2), the first terminal of the fourth transistor (T1b) coupled to the terminal of the second current source circuitry (Rt1, TS1) and the first terminal of the third transistor (T1a); and
inductor circuitry (L1, L2) having a first terminal (left terminal of L1) and a second terminal (right terminal of L2), the first terminal of the inductor circuitry (L1, L2) coupled to the second terminal of the first transistor (T4a), the control terminal of the second transistor (T4b), the second terminal of the third transistor (T1a), and the control terminal of the fourth transistor (T1b), the second terminal of the inductor circuitry (L1, L2) coupled to the control terminal of the first transistor (T4a), the second terminal of the second transistor (T4b), the control terminal of the third transistor (T1a), and the second terminal of the fourth transistor (T1b).
As for claim 2, Herbert teaches wherein the inductor circuitry (L1, L2) includes
a first inductor (L1) having a first terminal and a second terminal, the first terminal of the first inductor (L1) is coupled to the second terminal of the first transistor (T4a), the control terminal of the second transistor (T4b), the second terminal of the third transistor (T1a), and the control terminal of the fourth transistor (T1b); and
a second inductor (L2) having a first terminal and a second terminal, the first terminal of the second inductor (L2) is coupled to the control terminal of the first transistor (T4a), the second terminal of the second transistor (T4b), the control terminal of the third transistor (T1a), and the second terminal of the fourth transistor (T1b), the second terminal of the second inductor (L2) is coupled to the second terminal of the first inductor (L1).
Regarding claim 3, Herbert teaches a first resistor (Rg1) having a first terminal and a second terminal, the first terminal of the first resistor (Rg1) is coupled to the second terminal of the first transistor (T4a), the control terminal of the second transistor (T4b), the second terminal of the third transistor (T1a), the control terminal of the fourth transistor (T1b), and the first terminal of the first inductor (L1), the second terminal of the first resistor (Rg1) is coupled to the second terminal of the first inductor (L1); and
a second resistor (Rg2) having a first terminal and a second terminal, the first terminal of the second resistor (Rg2) is coupled to the control terminal of the first transistor (T4a), the second terminal of the second transistor (T4b), the control terminal of the third transistor (T1a), the second terminal of the fourth transistor (T1b), and the first terminal of the second inductor (L2), the second terminal of the second resistor (Rg2) is coupled to the second terminal of the second inductor (L2).
Regarding claim 4, Herbert teaches a third resistor (Rt4) having a first terminal and a second terminal, the first terminal of the third resistor (Rt4) is coupled to the second terminal of the first inductor (L1) and the second terminal of the second inductor (L2), the second terminal of the third resistor (Rt4) is coupled to the second terminal of the first resistor (Rg1) and the second terminal of the second resistor (Rg2).
As for claim 5, Herbert teaches wherein the first current source circuitry includes a fifth transistor (Para. [0055] teaches amplifier AB being switchable similarly to amplifiers AS) having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor is coupled to the first terminal of the first transistor (T4a) and the first terminal of the second transistor (T4b), the second current source circuitry includes a sixth transistor (TS1) having a first terminal and a control terminal, the first terminal of the sixth transistor (TS1) is coupled to the first terminal of the third transistor T1a) and the first terminal of the fourth transistor (T1b), the second terminal of the sixth transistor (TS1) coupled to the second terminal of the fifth transistor, the control terminal of the sixth transistor coupled to the control terminal of the fifth transistor (Para. [0055] teaches amplifier AB being switchable similarly to amplifiers AS, which receive switching voltage Vs).
As for claim 7, Herbert teaches wherein the first (T4a) and second (T4b) transistors have a first threshold voltage and a first transconductance (inherent properties of transistors), the third (T1a) and fourth (T1b) transistors have a second threshold voltage and a second transconductance (inherent properties of transistors), the first threshold voltage is greater than the second threshold voltage (The threshold voltages are related to the transistor channel width/length ratios discussed in para. [0039], [0042], [0044], [0046]), and the first transconductance is greater than the second transconductance (The transconductances are related to the transistor channel width/length ratios discussed in para. [0039], [0042], [0044], [0046]).
Regarding claim 9, Herbert teaches an apparatus (figure 2) comprising:
first oscillator circuitry (AB) having a first terminal (drain of T4a), a second terminal (drain of T4b), and including a first transistor (T4a) having a first threshold voltage (inherent property of transistors);
second oscillator circuitry (AS1) having a first terminal (drain of T1a), a second terminal (drain of T1b), and including a second transistor (T1a) having a second threshold voltage (inherent property of transistors), the second threshold voltage is less than the first threshold voltage (The threshold voltages are related to the transistor channel width/length ratios discussed in para. [0039], [0042], [0044], [0046]);
a first resistor (Rg1) having a first terminal and a second terminal, the first terminal of the first resistor (Rg1) coupled to the first terminal of the first oscillator circuitry (AB) and the first terminal of the second oscillator circuitry (AS1);
a second resistor (Rg2) having a first terminal and a second terminal, the first terminal of the second resistor (Rg2) coupled to the second terminal of the first oscillator circuitry (AB) and the second terminal of the second oscillator circuitry (AS1); and
a ground terminal (GND) coupled to the second terminal of the first resistor (Rg1) and the second terminal of the second resistor (Rg2).
As for claim 10, Herbert teaches a first inductor (L1) having a first terminal and a second terminal, the first terminal of the first inductor (L1) coupled to the first terminal of the first oscillator circuitry (AB), the first terminal of the second oscillator circuitry (AS1), and the first terminal of the first resistor (Rg1); and
a second inductor (L2) having a first terminal and a second terminal, the first terminal of the second inductor (L2) coupled to the second terminal of the first oscillator circuitry (AB), the second terminal of the second oscillator circuitry (AS1), and the first terminal of the second resistor (Rg2), the second terminal of the second inductor (L2) is coupled to the second terminal of the first resistor (Rg1), the second terminal of the second resistor (Rg2), the second terminal of the first inductor (L2), and the ground terminal (GND).
As for claim 11, Herbert teaches wherein the first oscillator circuitry (AB) includes:
current source circuitry (Rt4) having a terminal;
the first transistor (T4a) having a first terminal, a second terminal, and a control terminal; and
a third transistor (T4b) having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor is coupled to the terminal of the current source circuitry and the first terminal of the first transistor (T4a), the second terminal of the third transistor (T4b) is coupled to the first terminal of the second oscillator circuitry (AS1), the first terminal of the first resistor (Rg1), and the control terminal of the first transistor (T4a), the control terminal of the third transistor (T4b) is coupled to the second terminal of the second oscillator circuitry (AS1), the first terminal of the first resistor (Rg1), and the second terminal of the first transistor (T4a).
Regarding claim 13, Herbert teaches a first capacitor (C1) having a first terminal and a second terminal, the first terminal of the first capacitor (C1) coupled to the first terminal of the first oscillator circuitry (AB), the first terminal of the second oscillator circuitry (AS1), and the first terminal of the first resistor (Rg1); and
a second capacitor (C2) having a first terminal and a second terminal, the first terminal of the second capacitor (C2) is coupled to the second terminal of the first oscillator circuitry (AB), the second terminal of the second oscillator circuitry (AS1), and the first terminal of the second resistor (Rg2), the second terminal of the second capacitor (C2) is coupled to the second terminal of the first inductor (L1), the second terminal of the second resistor (Rg2), the ground terminal, and the second terminal of the first capacitor (C1).
As for claim 14, Herbert teaches a capacitor (C1v) having a first terminal and a second terminal, the first terminal of the capacitor is coupled to the first terminal of the first oscillator circuitry (AB), the first terminal of the second oscillator circuitry (AS1), and the first terminal of the first resistor (Rg1), the second terminal of the capacitor is coupled to the second terminal of the first oscillator circuitry (AB), the second terminal of the second oscillator circuitry (AS1), and the first terminal of the second resistor (Rg2).
Regarding claim 16, Herbert teaches an apparatus (figure 2) comprising:
a first transistor (T4a) having a first terminal, a second terminal, and a control terminal;
a second transistor (T4b) having a first terminal, a second terminal, and a control terminal, the first terminal (source) of the second transistor (T4b) coupled to the first terminal (source) of the first transistor (T4a);
a third transistor (T1a) having a first terminal, a second terminal, and a control terminal;
a fourth transistor (T1b) having a first terminal, a second terminal, and a control terminal, the first terminal (source) of the fourth transistor (T1b) coupled to the first terminal (source) of the third transistor(T1a);
a first resistor (Rg1) having a first terminal and a second terminal, the first terminal of the first resistor coupled to the second terminal of the first transistor (T4a), the control terminal of the second transistor (T4b), the second terminal of the third transistor (T1a), and the control terminal of the fourth transistor (T1b);
a second resistor (Rg2) having a first terminal and a second terminal, the first terminal of the second resistor (Rg2) coupled to the control terminal of the first transistor (T4a), the second terminal of the second transistor (T4b), the control terminal of the third transistor (T1a), and the second terminal of the fourth transistor (T1b); and
a ground terminal (GND) coupled to the second terminal of the first resistor (Rg1) and the second terminal of the second resistor (Rg2).
As for claim 17, Herbert teaches wherein the first transistor (T4a) and the second transistor (T4b) further have a first transconductance (inherent property of transistors), the third transistor (T1a) and fourth transistor (T1b) further have a second transconductance (inherent property of transistors), and the first transconductance is greater than the second transconductance (The transconductances are related to the transistor channel width/length ratios discussed in para. [0039], [0042], [0044], [0046]).
As for claim 18, Herbert teaches a first inductor (L1) having a first terminal and a second terminal, the first terminal of the first inductor (L1) is coupled to the second terminal of the first transistor (T4a), the control terminal of the second transistor (T4b), the second terminal of the third transistor (T1a), the control terminal of the fourth transistor (T1b), and the first terminal of the first resistor (Rg1);
a second inductor (L2) having a first terminal and a second terminal, the first terminal of the second inductor (L2) is coupled to the control terminal of the first transistor (T4a), the second terminal of the second transistor (T4b), the control terminal of the third transistor (T1a), the second terminal of the fourth transistor (T1b), and the first terminal of the second resistor (Rg2); and
a third resistor (Rt4) having a first terminal and a second terminal, the first terminal of the third resistor (Rt4) is coupled to the second terminal of the first resistor (Rg1) and the second terminal of the second resistor (Rg2), the second terminal of the second resistor is coupled to the second terminal of the first inductor (L1) and the second terminal of the second inductor (L2).
Claims 1, 2, 5, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feilkas et al. (US 2004/0100339; “Feilkas”; reference of record).
Regarding claim 1, Feilkas teaches an apparatus (Figure 2) comprising:
first current source circuitry (current source 3-4 connected to middle amplifier 2) having a terminal;
second current source circuitry (current source 3-4 connected to leftmost amplifier 2) having a terminal;
a first transistor (left transistor 21 in middle amplifier 2) having a first terminal, a second terminal, and a control terminal;
a second transistor (right transistor 21 in middle amplifier 2) having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the terminal of the first current source circuitry (3) and the first terminal of the first transistor (left transistor 21 in middle amplifier 2);
a third transistor (right transistor 21 in leftmost amplifier 2) having a first terminal, second terminal, and a control terminal;
a fourth transistor (left transistor 21 in leftmost amplifier 2) having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the terminal of the second current source circuitry (3) and the first terminal of the third transistor (right transistor 21 in leftmost amplifier 2); and
inductor circuitry (11) having a first terminal and a second terminal, the first terminal of the inductor circuitry coupled to the second terminal of the first transistor (left transistor 21 in middle amplifier 2), the control terminal of the second transistor (right transistor 21 in middle amplifier 2), the second terminal of the third transistor (right transistor 21 in leftmost amplifier 2), and the control terminal of the fourth transistor (left transistor 21 in leftmost amplifier 2), the second terminal of the inductor circuitry (11) coupled to the control terminal of the first transistor (left transistor 21 in middle amplifier 2), the second terminal of the second transistor (right transistor 21 in middle amplifier 2), the control terminal of the third transistor (right transistor 21 in leftmost amplifier 2), and the second terminal of the fourth transistor (left transistor 21 in leftmost amplifier 2).
As for claim 2, Feilkas teaches wherein the inductor circuitry including a first inductor (left inductor) having a first terminal and a second terminal, the first terminal of the first inductor is coupled to the second terminal of the first transistor, the control terminal of the second transistor, the second terminal of the third transistor, and the control terminal of the fourth transistor; and
a second inductor (right inductor) having a first terminal and a second terminal, the first terminal of the second inductor is coupled to the control terminal of the first transistor, the second terminal of the second transistor, the control terminal of the third transistor, and the second terminal of the fourth transistor, the second terminal of the second inductor is coupled to the second terminal of the first inductor.
As for claim 5, Feilkas teaches wherein the first current source circuitry includes a fifth transistor (4) having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor is coupled to the first terminal of the first transistor and the first terminal of the second transistor, the second current source circuitry includes a sixth transistor (4) having a first terminal and a control terminal, the first terminal of the sixth transistor is coupled to the first terminal of the third transistor and the first terminal of the fourth transistor, the second terminal of the sixth transistor coupled to the second terminal of the fifth transistor, the control terminal of the sixth transistor coupled to the control terminal of the fifth transistor (See configuration of current sources 3-4 in figure 2).
As for claim 7, Feilkas teaches wherein the first and second transistors (transistors 21 in middle amplifier 2) have a first threshold voltage and a first transconductance (inherent properties of transistors), the third and fourth transistors (transistors 21 in leftmost amplifier 21) have a second threshold voltage and a second transconductance (inherent properties of transistors), the first threshold voltage is greater than the second threshold voltage (The threshold voltages are related to the transistor channel width/length ratios discussed in para. [0024]-[0025]), and the first transconductance is greater than the second transconductance (The transconductances are related to the transistor channel width/length ratios discussed in para. [0024]-[0025]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Herbert in view of Yun et al. (US 2016/0080181; “Yun”; reference of record).
As for claim 8, Herbert teaches wherein the inductor circuitry (L1, L2) is first inductor circuitry, but fails to teach second inductor circuitry electromagnetically coupled to the first inductor circuitry; and receiver circuitry coupled to the second inductor circuitry.
However, it is well-known to those of ordinary skill in the art to utilize an LC oscillator in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver. For example, see figures 1 and 2 of Yun.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the LC oscillator of Herbert in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver because such a modification would have been implementing a well-known application of an LC oscillator.
As for claim 15, Herbert teaches wherein the first inductor (L1) and the second inductor (L2) are first inductor circuitry (L1/L2), but fails to teach second inductor circuitry electromagnetically coupled to the first inductor circuitry; and receiver circuitry coupled to the second inductor circuitry.
However, it is well-known to those of ordinary skill in the art to utilize an LC oscillator in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver. For example, see figures 1 and 2 of Yun.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the LC oscillator of Herbert in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver because such a modification would have been implementing a well-known application of an LC oscillator.
As for claim 19, Herbert teaches the apparatus of claim 18, as detailed above, but fails to teach a third inductor having a first terminal and a second terminal, the third inductor magnetically coupled to the first inductor and the second inductor; and receiver circuitry having a first terminal and a second terminal, the first terminal of the receiver circuitry is coupled to the third inductor and the second terminal of the receiver circuitry is coupled to second terminal of the third inductor.
However, it is well-known to those of ordinary skill in the art to utilize an LC oscillator in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver. For example, see figures 1 and 2 of Yun.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the LC oscillator of Herbert in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver because such a modification would have been implementing a well-known application of an LC oscillator.
As for claim 20, Herbert teaches the apparatus of claim 16, as detailed above, but fails to teach wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the first resistor, and the second resistor are a first communication channel, and the apparatus further comprising a second communication channel.
However, it is well-known to those of ordinary skill in the art to utilize an LC oscillator in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver. For example, see figures 1 and 2 of Yun.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the LC oscillator of Herbert in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver because such a modification would have been implementing a well-known application of an LC oscillator.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Feilkas in view of Gutierrez (US 2004/0066243; reference of record).
Regarding claim 3, Feilkas teaches the apparatus of claim 2, as detailed above, but fails to teach a first resistor having a first terminal and a second terminal, the first terminal of the first resistor is coupled to the second terminal of the first transistor, the control terminal of the second transistor, the second terminal of the third transistor, the control terminal of the fourth transistor, and the first terminal of the first inductor, the second terminal of the first resistor is coupled to the second terminal of the first inductor; and a second resistor having a first terminal and a second terminal, the first terminal of the second resistor is coupled to the control terminal of the first transistor, the second terminal of the second transistor, the control terminal of the third transistor, the second terminal of the fourth transistor, and the first terminal of the second inductor, the second terminal of the second resistor is coupled to the second terminal of the second inductor.
Gutierrez teaches serially resistors (28-30) between differential nodes (C, D) of an LC oscillator (Figure 2) for tuning the LC oscillator (para. [0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add serial resistors across the LC tank of Feilkas because such a modification would have provided the benefit of a well-known oscillator tuning configuration.
Response to Arguments
Applicant's arguments filed 03/06/26 have been fully considered but they are not persuasive.
Regarding Applicant’s comments directed to the rejection of claims 1, 9, and 16 under 35 U.S.C. 102(a)(1) as being anticipated by Herbert, Applicant argues, “However, Herbert does not teach what, if anything, the gate of transistor T4b is coupled to. Furthermore, the rejection cites the left terminal of L1 as the first terminal of the inductor circuitry, and Herbert also does not teach what, if anything, the left terminal of L1 is coupled to. For at least this reason, Herbert does not anticipate claim 1.” See page 11 of Applicant’s remarks. The Applicant appears to be noting that a connecting line is missing in figure 2 between the left terminal of inductor L1, the left terminal of capacitor C1, the drain terminal of transistor T4a, and the gate terminal of transistor T4b.
However, as would have been understood by one of ordinary skill in the art, figure 2 of Herbert discloses a differential LC oscillator with lines connecting the resonance circuit RS and the amplifier AB. While the connecting line between the left terminal of inductor L1, the left terminal of capacitor C1, the drain terminal of transistor T4a, and the gate terminal of transistor T4b is missing in figure 2, one of ordinary skill in the art would understand that this is a drafting error or mistake in the printing of the figure and not a connecting line that was purposely omitted.
This basic differential LC oscillator configuration with lines connecting a resonance circuit and amplifier can be seen throughout the references of record including at least the following references of record: Figure 3 of Gutierrez (US 2004/0066243); Figure 2 of Feilkas et al. (US 2004/0100339); Figure 1 of Khalil (US 2005/0122180); Figure 1 of Kousai (US 2007/0222489); and Figure 1 of Masuda et al. (US 2006/0261902).
Furthermore, Herbert describes the structure of figure 2 comprising a parallel configuration of resonance circuit RS and amplifiers AB, AS1, AS2, and AS3 (para. [0029], [0034], and [0035], which requires a connecting line between the left terminal of inductor L1, the left terminal of capacitor C1, the drain terminal of transistor T4a, and the gate terminal of transistor T4b.
Lastly, Herbert describes the structure of figure 2 comprising the amplifier AB and resonance circuit RS forming an oscillation loop (para. [0022] and [0048]), which also requires a connecting line between the left terminal of inductor L1, the left terminal of capacitor C1, the drain terminal of transistor T4a, and the gate terminal of transistor T4b.
Therefore, while not expressly shown in figure 2 of Herbert, for proper operation the oscillator circuit in figure 2 of Herbert requires a connecting line between the left terminal of inductor L1, the left terminal of capacitor C1, the drain terminal of transistor T4a, and the gate terminal of transistor T4b.
Allowable Subject Matter
Claims 6 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The best prior art references of record, Herbert and Feilkas, fail to teach:
“bias circuitry including: third current source circuitry having a terminal; a seventh transistor having a first terminal and a control terminal; and switch circuitry having a first terminal and a second terminal, the first terminal of the switch circuitry is coupled to the terminal of the third current source circuitry, the first terminal of the seventh transistor, and the control terminal of the seventh transistor, the second terminal of the switch circuitry is coupled to the control terminal of the fifth transistor and the control terminal of the sixth transistor.”, as set forth in claim 6; and
“switch circuitry having a first terminal, a second terminal, and a control terminal, the first terminal of the switch circuitry is coupled to the terminal of the second current source circuitry, the first terminal of the fifth transistor, and the control terminal of the fifth transistor, the second terminal of the switch circuitry is coupled to the third terminal of the second oscillator circuitry and the control terminal of the fourth transistor”, as set forth in claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LEVI GANNON/Primary Examiner, Art Unit 2849 March 23, 2026