DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Herbert (US 2008/0164957; reference of record). NOTE: There is a drafting error in figure 2 of Herbert. A connecting line is missing between the left terminal of inductor L1, the left terminal of capacitor C1, the drain terminal of transistor T4a, and the gate terminal of transistor T4b.
Regarding claim 16, Herbert teaches an apparatus (figure 2) comprising:
a first transistor (T4a) having a first terminal (source), a second terminal (drain), and a control terminal (gate);
a second transistor (T4b) having a first terminal (source), a second terminal (drain), and a control terminal (gate), the first terminal (source) of the second transistor (T4b) coupled to the first terminal (source) of the first transistor (T4a);
a third transistor (T1a) having a first terminal (source), a second terminal (drain), and a control terminal (gate);
a fourth transistor (T1b) having a first terminal (source), a second terminal (drain), and a control terminal (gate), the first terminal (source) of the fourth transistor (T1b) coupled to the first terminal (source) of the third transistor(T1a);
a first resistor (Rg1) having a first terminal (upper) and a second terminal (lower), the first terminal (upper) of the first resistor (Rg1) coupled (through C1) to the second terminal (drain) of the first transistor (T4a), the control terminal (gate) of the second transistor (T4b), the second terminal (drain) of the third transistor (T1a), and the control terminal (gate) of the fourth transistor (T1b);
a second resistor (Rg2) having a first terminal (upper) and a second terminal (lower), the first terminal (upper) of the second resistor (Rg2) coupled (through C2) to the control terminal (gate) of the first transistor (T4a), the second terminal (drain) of the second transistor (T4b), the control terminal (gate) of the third transistor (T1a), and the second terminal (drain) of the fourth transistor (T1b); and
a ground terminal (GND) coupled to the second terminal (lower) of the first resistor (Rg1) and the second terminal (lower) of the second resistor (Rg2).
As for claim 17, Herbert teaches wherein the first transistor (T4a) and the second transistor (T4b) further have a first transconductance (inherent property of transistors), the third transistor (T1a) and fourth transistor (T1b) further have a second transconductance (inherent property of transistors), and the first transconductance is greater than the second transconductance (The transconductances are related to the transistor channel width/length ratios discussed in para. [0039], [0042], [0044], [0046]).
As for claim 18, Herbert teaches a first inductor (L1) having a first terminal and a second terminal, the first terminal of the first inductor (L1) is coupled to the second terminal of the first transistor (T4a), the control terminal of the second transistor (T4b), the second terminal of the third transistor (T1a), the control terminal of the fourth transistor (T1b), and the first terminal of the first resistor (Rg1);
a second inductor (L2) having a first terminal and a second terminal, the first terminal of the second inductor (L2) is coupled to the control terminal of the first transistor (T4a), the second terminal of the second transistor (T4b), the control terminal of the third transistor (T1a), the second terminal of the fourth transistor (T1b), and the first terminal of the second resistor (Rg2); and
a third resistor (Rt4) having a first terminal and a second terminal, the first terminal of the third resistor (Rt4) is coupled to the second terminal of the first resistor (Rg1) and the second terminal of the second resistor (Rg2), the second terminal of the second resistor is coupled to the second terminal of the first inductor (L1) and the second terminal of the second inductor (L2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Herbert in view of Yun et al. (US 2016/0080181; “Yun”; reference of record).
As for claim 19, Herbert teaches the apparatus of claim 18, as detailed above, but fails to teach a third inductor having a first terminal and a second terminal, the third inductor magnetically coupled to the first inductor and the second inductor; and receiver circuitry having a first terminal and a second terminal, the first terminal of the receiver circuitry is coupled to the third inductor and the second terminal of the receiver circuitry is coupled to second terminal of the third inductor.
However, it is well-known to those of ordinary skill in the art to utilize an LC oscillator in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver. For example, see figures 1 and 2 of Yun.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the LC oscillator of Herbert in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver because such a modification would have been implementing a well-known application of an LC oscillator.
As for claim 20, Herbert teaches the apparatus of claim 16, as detailed above, but fails to teach wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the first resistor, and the second resistor are a first communication channel, and the apparatus further comprising a second communication channel.
However, it is well-known to those of ordinary skill in the art to utilize an LC oscillator in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver. For example, see figures 1 and 2 of Yun.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the LC oscillator of Herbert in a transceiver with an inductor-based isolation barrier between a transmitter comprising the LC oscillator and a receiver because such a modification would have been implementing a well-known application of an LC oscillator.
Response to Arguments
Applicant's arguments filed 06/03/26 have been fully considered but they are not persuasive.
Regarding Applicant’s comments directed to the rejection of claim 16 under 35 U.S.C. 102(a)(1) as being anticipated by Herbert, Applicant argues, “Figure 2 of Herbert seems to show that resistor Rg2 is coupled to capacitor C2 and to ground (GND). In fact, Herbert refers to resistor Rg2 as a "ground-coupling resistance." Herbert, 0021. Figure 2 shows a line between the bottom of resistor Rg2 and GND, and that line crosses multiple other lines, such as at the drain of transistor T4b, the source of transistor T4b, and the gate of transistor T4b. Herbert does not disclose that resistor Rg2 is coupled to any of the drain, gate, or source of transistor T4b. In fact, if one were to assume that the intersections of the various lines represent couplings, then the line from the bottom of resistor Rg2 to GND would short the drain, gate, and source of transistor T4b, which is both unlikely and unworkable. Thus, the cited portions of Herbert do not teach, "a second resistor having a first terminal and a second terminal, the first terminal of the second resistor coupled to the control terminal of the first transistor, the second terminal of the second transistor." For this reason alone, Herbert fails to anticipate claim 16.” See page 11 of Applicant’s remarks.
As discussed above in the rejection of claim 16, Herbert teaches a second resistor (Rg2) having a first terminal (upper) and a second terminal (lower), the first terminal (upper) of the second resistor (Rg2) coupled (through C2) to the control terminal (gate) of the first transistor (T4a), the second terminal (drain) of the second transistor (T4b), the control terminal (gate) of the third transistor (T1a), and the second terminal (drain) of the fourth transistor (T1b).
The phrase “coupled to” is interpreted as being a connection between two circuit elements that can be either an indirect connection or a direct connection. As seen in figure 2 of Herbert, the second resistor Rg2 is indirectly coupled to the drain of T4b, the gate of T4a, the gate of T1a, and the drain of T1b through the capacitor C2.
Herbert also teaches a first resistor (Rg1) having a first terminal (upper) and a second terminal (lower), the first terminal (upper) of the first resistor (Rg1) coupled (through C1) to the second terminal (drain) of the first transistor (T4a), the control terminal (gate) of the second transistor (T4b), the second terminal (drain) of the third transistor (T1a), and the control terminal (gate) of the fourth transistor (T1b).
Allowable Subject Matter
Claims 1-4, 7-10, and 13-15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The best prior art reference of record, Herbert, fails to teach:
“third current source circuitry having a terminal; a seventh transistor having a first terminal and a control terminal; and switch circuitry having a first terminal and a second terminal, the first terminal of the switch circuitry is coupled to the terminal of the third current source circuitry, the first terminal of the seventh transistor, and the control terminal of the seventh transistor, the second terminal of the switch circuitry is coupled to the control terminal of the fifth transistor and the control terminal of the sixth transistor.”, as set forth in claim 1; and
“switch circuitry having a first terminal, a second terminal, and a control terminal, the first terminal of the switch circuitry is coupled to the terminal of the second current source circuitry, the first terminal of the fifth transistor, and the control terminal of the fifth transistor, the second terminal of the switch circuitry is coupled to the third terminal of the second oscillator circuitry and the control terminal of the fourth transistor”, as set forth in claim 9.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM.
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/LEVI GANNON/Primary Examiner, Art Unit 2836 June 16, 2026
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