DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Request for Continued Examination
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 07/20/2026 has been entered.
Claim Rejections - 35 USC § 112
4. The rejection of claims 1-12 under 35 U.S.C. § 112, second paragraph, is withdrawn in view of applicant's amendments/remarks.
Response to Arguments
5. Applicant’s argument filed on 07/20/2026 with respect claims 18-20 have been fully considered but they are not persuasive.
The applicant contends that Zheng et al. (US 9,104, 646 B2) fails to teach or suggest the limitation of "detecting an error in the usage-based-disturbance data stored in the row." As recited in claim 18. The Examiner respectfully disagrees and asserts that Zheng et al. (US 9,104, 646 B2) in column 2, lines 41-64 teaches the such limitation. For example, the memory device 40 is an integrated circuit chip that stores data under the control of the memory controller 20. In one embodiment, the memory device 40 uses resistive memory cells that are relatively non-volatile but may lose their data after a number of access cycles cause disturbances to accumulate in the memory cells. The memory device 40 may be a substitute for a conventional DRAM memory device and be compatible with DRAM-like memory access commands. The memory device 40 detects, at row activation, a memory disturbance condition in the activated row that can potentially cause a loss of data if uncorrected, and corrects for the disturbance condition before it actually causes a loss of data. In this manner, accumulated disturbances are only corrected on an as-needed basis, thereby reducing the amount of energy spent on disturbance correction. In some embodiments, the memory device 40 can detect and react to disturbance conditions on its own without the memory controller's 20 receiving information on such disturbance conditions. Although only one memory device 40 is shown in FIG. 1, in other embodiments, there may be many memory devices 40 controlled by a single memory controller 20. Additionally, the memory device 40 may be mounted on a memory module and/or in a common package along with other memory devices 40. See column 2, lines 41-64.
Also, the applicant contends that the office action fails to teach or suggest the limitation of " responsive to the detecting of the error, preventing usage-based-disturbance circuitry of the memory device from using the faulty usage-based-disturbance data stored in the row to perform usage-based-disturbance mitigation." As recited in claim 18.
Examiner respectfully disagrees and asserts that Miura et al. (US 2019/0369884 A1) in paragraph [0039] teaches the such limitation. For example, Also, the access control circuit 20 stops the refresh operation when an access control error is detected. For example, when an access control error is detected by the error detection circuit 40, the access control circuit 20 stops the refresh operation, which reads the setting data from the nonvolatile memory 70 and reloads that setting data in the register 30. By doing so, after an access control error is detected by the error detection circuit 40, the refresh operation of the register 30 is not performed. Therefore, it is possible to prevent a situation in which due to a malfunction of the nonvolatile memory 70 or the like, or a connection failure, erroneous setting data is reloaded in the register 30, and the circuit device 10 malfunctions based on this erroneous setting data. Note that stopping of the refresh operation may also be realized by inputting an error detection signal from the error detection circuit 40 to the access control circuit 20. For example, when the error detection signal becomes active, the access control circuit 20 stops the refresh operation. Alternatively, as shown in FIG. 2 to be described later, a selector 36 may deactivate the setting data from the access control circuit 20, thereby stopping the refresh operation. Alternatively, when the external device 100 detects the error detection signal ERR, an instruction to stop the refresh operation may be sent from the external device 100 to the access control circuit 20 through the interface circuit 50.
Also, the applicant contends that office action fails to teach or suggest the limitation of "performing a parity check, an error-correcting-code check, a checksum check, or a cyclic redundancy check on the usage-based-disturbance data, the error indicating that the usage-based-disturbance data comprises faulty usage-based disturbance data.” As recited in claim 18. The Examiner notes that the applicant’s arguments regarding to the above limitations have been considered but are moot in view of the new ground(s) of rejection. In addition to, the Examiner maintained the references of Zheng et al. (US 9,104, 646 B2) and Miura et al. (US 2019/0369884 A1) since there is no further argument/s regarding to this reference.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
6. Claims 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per claim 18:
The claim recites “A method performed by a memory device, the method comprising: storing, within a subset of memory cells of a row, usage-based-disturbance data corresponding to the row, the usage-based-disturbance data comprising an activation count of the row; detecting an error in the usage-based-disturbance data stored in the row by performing a parity check, an error-correcting-code check, a checksum check, or a cyclic redundancy check on the usage-based-disturbance data, the error indicating that the usage-based-disturbance data comprises faulty usage-based disturbance data; and responsive to the detecting of the error, preventing usage-based-disturbance circuitry of the memory device from using the faulty usage-based-disturbance data stored in the row to perform usage-based-disturbance mitigation.”
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, see MPEP 2106.03. The claim recites a series of steps and, therefore, is a process, and thus directed to a statutory category.
At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes. MPEP 2106.04. The claim recites the following limitations directed to an abstract idea “detecting an error in the usage-based-disturbance data stored in the row performing a parity check, an error-correcting-code check, a checksum check, or a cyclic redundancy check on the usage-based-disturbance data, the error indicating that the usage-based-disturbance data comprises faulty usage-based disturbance data; and responsive to the detecting of the error,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind, a person just looking into the disturbance data is able to detect an error, then it falls within the “Mental Processes” grouping of abstract ideas. Similarly, the limitation of “preventing usage-based-disturbance circuitry of the memory device from using the faulty usage-based-disturbance data stored in the row to perform usage-based-disturbance mitigation” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind, limitation is interpreted in view of the disclosure (claim 7) as just writing a value into dataset. Therefore, a person is able to write a value with the help of a tool (computer), then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO. See MPEP 2106.04(d). This judicial exception is not integrated into a practical application because the additional limitations of “storing, within a subset of memory cells of a row, usage-based-disturbance data corresponding to the row, the usage-based-disturbance data comprising an activation count of the row” does not integrate the abstract idea into a practical application because is a generic computer function of data storing. These extra-solution activities do not provide practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO. See MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “a memory device” is generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See the prior arts Zheng et al. (US 9,104, 646 B2) in Fig. 1 and Miura et al. (US 2019/0369884 A1) in Fig. 1 teach well known elements. Therefore, the claim is not patent eligible.
Dependent claims 18-19 are extended elements of the abstract idea of the independent claims and the claims are abstract in nature falling withing Mental Processes. The dependent claims do not add any meaningful limits to the abstract idea to improve the technology or the computer component and fails to add significantly more than the abstracts idea. Therefore, the dependent claims are not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 18-20 are rejected under 35 U.S.C. 103 (a) as being unpatentable Zheng et al. (US 9,104, 646 B2) “hereinafter as Zheng” in view of Kim et al. (US 2022/0139482 A1) “herein after as Kim” in further view of Miura et al. (US 2019/0369884 A1) “hereinafter as Miura.”
As per claim 18: Zheng substantially teaches or discloses method performed by a memory device (see Fig. 1, memory device 40), the method comprising: storing, within a subset of memory cells of a row, usage-based-disturbance data corresponding to the row (see column 1, lines 57-61, the memory device also includes disturbance warning circuits, each of which is associated with one or more of the memory rows. A disturbance warning circuit has a state that corresponds to accumulated disturbances in the memory rows associated with the disturbance warning circuit; and column 2, lines 48-53, the memory device 40 detects, at row activation, a memory disturbance condition in the activated row that can potentially cause a loss of data if uncorrected, and corrects for the disturbance condition before it actually causes a loss of data) ,the usage-based-disturbance data comprising an activation count of the row (see column 5, lines 45-50, the disturbance warning circuits 54 may be counters that store counter values. Initially, the disturbance control circuit 56 resets the counter value to an initial counter value (e.g. 0). The value is adjusted (e.g. incremented or decremented) when the row associated with the counter is activated; and claim 17); detecting an error in the usage-based-disturbance datasee abstract, and column 2, lines 44-53, herein the memory device 40 uses resistive memory cells that are relatively non-volatile but may lose their data after a number of access cycles cause disturbances to accumulate in the memory cells,--- the memory device 40 detects, at row activation, a memory disturbance condition in the activated row that can potentially cause a loss of data if uncorrected, and corrects for the disturbance condition before it actually causes a loss of data). Zheng does not explicitly teach performing a parity check, an error-correcting-code check, a checksum check, or a cyclic redundancy check on the usage-based-disturbance data, the error indicating that the usage-based-disturbance data comprises faulty usage-based disturbance data. However, Kim in the same the field of endeavor teaches performing a parity check, an error-correcting-code check, a checksum check, or a cyclic redundancy check on the usage-based-disturbance data, the error indicating that the usage-based-disturbance data comprises faulty usage-based disturbance data (see abstract, and paragraph [0048], herein the control logic circuit 210 may control the row fault detector 600 to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected during a plurality of error detection operations performed by the ECC engine 400, therein by accumulating the error parameter for each of a plurality of defective memory cell rows in each of which the at least one error is detected. The row fault detector 600 may determine whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter stored therein and may transmit a decoding status flag DSF indicating that the row fault occurs to the memory controller (the external memory controller) 100; and paragraphs [0069], [0161], [0163], [0198]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the memory system of Zheng with the teachings of Kim by performing a parity check, an error-correcting-code check, a checksum check, or a cyclic redundancy check on the usage-based-disturbance data, the error indicating that the usage-based-disturbance data comprises faulty usage-based disturbance data. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the performing a parity check, an error-correcting-code check, a checksum check, or a cyclic redundancy check on the usage-based-disturbance data, the error indicating that the usage-based-disturbance data comprises faulty usage-based disturbance data would have improved the error detection and correction capability. Zheng-Kim as combined does not explicitly teach responsive to the detecting of the error, preventing usage-based-disturbance circuitry of the memory device from using the faulty usage-based-disturbance data stored in the row to perform usage-based-disturbance mitigation. However, Miura in the same the field of endeavor teaches responsive to the detecting of the error, preventing usage-based-disturbance circuitry of the memory device from using the faulty usage-based-disturbance data stored in the row to perform usage-based-disturbance mitigation (see paragraph [0039], herein the access control circuit 20 stops the refresh operation when an access control error is detected. For example, when an access control error is detected by the error detection circuit 40, the access control circuit 20 stops the refresh operation, which reads the setting data from the nonvolatile memory 70 and reloads that setting data in the register 30--- when the error detection signal becomes active, the access control circuit 20 stops the refresh operation [Note: limitation is interpreted in view of the disclosure claim 19, the preventing of the usage-based-disturbance mitigation for the row comprises preventing an activation count of the row to be refreshed]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the memory system of Zheng-Kim as combined with the teachings of Miura by preventing usage-based-disturbance circuitry of the memory device from using the faulty usage-based-disturbance data stored in the row to perform usage-based-disturbance mitigation. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the preventing usage-based-disturbance circuitry of the memory device from using the faulty usage-based-disturbance data stored in the row to perform usage-based-disturbance mitigation would have improved the memory device performance.
As per claim 19: Miura teaches that wherein the preventing of the usage-based-disturbance mitigation for the row comprises preventing the activation count of the row from causing other rows that are proximate to the row to be refreshed for usage-based-disturbance mitigation (see paragraph [0039], herein the access control circuit 20 stops the refresh operation when an access control error is detected. For example, when an access control error is detected by the error detection circuit 40, the access control circuit 20 stops the refresh operation, which reads the setting data from the nonvolatile memory 70 and reloads that setting data in the register 30 --- when the error detection signal becomes active, the access control circuit 20 stops the refresh operation).
As per claim 20: Zheng teaches that receiving, from a host device, a command to repair the row; responsive to the receiving of the command, repairing the row (see column 1, lines 61-66, herein a disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether a disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row); and enabling usage-based-disturbance mitigation to be performed based on the usage-based-disturbance data corresponding to the row responsive to the repairing of the row (see column 1, lines 67, and column 2, lines 1-7, herein If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row, e.g., to reduce the accumulated disturbances before they cause a loss of data. Advantageously, detecting disturbance conditions upon row activation and then performing disturbance recovery on a memory row corrects for accumulated disturbances only when necessary, thereby reducing energy spent on recovery operations).
Allowable Subject Matter
8. Claims 1-17 are found to be allowable over the prior art. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Examiner Notes
9. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
10. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112
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