DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Information Disclosure Statement
3. The references listed in the information disclosure statement (IDS) submitted on 03/31/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto.
Claim Rejections - 35 USC § 112
4. The rejection of claims 12 and 17 under 35 U.S.C. § 112, second paragraph, is withdrawn in view of applicant's amendments/remarks.
Response to Arguments
5. Applicant’s argument filed on filed on 02/12/2026 with respect to claims 18-20 have been fully considered but they are not persuasive.
The applicant contends that Zheng et al. (US 9,104, 646 B2) fails to teach or suggest the limitation of " storing, within a subset of memory cells of a row, usage-based-disturbance data corresponding to the row, the usage-based-disturbance data comprising an activation count of the row." As recited in claim 18.
Examiner respectfully disagrees and asserts that Zheng et al. (US 9,104, 646 B2) in column 1, lines 51-67, column 2, lines 1-7, lines 41-53, and column 5, lines 45-58 teaches the such limitation. For example, Embodiments of the present disclosure relate to components of a memory system, such as a memory controller and/or memory device, which detect and recover from potential memory read disturbances. In one embodiment, the memory device includes a memory array that includes a memory rows. The memory device also includes disturbance warning circuits, each of which is associated with one or more of the memory rows. A disturbance warning circuit has a state that corresponds to accumulated disturbances in the memory rows associated with the disturbance warning circuit. A disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether a disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row, e.g., to reduce the accumulated disturbances before they cause a loss of data. Advantageously, detecting disturbance conditions upon row activation and then performing disturbance recovery on a memory row corrects for accumulated disturbances only when necessary, thereby reducing energy spent on recovery operations. See column 1, lines 51-67 & column 2, lines 1-7.
The memory device 40 is an integrated circuit chip that stores data under the control of the memory controller 20. In one embodiment, the memory device 40 uses resistive memory cells that are relatively non-volatile but may lose their data after a number of access cycles cause disturbances to accumulate in the memory cells. The memory device 40 may be a substitute for a conventional DRAM memory device and be compatible with DRAM-like memory access commands. The memory device 40 detects, at row activation, a memory disturbance condition in the activated row that can potentially cause a loss of data if uncorrected, and corrects for the disturbance condition before it actually causes a loss of data. See column 2, lines 41-53.
In another embodiment, the disturbance warning circuits 54 may be counters that store counter values. Initially, the disturbance control circuit 56 resets the counter value to an initial counter value (e.g. 0). The value is adjusted (e.g. incremented or decremented) when the row associated with the counter is activated. Once the counter value crosses a threshold value, the disturbance control circuit 56 determines that a disturbance condition sufficient to trigger correction exists. The threshold value can be set to a level that allows accumulated disturbances in the memory array 52 to be acted upon before the disturbances gain a magnitude large enough to cause an uncorrectable loss of data (in an embodiment that stores error correction codes for each column of data, some loss of uncorrected data may be tolerated). See column 5, lines 45-58.
Also, the applicant contends that Zheng et al. (US 9,104, 646 B2) fails to teach or suggest the limitation of "detecting an error in the usage-based-disturbance data stored in the row." As recited in claim 18. The Examiner respectfully disagrees and asserts that Zheng et al. (US 9,104, 646 B2) in column 2, lines 41-64 teaches the such limitation. For example, the memory device 40 is an integrated circuit chip that stores data under the control of the memory controller 20. In one embodiment, the memory device 40 uses resistive memory cells that are relatively non-volatile but may lose their data after a number of access cycles cause disturbances to accumulate in the memory cells. The memory device 40 may be a substitute for a conventional DRAM memory device and be compatible with DRAM-like memory access commands. The memory device 40 detects, at row activation, a memory disturbance condition in the activated row that can potentially cause a loss of data if uncorrected, and corrects for the disturbance condition before it actually causes a loss of data. In this manner, accumulated disturbances are only corrected on an as-needed basis, thereby reducing the amount of energy spent on disturbance correction. In some embodiments, the memory device 40 can detect and react to disturbance conditions on its own without the memory controller's 20 receiving information on such disturbance conditions. Although only one memory device 40 is shown in FIG. 1, in other embodiments, there may be many memory devices 40 controlled by a single memory controller 20. Additionally, the memory device 40 may be mounted on a memory module and/or in a common package along with other memory devices 40. See column 2, lines 41-64.
Further, Also, the applicant contends that Zheng et al. (US 9,104, 646 B2) fails to teach or suggest the limitation of “responsive to the detecting of the error, preventing usage-based-disturbance mitigation from being performed based on the usage-based-disturbance data stored in the row.” As recited in claim 18.
The applicant’s arguments regarding to the limitation above have been considered but are moot in view of the new ground(s) of rejection. See the claim rejections -35 USC § 103 below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites the limitation of " setting the match flag responsive to the address of the accessed row matching the address logged at the local-bank level." There is insufficient antecedent basis in the claim by using the phrase “the accessed row.” The Examiner suggests that to add the feature of “accessing a row using an engine of the memory device” to overcome the under 35 U.S.C. 112(b) rejection. Dependent claims 2-12 depend from the base claim 1 and inherently include limitation therein and therefore are rejected under 35 USC 112, 2nd paragraph as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 18-20 are rejected under 35 U.S.C. 103 (a) as being unpatentable Zheng et al. (US 9,104, 646 B2) “hereinafter as Zheng” in view of Miura et al. (US 2019/0369884 A1) “hereinafter as Miura.”
As per claim 18: Zheng substantially teaches or discloses method performed by a memory device (see Fig. 1, memory device 40), the method comprising: storing, within a subset of memory cells of a row, usage-based-disturbance data corresponding to the row (see column 1, lines 57-61, the memory device also includes disturbance warning circuits, each of which is associated with one or more of the memory rows. A disturbance warning circuit has a state that corresponds to accumulated disturbances in the memory rows associated with the disturbance warning circuit; and column 2, lines 48-53, the memory device 40 detects, at row activation, a memory disturbance condition in the activated row that can potentially cause a loss of data if uncorrected, and corrects for the disturbance condition before it actually causes a loss of data) ,the usage-based-disturbance data comprising an activation count of the row (see column 5, lines 45-50, the disturbance warning circuits 54 may be counters that store counter values. Initially, the disturbance control circuit 56 resets the counter value to an initial counter value (e.g. 0). The value is adjusted (e.g. incremented or decremented) when the row associated with the counter is activated; and claim 17); detecting an error in the usage-based-disturbance datasee abstract, and column 2, lines 44-53, herein the memory device 40 uses resistive memory cells that are relatively non-volatile but may lose their data after a number of access cycles cause disturbances to accumulate in the memory cells,--- the memory device 40 detects, at row activation, a memory disturbance condition in the activated row that can potentially cause a loss of data if uncorrected, and corrects for the disturbance condition before it actually causes a loss of data). Zheng does not explicitly teach responsive to the detecting of the error, preventing usage-based-disturbance mitigation from being performed based on the usage-based-disturbance data stored in the row. However, Miura in the same the field of endeavor teaches responsive to the detecting of the error, preventing usage-based-disturbance mitigation from being performed based on the usage-based-disturbance data stored in the row (see paragraph [0039], herein the access control circuit 20 stops the refresh operation when an access control error is detected. For example, when an access control error is detected by the error detection circuit 40, the access control circuit 20 stops the refresh operation, which reads the setting data from the nonvolatile memory 70 and reloads that setting data in the register 30--- when the error detection signal becomes active, the access control circuit 20 stops the refresh operation [Note: limitation is interpreted in view of the disclosure claim 19, the preventing of the usage-based-disturbance mitigation for the row comprises preventing an activation count of the row to be refreshed]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the memory system of Zheng with the teachings of Miura by preventing usage-based-disturbance mitigation from being performed based on the usage-based-disturbance data stored in the row responsive to the detecting of the error. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the preventing usage-based-disturbance mitigation from being performed based on the usage-based-disturbance data stored in the row responsive to the detecting of the error would have improved the memory device performance.
As per claim 19: Miura teaches that wherein the preventing of the usage-based-disturbance mitigation for the row comprises preventing the activation count of the row from causing other rows that are proximate to the row to be refreshed for usage-based-disturbance mitigation (see paragraph [0039], herein the access control circuit 20 stops the refresh operation when an access control error is detected. For example, when an access control error is detected by the error detection circuit 40, the access control circuit 20 stops the refresh operation, which reads the setting data from the nonvolatile memory 70 and reloads that setting data in the register 30 --- when the error detection signal becomes active, the access control circuit 20 stops the refresh operation).
As per claim 20: Zheng teaches that receiving, from a host device, a command to repair the row; responsive to the receiving of the command, repairing the row (see column 1, lines 61-66, herein a disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether a disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row); and enabling usage-based-disturbance mitigation to be performed based on the usage-based-disturbance data corresponding to the row responsive to the repairing of the row (see column 1, lines 67, and column 2, lines 1-7, herein If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row, e.g., to reduce the accumulated disturbances before they cause a loss of data. Advantageously, detecting disturbance conditions upon row activation and then performing disturbance recovery on a memory row corrects for accumulated disturbances only when necessary, thereby reducing energy spent on recovery operations).
Allowable Subject Matter
8. Claims 1-12 are found to be allowable over the prior art, but the claims will be allowed if the applicant overcomes the claim rejections under 35 USC § 112, set forth in this Office action. 9. Claims 13-17 are found to be allowable over the prior art. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Examiner Notes
10. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
11. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069.
The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN ALSHACK/
Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
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