Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on November 29th, 2025. Claims 1-20 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over Benveniste (USPGPUB No. 2014/0010081 A1) in view of Dalal et al. (USPGPUB No. 2023/0231811 A1, hereinafter referred to as Dalal).
Referring to claim 1, Benveniste discloses a switch comprising {“Packet Switching in Radio Channels”, see Fig. 1, [0014], 1st sentence}:
receive an identifier of data to be transferred {“ Station 204A is supplied with data from a file transfer data source 214A [filename/identifier],”, see Fig. 2a, [0111], last two sentences; other data types “email, data backup” and “voice and video data” ([0111]} from a source device to a destination device {“a single frame to any destination.”, see Fig. 2b, [0113]};
begin an operation of the data {“Station 204A is supplied with data from the file transfer data source 214A,”, see Fig. 2b, [0115], 2nd sentence} by providing a set of signals {“Each wireless station 204A and 204B can determine the urgency class of its pending packets according to a [providing a set of signals] scheduling algorithm”, see Fig. 2b, [0115], 4th sentence};
Benveniste does not appear to explicitly disclose wherein the controller is a direct memory access (DMA) controller; wherein the DMA controller configured to:
begin an operation of the data by providing a set of signals; that specifies to the source device an expected size of the data and that specifies to begin retrieving at least a portion of the data;
determine to terminate the operation before the expected size of the data has been met;
and terminate read operation;
However, Dalal discloses wherein the controller is a direct memory access (DMA) controller {“DMA controller”, see Fig. 59a, [0287]}; wherein the DMA controller configured to:
begin an operation of the data {“the downstream resource can begin execution on the data.”, see Fig. 59a, [0289]} by providing a set of signals {“adapted to respond to these [set of signals] instructions in the form of data reads/data writes to the [DMA controller] DMA master”, see Fig. 2b, [0115], 4th sentence}; that specifies to the source device {“from the accessor to the [source/destination device] resource interface”, see Fig. 59a, [0289]} an expected size of the data {“an aperture with a hardware [data] size supported”, [0286], 2nd sentence} and that specifies to begin retrieving at least a portion of the data {“packets gets [portioned] quantized to a cell size (64 B), and so the transfer time increases with a worst case of 65B packets+metadata”, [0167], last two sentences};
determine to terminate the operation {“To parameterize packet inter-arrival times and bursting, 200 terminating client connections per Xockets DIMM and several thousand switched flows per DIMM are assumed” ([0161], 1st sentence)} before the expected size of the data has been met {“packets gets quantized to a cell size (64 B), and so the transfer time increases with a worst case of 65B packets+metadata”, [0167], last two sentences};
and terminate read operation {“minimal overhead context switching between terminated sessions” (see Fig. [0412], 1st sentence) as such sessions include both read/write operation(s)}.
Benveniste and Dalal are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Benveniste and Dalal before him or her, to modify Benveniste’s “Station 204A” (see Fig. 2b, [0115]) incorporating Dalal’s “DMA controller” (see Fig. 59a, [0287]).
The suggestion/motivation for doing so would have been to implement a method for efficiently providing network tunneling services for network overlay operations such as incoming packet data is converted to a memory bus compatible protocol and transferred to offload processors for further modifications that are sent back onto the memory bus for transfer to a network, memory unit, or host processor (Dalal [0366]).
Therefore, it would have been obvious to combine Dalal with Benveniste to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Dalal discloses wherein the controller is configured to receive the identifier of the data by receiving a source address and a size of the data {“communicates the session color, size, and [source] starting physical address to the scheduler circuit upon session initialization”, see Fig. 59a, [0306]}.
As per claim 3, the rejection of claim 1 is incorporated and Dalal discloses wherein the controller is configured to receive the identifier of the data as a trigger {“During an actual context switch [trigger]…”, see Fig. 59a, [0306]} from the source device {“During an actual context switch [trigger], a scheduler circuit can identify the session context [from which the identifier of the data]”, see Fig. 59a, [0306]}.
As per claim 4, the rejection of claim 1 is incorporated and Benveniste discloses wherein the source device comprises an analog-to-digital converter (ADC) {the source device “radio range between wireless stations 102, 104A,” (see Fig. 1a, [0003]) including an ADC to convert from analog signal via antenna to wireline “Much like 10/100 Mbps Ethernet wired LANs”, [0011] via “MAC layer” ([0112], 1st sentence)}, and wherein the destination device comprises a memory device {“streams received at each node, place a packet in the access buffer; the buffered packet”, see Fig. 1a, [0149], 2nd sentence}.
As per claim 5, the rejection of claim 1 is incorporated and Dalal discloses wherein the source device comprises a peripheral device {“cooperative mechanism between a scheduler circuit and the OS on the [peripheral device] offload processor 5908i”, see Fig. 59a, [0306]}, and wherein the destination device comprises a memory device {“initiate a bulk transfer of these contents to an [destination memory device] external low latency memory”, see Fig. 59a, [0306]}.
As per claim 6, the rejection of claim 1 is incorporated and Dalal discloses further wherein the DMA controller is configured to terminate the read operation {“terminate traffic, provide transparent services, and then virtually inject the traffic back to the intended target” (see Fig. 14, [0142], last two sentences) that traffic includes read operation as “offload processor whose session is complete/terminated)” (see Fig. 64, [0348], last two sentences) where the session include read/write DMAs per context “initiate a bulk transfer of these contents to an external low latency memory” (see Fig. 59a, [0306])} based on an indication of a transfer error {“imposes requirements on the delay or delay jitter and the error rates realized”, see Fig. 1a, [0062], 1st sentence}, further wherein the DMA controller is configured to terminate the read operation {“To parameterize packet inter-arrival times and bursting, 200 terminating client connections per Xockets DIMM and several thousand switched flows per DIMM are assumed” ([0161], 1st sentence)}.
As per claim 7, the rejection of claim 1 is incorporated and Dalal discloses wherein the DMA controller is configured to determine to terminate the read operation {“ability to terminate sessions with little or no overhead” whether the operations are read/write, see Fig. 65, [0355] last two sentences} based on an indication of a lack of access permission {such termination performed by “Xocket Tunneling Driver 650” (see Fig. 65, [0353], last two sentences) such tunneling based on access permission or lack thereof “independent SSL/TLS encryptions streams for the meta-data control and data exchanged, to handshake ciphers and possible certificates” ([0137], last sentence, [0138], 1st sentence)}, further wherein the DMA controller is configured to terminate the read operation {“terminate traffic, provide transparent services, and then virtually inject the traffic back to the intended target” (see Fig. 14, [0142], last two sentences) that traffic includes read operation as “offload processor whose session is complete/terminated)” (see Fig. 64, [0348], last two sentences) where the session include read/write DMAs per context “initiate a bulk transfer of these contents to an external low latency memory” (see Fig. 59a, [0306])}.
As per claim 8, the rejection of claim 1 is incorporated and Dalal discloses wherein the DMA controller is configured to determine to terminate the read operation {“ability to terminate sessions with little or no overhead” whether the operations are read/write, see Fig. 65, [0355] last two sentences} based on an indication of a higher-priority transaction {“scheduling discipline chosen for this prioritization, or traffic management (TM), can affect the traffic shape of flows and micro-flows through delay”, see Fig. 59a, [0293], 3rd sentence}, further wherein the DMA controller is configured to terminate the read operation {“terminate traffic, provide transparent services, and then virtually inject the traffic back to the intended target” (see Fig. 14, [0142], last two sentences) that traffic includes read operation as “offload processor whose session is complete/terminated)” (see Fig. 64, [0348], last two sentences) where the session include read/write DMAs per context “initiate a bulk transfer of these contents to an external low latency memory” (see Fig. 59a, [0306])} and resume the read operation of the data after completion of the higher-priority transaction {“a context stored by one offload processor can be resumed by a different offload processor” (see Fig. 60-0, [0320]) such as after completion “can manage session transfers and context switches so that there is minimal kernel/OS execution prior to resuming a session warmly” (see Fig. 83, [0435], 2nd sentence)}.
As per claim 9, the rejection of claim 1 is incorporated and Dalal discloses wherein the DMA controller is configured to determine to terminate the read operation {“ability to terminate sessions with little or no overhead” whether the operations are read/write, see Fig. 65, [0355] last two sentences} based on an indication of unused capacity {“otherwise [unused] underutilized socket IO blocks can be driven and processed by wimpy cores, and otherwise underutilized intra-rack communication can integrate the rack tightly.”, see Figs. 1 and 2, [0095], last sentence} in a first in first out (FIFO) buffer {“common large prefetch buffer” ([0100]) for a further transaction {“Given the timescale of these [transaction] transfers, versus packet inter-arrival times”, see Fig. 39, [0181], last sentence}, further wherein the DMA controller is configured to terminate the read operation {“terminate traffic, provide transparent services, and then virtually inject the traffic back to the intended target” (see Fig. 14, [0142], last two sentences) that traffic includes read operation as “offload processor whose session is complete/terminated)” (see Fig. 64, [0348], last two sentences) where the session include read/write DMAs per context “initiate a bulk transfer of these contents to an external low latency memory” (see Fig. 59a, [0306])}.
As per claim 10, the rejection of claim 1 is incorporated and Dalal discloses wherein the DMA controller is configured to begin the read operation by causing the source device {“issue the correct set of write and read commands to Xockets Memory 1222”, see Fig. 12, [0132], last sentence} to provide bus access to the DMA controller {“Additional DIMMs (e.g., 1232) and SSDs (e.g., 1224) can be integrated efficiently with RDMA capable NICs [over a bus]”, see Fig. 12, [0132], 2nd sentence} for the read operation {“attachment to a memory bus 5916 that can respond to DMA read/write requests.”, see Fig. 59a, [0287], 3rd sentence}, further wherein the DMA controller is configured to terminate the read operation {“terminate traffic, provide transparent services, and then virtually inject the traffic back to the intended target” (see Fig. 14, [0142], last two sentences} by transmitting a signal to the source device that causes the source device to stop the read operation {“that [DMA read/write] traffic includes read operation as “offload processor whose session is complete/terminated)” (see Fig. 64, [0348], last two sentences) where the session include read/write DMAs per context “initiate a bulk transfer of these contents to an external low latency memory” (see Fig. 59a, [0306])} and release the bus access {“tunneled over the DDR bus to between the virtual switch the x86 processors”, see Fig. 4, [0110], last sentence}.
As per claim 11, the rejection of claim 1 is incorporated and Dalal discloses wherein the DMA controller is further configured to:
move the data from the read operation {“transparent de-duplication for availability, and proprietary synchronization techniques for moving data to places of locality [buffer(s)]”, see Fig. 12, [0131]} into a first in first out (FIFO) buffer {“rate limiting allows bursting to consume buffer space”, see Fig. 24, [0164], 2nd sentence};
and write the data from the FIFO buffer to the destination device {“can be placed on each ARM processor to federate querying across [other destination devices] several processors through the rack.”, see Fig. 12, [0133], last sentence}.
Referring to claim 12, Benveniste discloses a method comprising:
receiving a command {“Station 204A is supplied [via a command] with data from the file transfer data source 214A,”, see Fig. 2b, [0115], 2nd sentence} from a controller {“use of an intelligent controller”, see Fig. 1, [0208], last sentence}, wherein the command indicates an operation having an address of data {“it provides address mapping”, see Fig. 1, [0026]; another type of addressing provided by “MAC dwell-time is the time spent by a frame in the MAC layer”, [0258], 1st two sentences};
Benveniste does not appear to explicitly disclose wherein the command indicates an operation having an address of data {“it provides address mapping”, see Fig. 1, [0026]; another type of addressing provided by “MAC dwell-time is the time spent by a frame in the MAC layer”, [0258], 1st two sentences} and indicates an expected size of a set of data associated with the command {“tiered contention multiple access (TCMA) period 218” (see Fig. 2b, [0114]) that specifies “operates during period 218 minimizes the chance of [begin retrieving/sending] collisions between stations sharing the medium”, [0116], 1st sentence};
receiving a read command from a direct memory access (DMA) controller, wherein the read command indicates a sequential read operation having an address of data and indicates an expected size of a set of data associated with the read command;
providing exclusive bus access to the DMA controller for the sequential read operation;
in response to the read command, reading data from an address range associated with the address of data; and
terminating reading the data prior to reading an entirety of the set of data in response to a signal from the DMA controller indicating releasing the exclusive bus access.
However, Dalal discloses wherein the command indicates an operation having an address of data {“address [of data residing] the local Xockets DIMM upon requesting a certain address range”, see Fig. 12, [0132], 3rd sentence} and indicates an expected size of a set of data associated with the command {“an aperture with a hardware [expected] size supported”, [0286], 2nd sentence};
receiving a read command from a direct memory access (DMA) controller {“DMA controller”, see Fig. 59a, [0287]}, wherein the read command indicates a sequential read operation {“point to consecutive entries in memory so as to direct incoming packets to [read/write] consecutive memory locations.”, see Fig. 59a, [0283], last sentence} having an address of data and indicates an expected size of a set of data {“if the descriptor is associated with a specific [/expected] data structure for handling incoming packets.” Such a data structure with a size as claimed, see Fig. 59a, [0283], 1st sentence} associated with the read command {“adapted to receive DMA read and write instructions encapsulated over a memory bus”, see Fig. 59a, [0287], last sentence};
providing exclusive bus access {“instructions encapsulated over a memory bus” such as “DDR data transmission” (see Fig. 59a, [0287], last sentence} to the DMA controller for the sequential read operation {“point to consecutive entries in memory so as to direct incoming packets to [read/write] consecutive memory locations.”, see Fig. 59a, [0283], last sentence};
in response to the read command {“a memory bus 5916 that can respond to DMA read/write requests.”, see Fig. 59a, [0287], 3rd sentence}, reading data from an address range {such block data interfaces include address mapping “An IOMMU can map received data to physical addresses of a system address space.”, see Figs. 59a and 59b, [0310], 1st sentence, and [0387], first two sentences} associated with the address of data {“interface capable of block data transfers over memory bus 5916”, see Fig. 59a, [0287]}; and terminating reading the data prior {“terminate traffic, provide transparent services, and then virtually inject the traffic back to the intended target” (see Fig. 14, [0142], last two sentences)} to reading an entirety of the set of data {“traffic includes read operation as “offload processor whose session is complete/terminated)” (see Fig. 64, [0348], last two sentences) where the session include read/write DMAs per context “initiate a bulk transfer of these contents to an external low latency memory” (see Fig. 59a, [0306]} in response to a signal from the DMA controller indicating releasing the exclusive bus access {“provisioning agent can be an entity on the host processor that initializes and interacts with virtual function drivers. The virtual function driver can be responsible for [and conversely releasing] providing the VF with the virtual address of the memory space where a DMA needs to be carried out [/terminated]”, see Fig. 78, [0407]}; “an arbitration circuit before being sent out over an output port” ([0415]) as an example circuit “scheduler 8200 can receive incoming packets through an arbitration circuit that is interposed between a memory bus and several such scheduler circuits” }.
Benveniste and Dalal are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Benveniste and Dalal before him or her, to modify Benveniste’s “Station 204A” (see Fig. 2b, [0115]) incorporating Dalal’s “DMA controller” (see Fig. 59a, [0287]).
The suggestion/motivation for doing so would have been to implement a method for efficiently providing network tunneling services for network overlay operations such as incoming packet data is converted to a memory bus compatible protocol and transferred to offload processors for further modifications that are sent back onto the memory bus for transfer to a network, memory unit, or host processor (Dalal [0366]).
Therefore, it would have been obvious to combine Dalal with Benveniste to obtain the invention as specified in the instant claim(s).
As per claim 13, the rejection of claim 12 is incorporated and Dalal discloses wherein the read command includes a first signal indicating the sequential read operation {“ reads and writes (r/w) [consecutively/sequentially] as well as reading out a cache (R) and writing in a cache (W) to facilitate context switches.”, see Figs. 30 and 31, [0175]}, a second signal indicating the address {“ the original SDRAM in the system (not shown) can provide similar operations during packet-level meta-data processing”, see Fig. 31, [0174]}, and a third signal indicating a size in bytes to be read {“ Each of these packets gets quantized to a cell size (64 B)”, see Figs. 29 and 30, [0167]} from the address per clock cycle {“ time accommodated by the [clock cycle] 800 MHz AMBA/AXI switch plane”, see Figs. 29 and 30, [0167]}.
As per claim 14, the rejection of claim 12 is incorporated and Dalal discloses further comprising:
releasing the exclusive bus access in response to the signal {“provisioning agent can be an entity on the host processor that initializes and interacts with virtual function drivers. The virtual function driver can be responsible for [and conversely releasing] providing the VF with the virtual address of the memory space where a DMA needs to be carried out [/terminated]”, see Fig. 78, [0407]}}.
As per claim 15, the rejection of claim 12 is incorporated and Dalal discloses wherein terminating reading the data comprises stopping sequential lookahead reading {“[lookahead reading/writing] execution resource can be optimized to reduce the penalty and overhead associated with context switch between resources”, see Fig. 59a, [0298] last two sentences}.
As per claim 16, the rejection of claim 12 is incorporated and Dalal discloses wherein the method is performed by a device storing the data in internal memory {a device “each wimpy core can serve data from local memory”, see Fig. 4, [0113], 2nd sentence}, and wherein reading the data includes reading the data from the internal memory {“[lookahead reading/writing] execution resource can be optimized to reduce the penalty and overhead associated with context switch between resources”, see Fig. 59a, [0298] last two sentences}.
Referring to claim 17 are system claims, reciting claim functionality corresponding to the method claim of claims 12-16, respectively, thereby the rationale relied upon as recited in claims 12-16 recited above, inter alia, Dalal discloses wherein the DMA controller is configured to:
receive a trigger indicating a burst data transfer {“rate limiting allows bursting to consume buffer space”, see Fig. 24, [0164], 2nd sentence} of a set of data from a first device {“During an actual context switch [triggered from a first device]…”, see Fig. 59a, [0306]} of the plurality of devices to a second device of the plurality of devices {“a context stored by one offload processor can be resumed by a [second device] different offload processor” (see Fig. 60-0, [0320])}.
The 103 motivation for this independent claim relied upon as recited in claim 12 above.
As per claim 18, the rejection of claim 17 is incorporated and Dalal discloses wherein the DMA controller is configured to transmit the second signal to the first device {“After the Xockets DIMMs differentiate between various [second signal] input streams to the device with reads and writes, it can convert requests and protocols,”, see Fig. 59a, [0213], 2nd sentence} in response to determining a data error {“Accounting, logging, and diagnostic scripts [for data errors]. Owners of particular connections can probe the functioning and statistics of their socket independently. Providers may log and account for the services they provide exploiting the fast random access of the RLDRAM”, [0211].
As per claim 19, the rejection of claim 17 is incorporated and Dalal discloses wherein the DMA controller is configured to transmit the second signal to the first device in response to determining a lack of access permission for reading the data {“application-level VPNs are tractable at high bandwidths, the aforementioned problem of simultaneous Intrusion Prevention Systems (IPS)” where a “’cloud-in-cloud’ hacks like CloudPassage to create an artificial transport hierarchy” determines a lack of access permission, see Figs. 15 and 16, [0139]}.
As per claim 20, the rejection of claim 17 is incorporated and Dalal discloses wherein the first device comprises a peripheral device {“transport packet data to one or more computational units”, see Fig. 59a, [0262] 1st sentence}, and wherein the second device comprises a memory device {“compatible with an existing memory module”, see Fig. 59a, [0262] 1st sentence}, wherein the processor core is configured to use the memory device as system memory {“A system memory bus 5916 can be a system memory bus”, see Fig. 59a, [0262], last sentence}.
Response to Arguments
Applicant’s arguments filed on 11/29/2025 have been considered but deemed moot in view of the following explanation:
Applicant alleges that the teachings of Benveniste does not explicitly disclose “terminate the read operation [sic]” as recited in the respective independent claims 1, 12, and 17 (Remarks pages 8 and 9).
The Examiner respectfully understands such assertions, and accordingly respectively updated such contested claim limitations with the maintained Dalal reference.
For these reasons the current ground of rejection(s) is respectfully maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “DMA controller”, “read operation”, or “being reading at least a portion”: US 10282328 B2, US 11023803 B2, US 11270201 B2, US 11373266 B2, US 11386029 B2, US 11822812 B2, US 12524360 B1, US 20110032995 A1, US 20120303841 A1, US 20190286589 A1, US 20220083486 A1, and US 20260079867 A1.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
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