Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-21 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/24/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-21 are rejected 35 U.S.C. 103 as being unpatentable over Benveniste (USPGPUB No. 2014/0010081 A1) in view of Dalal et al. (USPGPUB No. 2023/0231811 A1, hereinafter referred to as Dalal) and further in view of ONG et al. (USPGPUB No. 2023/0096468 A1, hereinafter referred to as ONG).
Referring to claim 1, Benveniste discloses a switch comprising {“Packet Switching in Radio Channels”, see Fig. 1, [0014], 1st sentence}:
receive an identifier of data to be transferred {“ Station 204A is supplied with data from a file transfer data source 214A [filename/identifier],”, see Fig. 2a, [0111], last two sentences; other data types “email, data backup” and “voice and video data” ([0111]} from a source device to a destination device {“a single frame to any destination.”, see Fig. 2b, [0113]};
begin an operation of the data {“Station 204A is supplied with data from the file transfer data source 214A,”, see Fig. 2b, [0115], 2nd sentence} by providing a set of signals {“Each wireless station 204A and 204B can determine the urgency class of its pending packets according to a [providing a set of signals] scheduling algorithm”, see Fig. 2b, [0115], 4th sentence};
Benveniste does not appear to explicitly disclose wherein the controller is a direct memory access (DMA) controller; wherein the DMA controller configured to:
begin an operation of the data by providing a set of signals; that specifies to the source device an expected size of the data and that specifies to begin retrieving at least a portion of the data;
determine to terminate the operation before the expected size of the data has been met;
and terminate read operation;
However, Dalal discloses wherein the controller is a direct memory access (DMA) controller {“DMA controller”, see Fig. 59a, [0287]}; wherein the DMA controller configured to:
begin an operation of the data {“the downstream resource can begin execution on the data.”, see Fig. 59a, [0289]} by providing a set of signals {“adapted to respond to these [set of signals] instructions in the form of data reads/data writes to the [DMA controller] DMA master”, see Fig. 2b, [0115], 4th sentence}; that specifies to the source device {“from the accessor to the [source/destination device] resource interface”, see Fig. 59a, [0289]} an expected size of the data {“an aperture with a hardware [data] size supported”, [0286], 2nd sentence} and that specifies to begin retrieving at least a portion of the data {“packets gets [portioned] quantized to a cell size (64 B), and so the transfer time increases with a worst case of 65B packets+metadata”, [0167], last two sentences};
determine to terminate the operation {“To parameterize packet inter-arrival times and bursting, 200 terminating client connections per Xockets DIMM and several thousand switched flows per DIMM are assumed” ([0161], 1st sentence)} before the expected size of the data has been met {“packets gets quantized to a cell size (64 B), and so the transfer time increases with a worst case of 65B packets+metadata”, [0167], last two sentences};
and terminate read operation {“minimal overhead context switching between terminated sessions” (see Fig. [0412], 1st sentence) as such sessions include both read/write operation(s)}.
Benveniste and Dalal are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Benveniste and Dalal before him or her, to modify Benveniste’s “Station 204A” (see Fig. 2b, [0115]) incorporating Dalal’s “DMA controller” (see Fig. 59a, [0287]).
The suggestion/motivation for doing so would have been to implement a method for efficiently providing network tunneling services for network overlay operations such as incoming packet data is converted to a memory bus compatible protocol and transferred to offload processors for further modifications that are sent back onto the memory bus for transfer to a network, memory unit, or host processor (Dalal [0366]).
Therefore, it would have been obvious to combine Dalal with Benveniste to obtain the invention as specified in the instant claim(s).
Neither Beneviste nor Dalal appears to explicitly disclose determine to terminate the operation before the expected size of the data has been met;
and terminate read operation;
Furthermore, Ong discloses determine to terminate the operation {“the ITD 420 can insert the [determine to terminate] next bit flag/tag into an end-of-packet (EOP) field, an EOP delimiter (EPD), end-of-stream delimiter (ESD), and/or other like field of the Rx frame/packet” [0045], 4th sentence)} before the expected size of the data has been met {“if a frame that is expected to be received [and an expected size] within a specific cycle does not appear until the next cycle” (see Figs. 1, 2, and 3, [0044], last three sentences)};
and terminate read operation {“to terminate a normal [read/write] data transmission;” [0272], last sentence}.
Benveniste/Dalal and Ong are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Benveniste/Dalal and Ong before him or her, to modify Benveniste/Dalal’s device incorporating Ong’s “NIC 468” as well as subcomponent “in-transit data unit detectors (ITD) 420-M and 420-N” (see Fig. 4, [0035], 1st sentence).
The suggestion/motivation for doing so would have been to implement time-aware networks, time-sensitive applications, edge computing frameworks, data processing, network communication, and communication system implementations, and in particular, techniques for providing in-transit packet detection to reduce real-time packet jitter (ONG [0001]).
Therefore, it would have been obvious to combine Ong with Benveniste/Dalal to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Dalal discloses wherein the controller is configured to receive the identifier of the data by receiving a source address and a size of the data {“communicates the session color, size, and [source] starting physical address to the scheduler circuit upon session initialization”, see Fig. 59a, [0306]}.
As per claim 3, the rejection of claim 1 is incorporated and Dalal discloses wherein the controller is configured to receive the identifier of the data as a trigger {“During an actual context switch [trigger]…”, see Fig. 59a, [0306]} from the source device {“During an actual context switch [trigger], a scheduler circuit can identify the session context [from which the identifier of the data]”, see Fig. 59a, [0306]}.
As per claim 4, the rejection of claim 1 is incorporated and Benveniste discloses wherein the source device comprises an analog-to-digital converter (ADC) {the source device “radio range between wireless stations 102, 104A,” (see Fig. 1a, [0003]) including an ADC to convert from analog signal via antenna to wireline “Much like 10/100 Mbps Ethernet wired LANs”, [0011] via “MAC layer” ([0112], 1st sentence)}, and wherein the destination device comprises a memory device {“streams received at each node, place a packet in the access buffer; the buffered packet”, see Fig. 1a, [0149], 2nd sentence}.
As per claim 5, the rejection of claim 1 is incorporated and Dalal discloses wherein the source device comprises a peripheral device {“cooperative mechanism between a scheduler circuit and the OS on the [peripheral device] offload processor 5908i”, see Fig. 59a, [0306]}, and wherein the destination device comprises a memory device {“initiate a bulk transfer of these contents to an [destination memory device] external low latency memory”, see Fig. 59a, [0306]}.
As per claim 6, the rejection of claim 1 is incorporated and Ong discloses further wherein the DMA controller is configured to terminate the read operation {“to terminate a normal [read/write] data transmission;” [0272], last sentence)} based on an indication of a transfer error {indicating “messages or packets more robust against noise, [transfer error] channel interference, limited channel bandwidth, and/or other errors”, [0280], 1st sentence}, further wherein the DMA controller is configured to terminate the read operation {“to terminate a normal [read/write] data transmission;” [0272], last sentence)}.
As per claim 7, the rejection of claim 1 is incorporated and Ong discloses wherein the DMA controller is configured to determine to terminate the read operation {“to terminate a normal [read/write] data transmission;” [0272], last sentence)} based on an indication of a lack of access permission {“host memory objects that can be comprehended, manipulated, or otherwise [access permission] consumable by the NIC 468, such as for security and reliability purposes”, see Figs. 12 and 4, [0031], last sentence)}, further wherein the DMA controller is configured to terminate the read operation {“PE 404 may be, or include, an (R)DMA engine for processing (R)DMA packets” and terminate as claimed, [0037], last sentence}.
As per claim 8, the rejection of claim 1 is incorporated and Ong discloses wherein the DMA controller is configured to determine to terminate the read operation {“to terminate a normal [read/write] data transmission;” [0272], last sentence)} based on an indication of a higher-priority transaction {“Different PCP values can be used to prioritize different classes of traffic”, last three sentences}, further wherein the DMA controller is configured to terminate the read operation {“PE 404 may be, or include, an (R)DMA engine for processing (R)DMA packets” and terminate as claimed, [0037], last sentence} and resume the read operation of the data after completion of the higher-priority transaction {“task switch can take place without incurring jitter-related delays/latency”, see Fig. 4, [0059], last sentence)}.
As per claim 9, the rejection of claim 1 is incorporated and Ong discloses wherein the DMA controller is configured to determine to terminate the read operation {“to terminate a normal [read/write] data transmission;” [0272], last sentence)} based on an indication of unused capacity {“there are no more packets/PDUs inflight or otherwise still in the buffer 411”, see Fig. 4, [0059], last sentence} in a first in first out (FIFO) buffer {“Rx buffer/queue may be a first in first out (FIFO) buffer and/or a buffer/queue” ([0019], 3rd sentence) for a further transaction {“the networking protocol may not always guarantee that the next frame is back-to-back [further transaction]”, see Fig. 4, [0045], last two sentences}, further wherein the DMA controller is configured to terminate the read operation {“PE 404 may be, or include, an (R)DMA engine for processing (R)DMA packets” and terminate as claimed, [0037], last sentence}.
As per claim 10, the rejection of claim 1 is incorporated and Dalal discloses wherein the DMA controller is configured to begin the read operation by causing the source device {“issue the correct set of write and read commands to Xockets Memory 1222”, see Fig. 12, [0132], last sentence} to provide bus access to the DMA controller {“Additional DIMMs (e.g., 1232) and SSDs (e.g., 1224) can be integrated efficiently with RDMA capable NICs [over a bus]”, see Fig. 12, [0132], 2nd sentence} for the read operation {“attachment to a memory bus 5916 that can respond to DMA read/write requests.”, see Fig. 59a, [0287], 3rd sentence}, further wherein the DMA controller is configured to terminate the read operation {“terminate traffic, provide transparent services, and then virtually inject the traffic back to the intended target” (see Fig. 14, [0142], last two sentences} by transmitting a signal to the source device that causes the source device to stop the read operation {“that [DMA read/write] traffic includes read operation as “offload processor whose session is complete/terminated)” (see Fig. 64, [0348], last two sentences) where the session include read/write DMAs per context “initiate a bulk transfer of these contents to an external low latency memory” (see Fig. 59a, [0306])} and release the bus access {“tunneled over the DDR bus to between the virtual switch the x86 processors”, see Fig. 4, [0110], last sentence}.
As per claim 11, the rejection of claim 1 is incorporated and Dalal discloses wherein the DMA controller is further configured to:
move the data from the read operation {“transparent de-duplication for availability, and proprietary synchronization techniques for moving data to places of locality [buffer(s)]”, see Fig. 12, [0131]} into a first in first out (FIFO) buffer {“rate limiting allows bursting to consume buffer space”, see Fig. 24, [0164], 2nd sentence};
and write the data from the FIFO buffer to the destination device {“can be placed on each ARM processor to federate querying across [other destination devices] several processors through the rack.”, see Fig. 12, [0133], last sentence}.
Referring to claim 12, Benveniste discloses a method comprising:
receiving a command {“Station 204A is supplied [via a command] with data from the file transfer data source 214A,”, see Fig. 2b, [0115], 2nd sentence} from a controller {“use of an intelligent controller”, see Fig. 1, [0208], last sentence}, wherein the command indicates an operation having an address of data {“it provides address mapping”, see Fig. 1, [0026]; another type of addressing provided by “MAC dwell-time is the time spent by a frame in the MAC layer”, [0258], 1st two sentences};
Benveniste does not appear to explicitly disclose wherein the command indicates an operation having an address of data {“it provides address mapping”, see Fig. 1, [0026]; another type of addressing provided by “MAC dwell-time is the time spent by a frame in the MAC layer”, [0258], 1st two sentences} and indicates an expected size of a set of data associated with the command {“tiered contention multiple access (TCMA) period 218” (see Fig. 2b, [0114]) that specifies “operates during period 218 minimizes the chance of [begin retrieving/sending] collisions between stations sharing the medium”, [0116], 1st sentence};
receiving a read command from a direct memory access (DMA) controller, wherein the read command indicates a sequential read operation having an address of data and indicates an expected size of a set of data associated with the read command;
providing exclusive bus access to the DMA controller for the sequential read operation;
in response to the read command, reading data from an address range associated with the address of data; and
terminating reading the data prior to reading an entirety of the set of data in response to a signal from the DMA controller indicating releasing the exclusive bus access.
However, Dalal discloses wherein the command indicates an operation having an address of data {“address [of data residing] the local Xockets DIMM upon requesting a certain address range”, see Fig. 12, [0132], 3rd sentence} and indicates an expected size of a set of data associated with the command {“an aperture with a hardware [expected] size supported”, [0286], 2nd sentence};
receiving a read command from a direct memory access (DMA) controller {“DMA controller”, see Fig. 59a, [0287]}, wherein the read command indicates a sequential read operation {“point to consecutive entries in memory so as to direct incoming packets to [read/write] consecutive memory locations.”, see Fig. 59a, [0283], last sentence} having an address of data and indicates an expected size of a set of data {“if the descriptor is associated with a specific [/expected] data structure for handling incoming packets.” Such a data structure with a size as claimed, see Fig. 59a, [0283], 1st sentence} associated with the read command {“adapted to receive DMA read and write instructions encapsulated over a memory bus”, see Fig. 59a, [0287], last sentence};
Benveniste and Dalal are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Benveniste and Dalal before him or her, to modify Benveniste’s “Station 204A” (see Fig. 2b, [0115]) incorporating Dalal’s “DMA controller” (see Fig. 59a, [0287]).
The suggestion/motivation for doing so would have been to implement a method for efficiently providing network tunneling services for network overlay operations such as incoming packet data is converted to a memory bus compatible protocol and transferred to offload processors for further modifications that are sent back onto the memory bus for transfer to a network, memory unit, or host processor (Dalal [0366]).
Therefore, it would have been obvious to combine Dalal with Benveniste to obtain the invention as specified in the instant claim(s).
Neither Benveniste nor Dalal discloses providing exclusive bus access to the DMA controller for the sequential read operation;
in response to the read command, reading data from an address range associated with the address of data; and terminating reading the data prior to reading an entirety of the set of data in response to a signal from the DMA controller indicating releasing the exclusive bus access;
However, Ong discloses providing exclusive bus access {“separated by a minimum IPG, and packet2 experiences SySBus congestion”, see Fig. 5, [0060], 1st sentence} to the DMA controller for the sequential read operation {sequence of events for [read/write] two back-to-back Ethernet packets (e.g., packet1 and packet2) that arrive over a communication medium 501”, see Fig. 5, [0060], 1st sentence};
in response to the read command {“reach steady-state synchronization with the [read command] received packet's timing”, see Fig. 5, [0060]}, reading data from an address range {“specifies the station(s) for which the MAC frame is intended [address range]”, see Fig. 5, [0061], 1st sentence} associated with the address of data {“includes a destination address field (e.g., 6 octets)”, [0287], 1st sentence};
and terminating reading {“to terminate a normal [read/write] data transmission;” [0272], last sentence} the data prior to reading an entirety of the set of data {“if a frame that is expected to be received [and an expected size] within a specific cycle does not appear until the next cycle” (see Figs. 1, 2, and 3, [0044], last three sentences)} in response to a signal {“the NIC 468 initiates an [signal] interrupt (e.g., IRQ or the like)”, see Fig. 4, [0054] last sentence} from the DMA controller indicating releasing the exclusive bus access {“an interrupt (e.g., IRQ) is generated and signaled to the host processor to indicate that those descriptors 473 have been released” and subsequently the exclusive bus access release, see Fig. 4, [0056], 1st sentence}.
As per claim 13, the rejection of claim 12 is incorporated and Dalal discloses wherein the read command includes a first signal indicating the sequential read operation {“ reads and writes (r/w) [consecutively/sequentially] as well as reading out a cache (R) and writing in a cache (W) to facilitate context switches.”, see Figs. 30 and 31, [0175]}, a second signal indicating the address {“ the original SDRAM in the system (not shown) can provide similar operations during packet-level meta-data processing”, see Fig. 31, [0174]}, and a third signal indicating a size in bytes to be read {“ Each of these packets gets quantized to a cell size (64 B)”, see Figs. 29 and 30, [0167]} from the address per clock cycle {“ time accommodated by the [clock cycle] 800 MHz AMBA/AXI switch plane”, see Figs. 29 and 30, [0167]}.
As per claim 14, the rejection of claim 12 is incorporated and Ong discloses further comprising:
releasing the exclusive bus access {“an interrupt (e.g., IRQ) is generated and signaled to the host processor to indicate that those descriptors 473 have been released” and subsequently the exclusive bus access release, see Fig. 4, [0056], 1st sentence} in response to the signal {“the NIC 468 initiates an [signal] interrupt (e.g., IRQ or the like)”, see Fig. 4, [0054] last sentence}.
As per claim 15, the rejection of claim 12 is incorporated and Ong discloses wherein terminating reading the data comprises stopping sequential lookahead reading {“avoiding relatively high context switch costs due to a high in-coming packet rate [lookahead reading]”, see Fig. 2, [0025] 2nd sentence}.
As per claim 16, the rejection of claim 12 is incorporated and Dalal discloses wherein the method is performed by a device storing the data in internal memory {a device “each wimpy core can serve data from local memory”, see Fig. 4, [0113], 2nd sentence}, and wherein reading the data includes reading the data from the internal memory {“[lookahead reading/writing] execution resource can be optimized to reduce the penalty and overhead associated with context switch between resources”, see Fig. 59a, [0298] last two sentences}.
Referring to claim 17 are system claims, reciting claim functionality corresponding to the method claim of claims 12-16, respectively, thereby the rationale relied upon as recited in claims 12-16 recited above, inter alia, Dalal discloses wherein the DMA controller is configured to:
receive a trigger indicating a burst data transfer {“rate limiting allows bursting to consume buffer space”, see Fig. 24, [0164], 2nd sentence} of a set of data from a first device {“During an actual context switch [triggered from a first device]…”, see Fig. 59a, [0306]} of the plurality of devices to a second device of the plurality of devices {“a context stored by one offload processor can be resumed by a [second device] different offload processor” (see Fig. 60-0, [0320])}.
The 103 motivation for this independent claim relied upon as recited in claim 12 above.
As per claim 18, the rejection of claim 17 is incorporated and Dalal discloses wherein the DMA controller is configured to transmit the second signal to the first device {“After the Xockets DIMMs differentiate between various [second signal] input streams to the device with reads and writes, it can convert requests and protocols,”, see Fig. 59a, [0213], 2nd sentence} in response to determining a data error {“Accounting, logging, and diagnostic scripts [for data errors]. Owners of particular connections can probe the functioning and statistics of their socket independently. Providers may log and account for the services they provide exploiting the fast random access of the RLDRAM”, [0211].
As per claim 19, the rejection of claim 17 is incorporated and Dalal discloses wherein the DMA controller is configured to transmit the second signal to the first device in response to determining a lack of access permission for reading the data {“application-level VPNs are tractable at high bandwidths, the aforementioned problem of simultaneous Intrusion Prevention Systems (IPS)” where a “’cloud-in-cloud’ hacks like CloudPassage to create an artificial transport hierarchy” determines a lack of access permission, see Figs. 15 and 16, [0139]}.
As per claim 20, the rejection of claim 17 is incorporated and Dalal discloses wherein the first device comprises a peripheral device {“transport packet data to one or more computational units”, see Fig. 59a, [0262] 1st sentence}, and wherein the second device comprises a memory device {“compatible with an existing memory module”, see Fig. 59a, [0262] 1st sentence}, wherein the processor core is configured to use the memory device as system memory {“A system memory bus 5916 can be a system memory bus”, see Fig. 59a, [0262], last sentence}.
As per claim 21, the rejection of 20 is incorporated and ONG discloses wherein the peripheral device comprises an analog-to- digital converter (ADC) {“[peripheral device] battery monitor/charger 1282 may also include an analog-to-digital (ADC) converter”, Fig. 12, [0140]}.
Response to Arguments
Applicant’s arguments, filed on 07/24/2026, have been considered however rendered moot in view of the new ground of rejection(s). The Dala [0288] and [0286] describing a set of signals via “hardware size supported… may be coded into the descriptor”, a descriptor understood by one of ordinary skill in the art according to a protocol retrieved/transmitted to a storage medium, such as “VF virtual function” or hard drive/disk/disc known for storing a plurality of signals in binary format among a plurality of formats (e.g. hexadecimal, ASCII coding) to name a few.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art claim 1’s “DMA controller”, “identifier of data”, or “begin a read operation”: US 20250238381 A1, US 20220147476 A1, US 10929315 B2, US 20190243781 A1, and US 20180260343 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.B./
Examiner
Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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