Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190155744 A1 (Srinivasan, et al., hereinafter Srinivasan) in view of US 20200117387 A1 (Cadloni, et al., hereinafter Cadloni).
Regarding claim 1, Srinivasan teaches a system comprising: a plurality of memory devices; (Srinivasan, [0016]: “A number of embodiments of the present disclosure include sending a single command (e.g., in parallel) from a system controller to one or more memory devices to initiate a LWP search, and results in a response from the memory devices providing the system controller with LWP information.”) and a processing device operatively coupled to the plurality of memory devices (Srinivasan, [0021]: “Computing system 100 includes a memory system 104 coupled to a host 102 through an interface 106.”; Srinivasan, [0023]: “Host 102 can include a number of processors 105 (e.g., parallel processors, co-processors, etc.) coupled to a memory and bus control 107. The processor 105 can be a number of microprocessors, or some other type of controlling circuitry, such as a number of application-specific integrated circuits (ASICs), for example. Other components of the computing system 100 may also have processors”); determining last written page (LWP) data for one or more memory devices of the plurality of memory devices; (Srinivasan, [0013]: “An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.”) and performing a scan on one or more pages of the one or more memory devices of the plurality of memory devices based on the LWP data. (Srinivasan, [0068]: “Responsive to determining the particular word line corresponding to the last written page of a block (e.g., WL6 in this example), a subsequent binary search of the sub-blocks SB0 through SB5 coupled to word line WL6 can be performed to determine in which particular sub-block the last written page of the block is located.”)
Srinivasan does not appear to explicitly teach a processor configured to perform operations comprising: detecting a scan trigger event.
Cadloni cures the deficiencies of Srinivasan. Cadloni teaches a device including a processor configured to perform operations comprising: detecting a scan trigger event; (Cadloni, [0027]: “The processing logic for method 200 can be triggered by a background scan trigger event from a set of background scan trigger events. For example, at block 202, a trigger event can occur in response to a timer reaching a timing threshold, or at block 204, a trigger event can occur in response to event tracking data (e.g. a count of I/O events) reaching an event limit threshold.”)
Srinivasan and Cadloni are both directed to searches/scans in a memory system. It would have been obvious to one of ordinary skill in the art at the time of effective filing to combine the memory system of Srinivasan with the detection of a scan trigger event of Cadloni in order to include a specific “scan trigger event” to trigger a scan/search of a memory sub-system. One would have the motivation to combine in order to improve functionality of the memory device.
Regarding claim 9, Srinivasan teaches a method comprising: determining last written page (LWP) data for one or more memory devices of a plurality of memory devices in the memory sub-system; (Srinivasan, [0013]: “An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.”)and performing a scan on one or more pages of the one or more of the plurality of memory devices based on the LWP data. (Srinivasan, [0068]: “Responsive to determining the particular word line corresponding to the last written page of a block (e.g., WL6 in this example), a subsequent binary search of the sub-blocks SB0 through SB5 coupled to word line WL6 can be performed to determine in which particular sub-block the last written page of the block is located.”)
Srinivasan does not explicitly teach detecting a scan trigger event in a memory sub-system.
Cadloni cures the deficiencies of Srinivasan. Cadloni teaches detecting a scan trigger event in a memory sub-system. (Cadloni, [0027]: “The processing logic for method 200 can be triggered by a background scan trigger event from a set of background scan trigger events. For example, at block 202, a trigger event can occur in response to a timer reaching a timing threshold, or at block 204, a trigger event can occur in response to event tracking data (e.g. a count of I/O events) reaching an event limit threshold.”)
Srinivasan and Cadloni are both directed to searches/scans in a memory system. It would have been obvious to one of ordinary skill in the art at the time of effective filing to combine the memory system of Srinivasan with the detection of a scan trigger event of Cadloni in order to include a specific “scan trigger event” to trigger a scan/search of a memory sub-system. One would have the motivation to combine in order to improve functionality of the memory device.
Regarding claim 15. Srinivasan teaches a non-transitory computer-readable storage medium (Srinivasan, [0022]: “Example hosts 102 can include laptop computers, personal computers, digital cameras, digital recording and playback devices, mobile telephones, PDAs (personal digital assistants), memory card readers, interface hubs, sensors, and Internet-of-Things (IoT) enabled devices, among other host systems.”) comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining last written page (LWP) data for one or more memory devices of a plurality of memory devices in the memory sub-system; (Srinivasan, [0013]: “An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.”) and performing a scan on one or more pages of the one or more of the plurality of memory devices based on the LWP data. (Srinivasan, [0068]: “Responsive to determining the particular word line corresponding to the last written page of a block (e.g., WL6 in this example), a subsequent binary search of the sub-blocks SB0 through SB5 coupled to word line WL6 can be performed to determine in which particular sub-block the last written page of the block is located.”) Srinivasan does not explicitly teach detecting a scan trigger event in a memory sub-system.
Cadloni cures the deficiencies of Srinivasan. Cadloni teaches detecting a scan trigger event in a memory sub-system. (Cadloni, [0027]: “The processing logic for method 200 can be triggered by a background scan trigger event from a set of background scan trigger events. For example, at block 202, a trigger event can occur in response to a timer reaching a timing threshold, or at block 204, a trigger event can occur in response to event tracking data (e.g. a count of I/O events) reaching an event limit threshold.”)
Srinivasan and Cadloni are both directed to searches/scans in a memory system. It would have been obvious to one of ordinary skill in the art at the time of effective filing to combine the memory system of Srinivasan with the detection of a scan trigger event of Cadloni in order to include a specific “scan trigger event” to trigger a scan/search of a memory sub-system. One would have the motivation to combine in order to improve functionality of the non-transitory computer-readable storage medium.
Allowable Subject Matter
Claims 2-8, 10-14, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art of record does not teach a system comprising: a plurality of memory devices; and a processing device operatively coupled to the plurality of memory devices and configured to perform operations comprising: detecting a scan trigger event; determining last written page (LWP) data for one or more memory devices of the plurality of memory devices; and performing a scan on one or more pages of the one or more memory devices of the plurality of memory devices based on the LWP data, wherein the scan comprises a media scan, and wherein the scan trigger event for the media scan comprises an expiration of a pre-determined time interval.
Claims 3-5 are objected to as dependent upon claim 2.
Regarding claim 6, the prior art of record does not teach a system comprising: a plurality of memory devices; and a processing device operatively coupled to the plurality of memory devices and configured to perform operations comprising: detecting a scan trigger event; determining last written page (LWP) data for one or more memory devices of the plurality of memory devices; and performing a scan on one or more pages of the one or more memory devices of the plurality of memory devices based on the LWP data, wherein the scan comprises a read disturb scan, and wherein the scan trigger event for the read disturb scan comprises a current read count for a memory device satisfying a threshold criterion.
Claims 7-8 are objected to as dependent upon claim 6.
Regarding claim 10, the prior art of record does not teach a method comprising: detecting a scan trigger event in a memory sub-system; determining last written page (LWP) data for one or more memory devices of a plurality of memory devices in the memory sub-system; and performing a scan on one or more pages of the one or more of the plurality of memory devices based on the LWP data, wherein the scan comprises a media scan, and wherein the scan trigger event for the media scan comprises an expiration of a pre-determined time interval.
Claims 11-12 are objected to as dependent upon claim 10.
Regarding claim 13, the prior art of record does not teach a method comprising: detecting a scan trigger event in a memory sub-system; determining last written page (LWP) data for one or more memory devices of a plurality of memory devices in the memory sub-system; and performing a scan on one or more pages of the one or more of the plurality of memory devices based on the LWP data, wherein the scan comprises a read disturb scan, and wherein the scan trigger event for the read disturb scan comprises a current read count for a memory device satisfying a threshold criterion.
Claim 14 is objected to as dependent upon claim 13.
Regarding claim 16, the prior art of record does not teach a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: detecting a scan trigger event in a memory sub-system; determining last written page (LWP) data for one or more memory devices of a plurality of memory devices in the memory sub-system; and performing a scan on one or more pages of the one or more of the plurality of memory devices based on the LWP data, wherein the scan comprises a media scan, and wherein the scan trigger event for the media scan comprises an expiration of a pre-determined time interval.
Claims 17-18 are objected to as dependent upon claim 16.
Regarding claim 19, the prior art of record does not teach a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: detecting a scan trigger event in a memory sub-system; determining last written page (LWP) data for one or more memory devices of a plurality of memory devices in the memory sub-system; and performing a scan on one or more pages of the one or more of the plurality of memory devices based on the LWP data, wherein the scan comprises a read disturb scan, and wherein the scan trigger event for the read disturb scan comprises a current read count for a memory device satisfying a threshold criterion.
Claim 20 is objected to as dependent upon claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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