Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang US Patent Application (20230335170), hereinafter “Tang” and Wang et al., US Patent Application (20240107760), hereinafter “Wang”
Regarding claim 1 Tang teaches a semiconductor device, three-dimensional (3D) semiconductor device [Tang para 0057] comprising: a first stack of conductive layers and isolating layers alternating with each other along a first direction a plurality of tiers of control stacking on top of the LSGs 332 to form a film stack 335 of alternating conductive and dielectric layers. [Tang para 0062] The alternating dielectric stack 1164 extends in a lateral direction that is parallel to the front surface 330f of the substrate 330. [Tang para 0108]; wherein a first portion of the first stack comprises: one or more top select gate (TSG) layers of the conductive layers in a first part of the first portion of the first stack a tier of top select gates (TSGs) 334 over the stack of control gates 333 [Tang para 0063] FIG. 16 illustrates a cross-sectional view of an exemplary structure 1600, … stack 335 is similar to the film stack previously discussed with reference to FIGS. 3 and 4. After replacing the sacrificial layers with conductive layers, … [Tang para 0129 and see Fig. 16 below (i.e. right hand side of the figure)], one or more conductive layers of the conductive layers corresponding to the one or more TSG layers in a second part of the first portion of the first stack, the second part of the first portion of the first stack being connected to the second stack, FIG. 16 illustrates a cross-sectional view of an exemplary structure 1600, … stack 335 is similar to the film stack previously discussed with reference to FIGS. 3 and 4. After replacing the sacrificial layers with conductive layers, … [Tang para 0129 and see Fig. 16 (i.e. Left hand side of the figure)] wherein the first part comprises a first staircase structure having one or more first stairs corresponding to the one or more TSG layers, and the second part comprises a second staircase structure having one or more second stairs corresponding to the one or more conductive layers, staircase structures 210-L and 210-R can be formed in the staircase region 210. [Tang para 0129 and see Fig. 16 (i.e. Right and Left hand side of the figure form the two staircases)] and wherein the first staircase structure and the second staircase structure are separated by a separation structure between the first part and the second part. the insulating layer 1582 can include an etch-stop layer (not shown) that protects the underlying structure until all the contact holes 1788 are formed on each staircase step 1686. [Tang para 0137 and see Fig. 16]; and
Tang does not expletively disclose but Wang teaches a second stack of dielectric layers a second stack structure including interleaved second dielectric layers and the first dielectric layers, [Wang para 0017] first dielectric layers 503 of the conductive stack structure of stack structure [Wang para 0066 and see Fig. 5] and isolating layers alternating with each other along the first direction, the dielectric stack structure and are surrounded by first and second dielectric layers 503 and 505 in dielectric portion [Wang para 0066] wherein the second stack is connected to the first stack along a second direction perpendicular to the first direction, The bottom of each word line pick-up region 103 can be aligned with a corresponding second dielectric layer 505, as opposed to first dielectric layer 503, and the corresponding second dielectric layer 505 can be partially replaced with interconnect line 206 to form the electrical connection between vertical contact 202 [Wang para 0071]
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Tang discloses three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures
Wang discloses a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures.
Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Tang and Wang in the art of three-dimensional (3D) memory devices and operating the same, as one of ordinary skill in the art would have recognized that the results of the combination were predictable as the combined teachings and technologies were well known in the art. Wang improves Tang’s systems, methods and/or apparatus by adding a second stack of layers to the 3D structure which overcomes density issues in the formation of the structure..
Regarding claim 2 Tang and Wang teach claim 1 in addition Tang teaches wherein a number of the one or more first stairs is equal to a number of the one or more second stairs. [Tang see Fig. 16 above]
Regarding claim 3 Tang and Wang teach claim 1 in addition Tang teaches further comprising: a TSG cut structure extending through the first part of the first portion of the first stack and at least one of the conductive layers in a second portion of the first stack that is adjacent to the first portion of the first stack along the first direction, the TSG cut structure configured to separate the one or more TSG layers into a plurality of TSG electrodes. top select gates (TSGs) 334 over the stack of control gates 333. The stack of TSG 334, control gates 333 and LSG 332 is also referred to as “gate electrodes. [Tang para 0063] the 3D memory structure 400 can also include one or more top select gate (TSG) cut 220. The TSG cut 220 can separate TSG 334 into two or more sub-TSGs 334-1, 334-2, 334-3, [Tang para 0084]
Regarding claim 4 Tang and Wang teach claim 3 in addition Tang teaches wherein a conductive layer of the at least one of the conductive layers comprises a first section and a second section, the memory array structure 300 includes a substrate 330, an insulating film 331 over the substrate 330, a tier of lower select gates (LSGs) 332 over the insulating film 331, and a plurality of tiers of control gates 333, also referred to as “word lines (WLs),” stacking on top of the LSGs 332 to form a film stack 335 of alternating conductive and dielectric layers. [Tang para 0062] and wherein the TSG cut structure is configured to separate the first section of the conductive layer into a plurality of layer portions, and the second section of the conductive layer connects ends of the plurality of layer portions. The TSG cut 220 can separate TSG 334 into two or more sub-TSGs 334-1, 334-2, 334-3, . . . , and can divide each memory block 103 into the memory slices 224. [Tang para 0084] one or more TSG cuts 220 can extend vertically through one or more dielectric layer pairs 1066. The TSG cuts 220 can extend laterally in x-direction [Tang para 0111]
Regarding claim 5 Tang and Wang teach claim 4 in addition Tang teaches wherein the second section of the conductive layer is between the TSG cut structure and the second stack along the second direction. The TSG cuts 220 can extend laterally in x-direction [Tang para 0111]
Regarding claim 6 Tang and Wang teach claim 3 in addition Tang teaches wherein the TSG cut structure comprises a first end and a second end opposite to the first end along the second direction, The TSG cut 220 can separate TSG 334 into two or more sub-TSGs 334-1, 334-2, 334-3 [Tang para 0084 and see Fig. 17B] and wherein the second end of the TSG cut structure is between the first staircase structure and the second stack. FIG. 17B illustrates a top-down view of the structure 1700. The cross-sectional view in FIG. 17A is in x-direction along line BB′. The contact structures 214 can be similar to the contact structures discussed previously with reference to FIGS. 2-4. [Tang para 0135 and see Fig. 17B]
Regarding claim 7 Tang and Wang teach claim 6 in addition Tang teaches wherein the second end of the TSG cut structure is between the first staircase structure and the second staircase structure. A top select gate cut 220 can be disposed, for example, in the middle of each memory finger 218 to divide a top select gate (TSG) of the memory finger 218 into two portions, and thereby can divide a memory finger into two memory slices 224, [Tang para 0061] (i.e. The length and position of the cut would be a design choice for one of ordinary skill in the art.)
Regarding claim 8 Tang and Wang teach claim 3 in addition Tang teaches further comprising TSG contact structures, one of the TSG contact structures being in contact with a corresponding one of the plurality of TSG electrodes at a corresponding one of the one or more first stairs along the first direction. top select gates (TSGs) 334 over the stack of control gates 333. The stack of TSG 334, control gates 333 and LSG 332 is also referred to as “gate electrodes. … The memory array structure 300 also includes a plurality of metal interconnect lines 343 connected with the gate electrodes through a plurality of contact structures 214. [Tang para 0063] Through the contact structures 214, metal interconnect lines formed at back-end-of-line processes can be electrically connected to each conductive layer 454. Accordingly, by using the staircase structure, each memory cell 340 in the 3D memory structure 400 can be controlled by corresponding word line 333 to perform read, write, or erase operation [Tang para 0076]
Regarding claim 9 Tang and Wang teach claim 1 in addition Tang teaches further comprising a slit structure extending along the second direction and comprising a first portion and a second portion, the first portion and the second portion of the slit structure being separated by a slit cut. a plurality of slit structures 216, extending in WL direction across the channel structure region 211 and the staircase region 210, can divide a memory block into multiple memory fingers 218 [Tang para 0061]
Regarding claim 10 Tang and Wang teach claim 9 in addition Tang teaches wherein the slit cut is between the first part of the first portion of the first stack and the second stack along the second direction. The control gates of each tier are separated by slit structures 216-1 and 216-2 through the film stack 335. The memory array structure 300 also includes a tier of top select gates (TSGs) 334 over the stack of control gates 333. [Tang para 0063]
Regarding claim 11 Tang and Wang teach claim 1 in addition Tang teaches further comprising a plurality of contact structures, wherein the plurality of contact structures extends into the second stack at different depths, and wherein one of the plurality of contact structures comprises a vertical contact and an interconnect structure connected with the vertical contact. contact structures 214 can be formed on the staircase structures 210-L and 210-R. FIG. 17A illustrates a cross-sectional view of an exemplary structure 1700 at process step S980. FIG. 17B illustrates a top-down view of the structure 1700. The cross-sectional view in FIG. 17A is in x-direction along line BB′. The contact structures 214 can be similar to the contact structures discussed previously with reference to FIGS. 2-4. [Tang para 0135 and see Fig. 17A]
Regarding claim 12 Tang teaches a method, comprising: forming a first stack of conductive layers and isolating layers alternating with each other along a first direction tacking on top of the LSGs 332 to form a film stack 335 of alternating conductive and dielectric layers. [Tang para 0062] The alternating dielectric stack 1164 extends in a lateral direction that is parallel to the front surface 330f of the substrate 330. [Tang para 0108]; wherein a first portion of the first stack comprises: one or more top select gate (TSG) layers of the conductive layers in a first part of the first portion of the first stack tier of top select gates (TSGs) 334 over the stack of control gates 333 [Tang para 0063] FIG. 16 illustrates a cross-sectional view of an exemplary structure 1600, … stack 335 is similar to the film stack previously discussed with reference to FIGS. 3 and 4. After replacing the sacrificial layers with conductive layers, … [Tang para 0129 and see Fig. 16 below (i.e. right hand side of the figure)], one or more conductive layers of the conductive layers corresponding to the one or more TSG layers in a second part of the first portion of the first stack, the second part of the first portion of the first stack being connected to the second stack FIG. 16 illustrates a cross-sectional view of an exemplary structure 1600, … stack 335 is similar to the film stack previously discussed with reference to FIGS. 3 and 4. After replacing the sacrificial layers with conductive layers, … [Tang para 0129 and see Fig. 16 (i.e. Left hand side of the figure)], wherein the first part comprises a first staircase structure having one or more first stairs corresponding to the one or more TSG layers, and the second part comprises a second staircase structure having one or more second stairs corresponding to the one or more conductive layers, staircase structures 210-L and 210-R can be formed in the staircase region 210. [Tang para 0129 and see Fig. 16 (i.e. Right and Left hand side of the figure form the two staircases)] and wherein the first staircase structure and the second staircase structure are separated by a separation structure between the first part and the second part the insulating layer 1582 can include an etch-stop layer (not shown) that protects the underlying structure until all the contact holes 1788 are formed on each staircase step 1686. [Tang para 0137 and see Fig. 16];; and
Tang does not expletively disclose but Wang teaches forming a second stack of dielectric layers a second stack structure including interleaved second dielectric layers and the first dielectric layers, [Wang para 0017] first dielectric layers 503 of the conductive stack structure of stack structure [Wang para 0066 and see Fig. 5] and isolating layers alternating with each other along the first direction, the dielectric stack structure and are surrounded by first and second dielectric layers 503 and 505 in dielectric portion [Wang para 0066] wherein the second stack is connected to the first stack along a second direction perpendicular to the first direction The bottom of each word line pick-up region 103 can be aligned with a corresponding second dielectric layer 505, as opposed to first dielectric layer 503, and the corresponding second dielectric layer 505 can be partially replaced with interconnect line 206 to form the electrical connection between vertical contact 202 [Wang para 0071]
Tang discloses three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures
Wang discloses a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures.
Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Tang and Wang in the art of three-dimensional (3D) memory devices and operating the same, as one of ordinary skill in the art would have recognized that the results of the combination were predictable as the combined teachings and technologies were well known in the art. Wang improves Tang’s systems, methods and/or apparatus by adding a second stack of layers to the 3D structure which overcomes density issues in the formation of the structure.
Regarding claim 13 Tang and Wang teach claim 12 in addition Tang teaches comprising: forming a stack structure of the dielectric layers and the isolating layers alternating with each other along the first direction The hard mask 1378 can include a thickness large enough to protect the underlying alternating dielectric stack 1164 during the subsequent etching processes [Tang para 0113]; and etching a first portion of the stack structure to form a first initial staircase in a first part of the first portion and a second initial staircase in a second part of the first portion. The hard mask 1378 can include a thickness large enough to protect the underlying alternating dielectric stack 1164 during the subsequent etching processes [Tang para 0113] During the etching process, a portion of each staircase step 1476 with exposed surface can be removed [Tang para 0117]
Regarding claim 14 Tang and Wang teach claim 13 in addition Tang teaches comprising: partially replacing the dielectric layers with the conductive layers in the stack structure to form the first stack. After replacing the sacrificial layers with conductive layers, staircase structures 210-L and 210-R can be formed in the staircase region 210. [Tang para 0129]
Regarding claim 15 Tang and Wang teach claim 12 in addition Tang teaches comprising: forming a TSG cut structure extending through the TSG layers and at least one of the conductive layers along the first direction, wherein the TSG cut structure is configured to separate the TSG layers into a plurality of TSG electrodes. top select gates (TSGs) 334 over the stack of control gates 333. The stack of TSG 334, control gates 333 and LSG 332 is also referred to as “gate electrodes. [Tang para 0063] the 3D memory structure 400 can also include one or more top select gate (TSG) cut 220. The TSG cut 220 can separate TSG 334 into two or more sub-TSGs 334-1, 334-2, 334-3, [Tang para 0084]
Regarding claim 16 Tang and Wang teach claim 15 in addition Tang teaches wherein the TSG cut structure comprises a first end and a second end opposite to the first end along the second direction, and wherein the second end of the TSG cut structure is between the first staircase structure and the second staircase structure. the TSG cut 220 can separate TSG 334 into two or more sub-TSGs 334-1, 334-2, 334-3 [Tang para 0084 and see Fig. 17B] and wherein the second end of the TSG cut structure is between the first staircase structure and the second staircase structure. FIG. 17B illustrates a top-down view of the structure 1700. The cross-sectional view in FIG. 17A is in x-direction along line BB′. The contact structures 214 can be similar to the contact structures discussed previously with reference to FIGS. 2-4. [Tang para 0135 and see Fig. 17B]
Regarding claim 17 Tang and Wang teach claim 12 in addition Tang teaches comprising: forming a slit structure extending along the second direction each tier are separated by slit structures 216-1 and 216-2 through the film stack 335. [Tang para 0063]; and forming a slit cut extending through the slit structure along the first direction, wherein the slit cut separates the slit structure into a first segment and a second segment, a plurality of slit structures 216, extending in WL direction across the channel structure region 211 and the staircase region 210, can divide a memory block into multiple memory fingers 218 [Tang para 0061] and the slit cut is between the first staircase structure and the second stack. the staircase bridge 450 can be disposed anywhere in the staircase region 210. FIGS. 4 and 5 illustrates the configuration where the staircase bridge 450 is disposed on the sub-block 448-1 close to the slit structure 216 [Tang para 0086]
Regarding claim 18 Tang and Wang teach claim 15 in addition Tang teaches comprising: forming a plurality of TSG contact structures, one of the TSG contact structures being in contact with a corresponding one of the TSG electrodes at a corresponding one of the one or more first stairs. top select gates (TSGs) 334 over the stack of control gates 333. The stack of TSG 334, control gates 333 and LSG 332 is also referred to as “gate electrodes. … The memory array structure 300 also includes a plurality of metal interconnect lines 343 connected with the gate electrodes through a plurality of contact structures 214. [Tang para 0063]
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al., US Patent Application (20220085181), hereinafter “Yin” and Wang et al., US Patent Application (20240107760), hereinafter “Wang”.
Rgearding claim 19 Yin teaches a semiconductor device, comprising: a first stack of conductive layers and isolating layers alternating with each other along a first direction, the device 100 can include a stack of alternating insulating layers 111 and word line layers 112 (also referred to as gate layers) that are arranged in a vertical direction over a substrate 101. [Yin para 0021] wherein a first portion of the first stack comprises one or more top select gate (TSG) layers of the conductive layers; in FIG. 1A, the device can include a TSG trench 120 having a first TSG cut structure 121 in the core region 170 and a second TSG cut structure 122 in the staircase region 130. The first TSG cut structure 121 is made of a same dielectric material (e.g., silicon oxide) as the second TSG cut structure 122 in the FIG. 1A example. The first TSG cut structure 121 and the second TSG cut structure 122 are formed in separate steps and can therefore have different depths as illustrated. … the first TSG cut structure 121 can be made of a different dielectric material from the second TSG cut structure 122. [Yin para 0024] and a TSG cut structure a first TSG cut structure 121 in the core region 170 and a second TSG cut structure 122 [Yin para 0024 and see Fig. 1A]] extending through the first portion of the first stack and at least one of the conductive layers in a second portion of the first stack that is adjacent to the first portion of the first stack along the first direction, one or more of the TSG trenches 120 that extend along the x direction. Again, the TSG trench 120 includes the first TSG cut structure 121 in the core region 112 [Yin para 0027] the TSG cut structure being configured to separate the one or more TSG layers into a plurality of TSG electrodes, the core region 170 includes a plurality of channel structures (not shown, but will be explained in detail in FIG. 1B) that extend through the stack in the vertical direction. [Yin para 0022] wherein a conductive layer of the at least one of the conductive layers comprises a first part and a second part, the word line layers 112 can include one or more top select gates (TSGs) and may further include one or more dummy TSGs below the TSGs. [Yin para 0022] and wherein the TSG cut structure is configured to separate the first part of the conductive layer into a plurality of layer portions, and the second part connects ends of the plurality of layer portions. the stair step 110 is demonstrated to have four pairs of alternating insulating layers 111 and word line layers 112 in FIG. 1A. The staircase region 130 can also have an insulating layer 131 over the stair steps 110. [Yin para 0023 and see Fig. 1A]
Yin does not explicitly teach but Wang teaches the second part is between the first part and the second stack, a second stack of dielectric layers a second stack structure including interleaved second dielectric layers and the first dielectric layers, [Wang para 0017] first dielectric layers 503 of the conductive stack structure of stack structure [Wang para 0066 and see Fig. 5] and isolating layers alternating with each other along the first direction the dielectric stack structure and are surrounded by first and second dielectric layers 503 and 505 in dielectric portion [Wang para 0066], wherein the second stack is connected to the first stack along a second direction perpendicular to the first direction; The bottom of each word line pick-up region 103 can be aligned with a corresponding second dielectric layer 505, as opposed to first dielectric layer 503, and the corresponding second dielectric layer 505 can be partially replaced with interconnect line 206 to form the electrical connection between vertical contact 202 [Wang para 0071]
Yin discloses a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.
Wang discloses a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures.
Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Yin and Wang in the art of stacked semiconductor devices and operating the same, as one of ordinary skill in the art would have recognized that the results of the combination were predictable as the combined teachings and technologies were well known in the art. Wang improves Yin’s systems, methods and/or apparatus by adding a second stack of layers to the 3D structure which overcomes density issues in the formation of the structure.
Regarding claim 20 Yin and Wang teaches claim 19 in addition Yin teaches wherein the first portion comprises a first staircase structure having one or more first stairs corresponding to the one or more TSG layers, and the semiconductor device one or more of the TSG trenches 120 that extend along the x direction. Again, the TSG trench 120 includes the first TSG cut structure 121 in the core region 170 and the second TSG cut structure 122 in the staircase region 130. [Yin para 0027] further comprises TSG contact structures, one of the TSG contact structures being in contact with a corresponding one of the plurality of TSG electrodes at a corresponding one of the first stairs. the device 100 can have a plurality of contact structures (not shown) that extend through the insulating layer 131 in the staircase region 130. The plurality of contact structures can be electrically connected to respective word line layers 112. [Yin para 0031]
Conclusion
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/ROBERT J MICHAUD/Examiner, Art Unit 2622
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