Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 8, and 11-19 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Vimercarti (US 20140328134 A1).
Regarding claim 1: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), comprising: an array of memory cells (memory array 630, FIG. 4); a differential amplifier (110, FIG.3) having a first input (111, FIG.3) and a second input (112), FIG.3 wherein the first input is connectable to a target voltage (VREF, FIG.3); and a capacitor (129, FIG.3) coupled to the second input (112, FIG.3) and configured to store an offset (VOFFSET, par. 16 and 21) of the differential amplifier; wherein the differential amplifier is configured to, during an operation to sense a data state (pars. 15-20) of a memory cell of the array, reconnect the first input and the second input (first and second inputs 111/112 connected during operation during phase 1 of operation, par 14-18).
Regarding claim 2: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the first input is connected to the target voltage prior to the operation (T0, switch between VREF and first input 111 is closed, par. 14, FIG. 1B and 3).
Regarding claim 3: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein reconnecting the first input and the second input inputs the target voltage to the first input (during T1, after connecting inputs 111/112 the first input 111 is left at VREF, par. 18).
Regarding claim 4: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the first input is connectable to the target voltage via a switch (via switch of switch box 120, FIG. 3).
Regarding claim 5: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein: an output (OUT_DIFF from differential amplifier 110) of the differential amplifier is coupled to a data line (global data line GBL 20, FIG. 3) of the array; and the memory cell (10) is coupled to the data line (memory cell 10 connected to global data line GBL 20, FIG. 3).
Regarding claim 6: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein: the apparatus includes: an additional differential amplifier (310, FIG.3) having a first input (311, FIG.3) and a second input (312, FIG.3), wherein the first input of the additional differential amplifier is connectable to the target voltage (VREF, FIG.3); and an additional capacitor (312, FIG.3) coupled to the second input of the additional differential amplifier and configured to store an offset (VOFFSET, pars. 16-21) of the additional differential amplifier; and wherein the additional differential amplifier is configured to, during an operation to sense a data state (pars. 15-20) of an additional memory cell of the array, reconnect the first input and the second input of the additional differential amplifier (first and second inputs 311/312 connected during operation during phase 1 of operation, par 14-18).
Regarding claim 8: Vimercarti discloses a method for sensing a data state of a memory cell including a differential amplifier (100/300), comprising: connecting a first input (111, FIG.3) of a differential amplifier (110, FIG.3) to a target voltage (VREF, FIG.3); storing an offset of the differential amplifier (par. 16 and 21) in a capacitor (129, FIG.3) coupled to a second input (112, FIG.3) of the differential amplifier; and during an operation to sense a data state (pars. 15-20) of a memory cell of the memory: disconnecting the first input of the differential amplifier from the target voltage (after T1, switches disconnect VREF from first input 111, par. 18); and reconnecting the first input and the second input of the differential amplifier (first and second inputs 111/112 connected during operation during phase 1 ph1 of operation, par 14-18).
Regarding claim 11: Vimercarti discloses a method for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the method includes inputting the offset (VOFFSET) of the differential amplifier to the second input (driving inverting input 112 to voltage of (VREF + VOFFSET), par. 16-18) of the different amplifier during the operation.
Regarding claim 12: Vimercarti discloses a method for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the method includes: connecting the capacitor to an output of the differential amplifier prior to the operation (T0, switch between capacitor 129 and output OUT_DIFF is closed, par. 14, FIG. 1B and 3); and disconnecting the capacitor from the output of the differential amplifier during the operation (after T1, switch between capacitor 129 and output OUT_DIFF is opened, par. 14, FIG. 1B and 3).
Regarding claim 13: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), comprising: an array of memory cells (530, FIG. 4); a differential amplifier (110, FIG.3) having a first input (111, FIG.3), a second input (112, FIG.3), and an output (output of differential amplifier 110, FIG. 4), wherein the first input is connectable to a target voltage (VREF, FIG.3); a first capacitor (129, FIG.3) coupled to the second input and configured to store an offset (par. 16 and 21) of the differential amplifier; and a second capacitor (125, FIG. 3) connectable to the first input (connected to input 111, FIG. 3) and coupled to the output (coupled to output of differential amplifier 110 when switches are in place in operation, FIG. 3); wherein the differential amplifier is configured to, during an operation to sense a data state (pars. 15-20) of a memory cell of the array, reconnect the first input and the second input such that the target voltage is input to the first input (first and second inputs 311/312 connected during operation during phase 1 ph1 of operation, par 14-18) through the second capacitor.
Regarding claim 14: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the target volage (VREF) is input to the first input (during operation, the first input 111 is left at VREF, par. 18) without the offset of the differential amplifier during the operation.
Regarding claim 15: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the second capacitor is connected to the first input during the operation (during T1, capacitor 129 is coupled to first input 111 through switches 120A and 120C, FIG. 3).
Regarding claim 16: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the second capacitor is disconnected from the first input prior to the operation (T0, switch between capacitor 129 and first input 111 is open, par. 14, FIG. 1B and 3).
Regarding claim 17: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the second capacitor is connectable to the first input via a switch (switch box 120, FIG. 3).
Regarding claim 18: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein the first capacitor is connectable to the output of the differential amplifier (capacitor 129 connectable to output of differential amplifier 10 via switch 120D, FIG. 3).
Regarding claim 19: Vimercarti discloses an apparatus for sensing a data state of a memory cell including a differential amplifier (100/300), wherein a charge of the second capacitor during the operation indicates the data state of the memory cell (during operation, OUT_DIFF is connected to second capacitor 125, connected to a sense voltage IN_GBL to be checked to determine the data state of the memory cell, par. 19-20).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Vimercarti (US 20140328134 A1) in view of Komatsuzaki (US 6574135 B1).
Regarding claim 7: Vimercarti does not disclose an apparatus, wherein the memory cells of the array are ferroelectric random-access memory (FeRAM) cells.
Komatsuzaki does disclose an apparatus utilizing ferro-electric memory capable of sensing data states, wherein the memory cells of the array are ferroelectric random-access memory (FeRAM) cells (ferroelectric memory cells of array 610, FIG. 8A).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory array of Vimercarti with the FeRAM cells of Komatsuzaki to allow the system to utilize ferro electric memory cells for their array to track data states.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Vimercarti (US 20140328134 A1) in view of Rovere et al. (WO 2022038347 A1).
Regarding claim 9: Vimercarti does not disclose an apparatus, wherein reconnecting the first input and the second input of the differential amplifier comprises: switching the first input from a noninverting input to an inverting input; and switching the second input from an inverting input to a noninverting input.
Rovere does disclose a differential amplifier having a swapping the inputs of the differential transistor by altering the input voltage magnitudes between the inverting and noninverting inputs (par. 31-33).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Vimercarti with the configuration of Rovere to have the differential amplifier capable of acting between the two polarities for outputting the sensed data state.
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having reconnecting the first input and the second input of the differential amplifier comprises switching the connection of the gate of the first transistor and the gate of the second transistor from the drain of the third transistor to a drain of the fourth transistor as in claims 10 and 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827