DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the RCE and amendment filed on 7/30/2026.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/1/2026 has been entered.
Claims 1, 19, and 20 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 6-8, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely, Jr. et al. (US 2013/0339621) and Vaz et al. (US 2011/0246688).
With respect to claim 1, Steely teaches of a method of processing a memory access transaction through an execution path of a processing system, wherein a memory attribute structure comprises one or more memory address entries (fig. 5; paragraph 39-40; where the ARP references a mapping of virtual address ranges to priorities to determine the priority of an incoming request for data),
each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels (fig. 5; paragraph 39-40; where as shown in figure 5 each address range has a start and end address and maps to a priority of X, Y, or Z),
the method comprising: determining a memory address of the memory access transaction (fig. 3, 5; paragraph 33; where a request for data contains a virtual address);
using the memory attribute structure to determine a priority level mapped to the determined memory address (fig. 3, 5; paragraph 33, 39-40; where the ARP determines the priority of the data/request using the mapping of virtual addresses to priorities); and
processing the memory access transaction based on the determined priority level (paragraph 15, 34-37; where the cache memory is managed based on the priorities assigned to the requests),
wherein processing the memory access transaction comprises: associating the memory access transaction with the determined priority level (fig. 3, 5; paragraph 33, 39-40; where the ARP determines the priority of the data/request using the mapping of virtual addresses to priorities).
Steely fails to explicitly teach of prioritizing acceptance of the memory access transaction into buffer space over the acceptance of one or more respective memory access transactions associated with respective priority levels having a lower priority than the determined priority level into buffer space, and wherein said prioritizing comprises prioritizing storing of the memory transaction into buffer space.
However, Vaz teaches of prioritizing acceptance of the memory access transaction into buffer space over the acceptance of one or more respective memory access transactions associated with respective priority levels having a lower priority than the determined priority level into buffer space, and wherein said prioritizing comprises prioritizing storing of the memory transaction into buffer space (fig. 2; paragraph 29-30; where the higher priority request is chosen and stored into the queue over the lower priority request).
Steely and Vaz are analogous art because they are from the same field of endeavor, as they are directed to prioritizing data/transactions.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely and Vaz before the time of the effective filing of the claimed invention to incorporate the arbitration of transactions into the memory controller queue in Steely as taught in Vaz. Their motivation would have been to maximize performance of higher priority agents (Vaz, paragraph 29).
With respect to claim 19, the combination of Steely and Vaz teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Steely also teaches of a non-transitory computer-readable storage medium having computer code stored thereon, which when run on a processing system, causes the processing system to perform the method of claim 1 (paragraph 62; where the operations are carried out by a processing element executing firmware stored in memory).
With respect to claim 20, the combination of Steely and VaZ teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Steely also teaches of a processing system for processing a memory access transaction through an execution path of the processing system, wherein the processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels (fig. 3, 5; paragraph 39-40; where a TLB stores the mappings that are used by the ARP).
With respect to claim 6, the combination of Steely and Vaz teaches of wherein said prioritising comprises prioritising processing of the memory access transaction by one or more components of the execution path (Steely paragraph 15, 34-37; Vaz, paragraph 29-30; where the cache memory is managed based on the priorities assigned to the requests such that a cache line with a high priority may replace any cache line that is normal priority and the request queue prioritizes higher priority transactions for storage over lower priority transactions).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 7, Steely teaches of wherein said associating comprises associating a flag with the memory access transaction, wherein the flag indicates the priority level (paragraph 15, 44; where the priority value of data is represented in each cache line by two bits).
With respect to claim 8, the combination of Steely and Vaz teaches of wherein the memory access transaction is not prioritised over one or more respective memory access transactions associated with respective priority levels having a higher priority than the determined priority level (Steely paragraph 36-37; Vaz, paragraph 29-30; where the retrieved cache line is normal priority and may not replace any cache line in the cache which contains high priority data. The transaction with a higher priority is prioritized over a lower priority transaction).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
Claim(s) 3-4 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely, Vaz, and Bell, Jr. et al. (US 2017/0308468).
With respect to claim 3, the combination of Steely and Vaz fails to explicitly teach of wherein said prioritising comprises prioritising selection of the memory access transaction for transmission over one or more interfaces of the processing system.
However, Bell teaches of wherein said prioritising comprises prioritising selection of the memory access transaction for transmission over one or more interfaces of the processing system (fig. 3, 5; paragraph 42-44; where the low and high priority cache line requests from the bus command and reorder queues are prioritized in their fetching from the memory).
Steely, Vaz, and Bell are analogous art because they are from the same field of endeavor, as they are directed to prioritizing data/transactions.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely, Vaz, and Bell before the time of the effective filing of the claimed invention to incorporate the bus command and reorder queues of Bell into the combination of Steely and Vaz. Their motivation would have been to more quickly retrieve high priority data from the memory.
With respect to claim 4, Bell teaches of wherein the one or more interfaces comprise a CPU-to- interconnect interface and/or an interconnect-to-slave interface (fig. 3, 5; paragraph 42-44; bus command queue is coupled to the chip bus which connects the memory controller with the processor core and the reorder queue is coupled to the memory via the memory bus).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claim 9, Bell teaches of wherein the processing system comprises one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level, and wherein processing the memory access transaction comprises allocating the memory access transaction to one of said reserved buffer spaces (fig. 3, 5; abstract; paragraph 42-44; where the reorder queue and bus command queue contain a high priority and low priority queues where high and low priority requests are placed).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claim 10, Bell teaches of wherein multiple reserved buffer spaces are reserved for memory access transactions associated with the determined priority level (fig. 3, 5; abstract; paragraph 42-44; where there are multiple high and low priority queues).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claim 11, Bell teaches of wherein the processing system comprises a plurality of buffer spaces, and wherein the method comprises marking one or more of the plurality of buffers spaces as the one or more reserved buffer spaces (fig. 3, 5; abstract; paragraph 42-44; where a high priority request is placed in the high priority queue).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claim 12, the combination of Steely, Vaz, and Bell teaches of wherein the memory attribute structure comprises, for each respective priority level of the set of priority levels, a respective indication of one or more respective reserved buffer spaces (Steely, fig. 5; paragraph 39-40; Bell, fig. 3, 5; abstract; paragraph 42-44; wherein the combination the map maps the virtual address ranges to a priority level, in the combination with Bell’s priority level queues, the priority level in the map is an indication that corresponds to the buffer of that priority level).
The reasons for obviousness are the same as indicated above with respect to claim 3.
Claim(s) 13-14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely, Vaz, and Talwar et al. (US 2018/0004456).
With respect to claim 13, the combination of Steely and Vaz fails to explicitly teach of wherein the memory attribute structure is configurable by a user of the processing system.
However, Talwar teaches of dynamic memory access priority level adjustments with any number of priority states that is configurable by an administrator (paragraph 49; where the dynamic memory access priority level adjustments with any number of priority states that is configurable by an administrator).
The combination of Steely, Vaz, and Talwar teaches of wherein the memory attribute structure is configurable by a user of the processing system (Steely, fig. 5; paragraph 39-40; Talwar, paragraph 49; where in the combination, the mapping structure of Steely is configured as the priority levels are configured by the admin).
Steely, Vaz, and Talwar are analogous art because they are from the same field of endeavor, as they are directed to prioritizing data/transactions.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely, Vaz, and Talwar before the time of the effective filing of the claimed invention to incorporate an administrator being able to configure the priority levels in Steely as taught in Talwar. Their motivation would have been to increase the flexibility of the system.
With respect to claim 14, Steely teaches of wherein the respective priority level mapped to the respective memory address range is configurable (paragraph 39; where any number of priorities can be defined in the mapping).
With respect to claim 16, Steely teaches of wherein a number of priority levels of the set of priority levels is configurable (paragraph 39; where any number of priorities can be defined in the mapping).
With respect to claim 17, the combination of Steely, Vaz, and Talwar teaches of wherein the memory attribute structure is configurable by a user of the processing system (Steely, fig. 5; paragraph 39-40; Talwar, paragraph 49; where in the combination, the mapping structure of Steely is configured as the priority levels are configured by the admin), and
wherein a respective number of reserved buffer spaces per respective priority level is configurable (Steely, paragraph 39, 42, 44-45; where the cache lines already stored in the cache have priority levels that can be changed).
The reasons for obviousness are the same as indicated above with respect to claim 13.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely, Vaz, and Bell as applied to claim 9 above and in further view of Talwar.
With respect to claim 15, the combination of Steely, Vaz, and Bell fails to explicitly teach of wherein the memory attribute structure is configurable by a user of the processing system, and wherein the one or more reserved buffer spaces reserved for use by memory access transactions associated with a respective priority level is configurable.
However, the combination of Steely, Vaz, and Talwar teaches of wherein the memory attribute structure is configurable by a user of the processing system (Steely, fig. 5; paragraph 39-40; Talwar, paragraph 49; where in the combination, the mapping structure of Steely is configured as the priority levels are configured by the admin), and
wherein the one or more reserved buffer spaces reserved for use by memory access transactions associated with a respective priority level is configurable (Talwar, paragraph 49; Bell, abstract, paragraph 42-44; where in the combination the queues are also configurable).
Steely, Vaz, Bell, and Talwar are analogous art because they are from the same field of endeavor, as they are directed to prioritizing data/transactions.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely, Vaz, Bell, and Talwar before the time of the effective filing of the claimed invention to incorporate an administrator being able to configure the priority levels and queues in the combination of Steely, Vaz, and Bell as taught in Talwar. Their motivation would have been to increase the flexibility of the system.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely, Vaz, and Talwar as applied to claim 13 above and in further view of Weaver et al. (US 2020/0285408).
With respect to claim 18, Steely, Vaz, and Talwar fails to explicitly teach of wherein the memory attribute structure is configurable at build time of the processing system.
However, Weaver teaches of wherein the memory attribute structure is configurable at build time of the processing system (paragraph 82; where memory attributes including priority information is configured by the programmer. Since the configuration is done when programmed, this is done when the is built).
Steely, Vaz, Talwar, and Weaver are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely, Vaz, Talwar, and Weaver before the time of the effective filing of the claimed invention to incorporate configuring some of the attributes of the memory when it is programmed in the combination of Steely, Vaz, and Talwar as taught in Weaver. Their motivation would have been to increase the flexibility of the system.
Response to Arguments
Applicant's arguments with respect to independent claims 1 and 19-20 have been considered but are moot because of the new reference(s) being applied, in light of the amendment, to the particular limitations the arguments are referencing. Thereby the arguments no longer apply to the rejection.
Applicant's arguments filed 7/1/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., that the prioritization occurs upstream of the cache memory) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138
Prosecution Insights