DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendment filed on 12/29/2025.
The title and claims 1, 3, 6-8, and 19-20 have been amended.
Claims 2 and 5 have been cancelled.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-8, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1), (a)(2) as being anticipated by Steely, Jr. et al. (US 2013/0339621).
With respect to claim 1, Steely teaches of a method of processing a memory access transaction through an execution path of a processing system, wherein a memory attribute structure comprises one or more memory address entries (fig. 5; paragraph 39-40; where the ARP references a mapping of virtual address ranges to priorities to determine the priority of an incoming request for data),
each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels (fig. 5; paragraph 39-40; where as shown in figure 5 each address range has a start and end address and maps to a priority of X, Y, or Z),
the method comprising: determining a memory address of the memory access transaction (fig. 3, 5; paragraph 33; where a request for data contains a virtual address);
using the memory attribute structure to determine a priority level mapped to the determined memory address (fig. 3, 5; paragraph 33, 39-40; where the ARP determines the priority of the data/request using the mapping of virtual addresses to priorities); and
processing the memory access transaction based on the determined priority level (paragraph 15, 34-37; where the cache memory is managed based on the priorities assigned to the requests),
wherein processing the memory access transaction comprises: associating the memory access transaction with the determined priority level (fig. 3, 5; paragraph 33, 39-40; where the ARP determines the priority of the data/request using the mapping of virtual addresses to priorities); and
prioritising the memory access transaction over one or more respective memory access transactions associated with respective priority levels having a lower priority than the determined priority level (paragraph 15, 34-37; where it is determined whether the retrieved data should be stored in the cache based on the priority assigned to the retrieved data’s associated request. Retrieved data with a request that is a high priority may replace any cache line that is normal priority and any high priority cache line when all the cache lines in the cache contain high priority data. Retrieved data with a request that is a normal priority may replace any cache line with normal priority. When retrieved data with a normal priority request occurs when all the cache lines contain high priority data, the normal priority data request can’t replace any of the cache lines, while retrieved data with a high priority request replaces a high priority cache line and is stored in the cache), and
wherein said prioritising comprises prioritising acceptance of the memory transaction into buffer space (paragraph 15, 34-37; where the cache memory is managed based on the priorities assigned to the requests such that a cache line with a high priority may replace any cache line that is normal priority).
With respect to claim 19, Steely teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Steely also teaches of a non-transitory computer-readable storage medium having computer code stored thereon, which when run on a processing system, causes the processing system to perform the method of claim 1 (paragraph 62; where the operations are carried out by a processing element executing firmware stored in memory).
With respect to claim 20, Steely teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Steely also teaches of a processing system for processing a memory access transaction through an execution path of the processing system, wherein the processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels (fig. 3, 5; paragraph 39-40; where a TLB stores the mappings that are used by the ARP).
With respect to claim 6, Steely teaches of wherein said prioritising comprises prioritising processing of the memory access transaction by one or more components of the execution path (paragraph 15, 34-37; where the cache memory is managed based on the priorities assigned to the requests such that a cache line with a high priority may replace any cache line that is normal priority).
With respect to claim 7, Steely teaches of wherein said associating comprises associating a flag with the memory access transaction, wherein the flag indicates the priority level (paragraph 15, 44; where the priority value of data is represented in each cache line by two bits).
With respect to claim 8, Steely teaches of wherein the memory access transaction is not prioritised over one or more respective memory access transactions associated with respective priority levels having a higher priority than the determined priority level (paragraph 36-37; where the retrieved cache line is normal priority and may not replace any cache line in the cache which contains high priority data).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely and Bell, Jr. et al. (US 2017/0308468).
With respect to claim 3, Steely fails to explicitly teach of wherein said prioritising comprises prioritising selection of the memory access transaction for transmission over one or more interfaces of the processing system.
However, Bell teaches of wherein said prioritising comprises prioritising selection of the memory access transaction for transmission over one or more interfaces of the processing system (fig. 3, 5; paragraph 42-44; where the low and high priority cache line requests from the bus command and reorder queues are prioritized in their fetching from the memory).
Steely and Bell are analogous art because they are from the same field of endeavor, as they are directed to prioritizing data/transactions.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely and Bell before the time of the effective filing of the claimed invention to incorporate the bus command and reorder queues of Bell into Steely. Their motivation would have been to more quickly retrieve high priority data from the memory.
With respect to claim 4, Bell teaches of wherein the one or more interfaces comprise a CPU-to- interconnect interface and/or an interconnect-to-slave interface (fig. 3, 5; paragraph 42-44; bus command queue is coupled to the chip bus which connects the memory controller with the processor core and the reorder queue is coupled to the memory via the memory bus).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claim 9, Bell teaches of wherein the processing system comprises one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level, and wherein processing the memory access transaction comprises allocating the memory access transaction to one of said reserved buffer spaces (fig. 3, 5; abstract; paragraph 42-44; where the reorder queue and bus command queue contain a high priority and low priority queues where high and low priority requests are placed).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claim 10, Bell teaches of wherein multiple reserved buffer spaces are reserved for memory access transactions associated with the determined priority level (fig. 3, 5; abstract; paragraph 42-44; where there are multiple high and low priority queues).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claim 11, Bell teaches of wherein the processing system comprises a plurality of buffer spaces, and wherein the method comprises marking one or more of the plurality of buffers spaces as the one or more reserved buffer spaces (fig. 3, 5; abstract; paragraph 42-44; where a high priority request is placed in the high priority queue).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claim 12, the combination of Steely and Bell teaches of wherein the memory attribute structure comprises, for each respective priority level of the set of priority levels, a respective indication of one or more respective reserved buffer spaces (Steely, fig. 5; paragraph 39-40; Bell, fig. 3, 5; abstract; paragraph 42-44; wherein the combination the map maps the virtual address ranges to a priority level, in the combination with Bell’s priority level queues, the priority level in the map is an indication that corresponds to the buffer of that priority level).
The reasons for obviousness are the same as indicated above with respect to claim 3.
Claim(s) 13-14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely and Talwar et al. (US 2018/0004456).
With respect to claim 13, Steely fails to explicitly teach of wherein the memory attribute structure is configurable by a user of the processing system.
However, Talwar teaches of dynamic memory access priority level adjustments with any number of priority states that is configurable by an administrator (paragraph 49; where the dynamic memory access priority level adjustments with any number of priority states that is configurable by an administrator).
The combination of Steely and Talwar teaches of wherein the memory attribute structure is configurable by a user of the processing system (Steely, fig. 5; paragraph 39-40; Talwar, paragraph 49; where in the combination, the mapping structure of Steely is configured as the priority levels are configured by the admin).
Steely and Talwar are analogous art because they are from the same field of endeavor, as they are directed to prioritizing data/transactions.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely and Talwar before the time of the effective filing of the claimed invention to incorporate an administrator being able to configure the priority levels in Steely as taught in Talwar. Their motivation would have been to increase the flexibility of the system.
With respect to claim 14, Steely teaches of wherein the respective priority level mapped to the respective memory address range is configurable (paragraph 39; where any number of priorities can be defined in the mapping).
With respect to claim 16, Steely teaches of wherein a number of priority levels of the set of priority levels is configurable (paragraph 39; where any number of priorities can be defined in the mapping).
With respect to claim 17, the combination of Steely and Talwar teaches of wherein the memory attribute structure is configurable by a user of the processing system (Steely, fig. 5; paragraph 39-40; Talwar, paragraph 49; where in the combination, the mapping structure of Steely is configured as the priority levels are configured by the admin), and
wherein a respective number of reserved buffer spaces per respective priority level is configurable (Steely, paragraph 39, 42, 44-45; where the cache lines already stored in the cache have priority levels that can be changed).
The reasons for obviousness are the same as indicated above with respect to claim 13.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely and Bell as applied to claim 9 above and in further view of Talwar.
With respect to claim 15, the combination of Steely and Bell fails to explicitly teach of wherein the memory attribute structure is configurable by a user of the processing system, and wherein the one or more reserved buffer spaces reserved for use by memory access transactions associated with a respective priority level is configurable.
However, the combination of Steely and Talwar teaches of wherein the memory attribute structure is configurable by a user of the processing system (Steely, fig. 5; paragraph 39-40; Talwar, paragraph 49; where in the combination, the mapping structure of Steely is configured as the priority levels are configured by the admin), and
wherein the one or more reserved buffer spaces reserved for use by memory access transactions associated with a respective priority level is configurable (Talwar, paragraph 49; Bell, abstract, paragraph 42-44; where in the combination the queues are also configurable).
Steely, Bell, and Talwar are analogous art because they are from the same field of endeavor, as they are directed to prioritizing data/transactions.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely, Bell, and Talwar before the time of the effective filing of the claimed invention to incorporate an administrator being able to configure the priority levels and queues in the combination of Steely and Bell as taught in Talwar. Their motivation would have been to increase the flexibility of the system.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely and Talwar as applied to claim 13 above and in further view of Weaver et al. (US 2020/0285408).
With respect to claim 18, Steely and Talwar fails to explicitly teach of wherein the memory attribute structure is configurable at build time of the processing system.
However, Weaver teaches of wherein the memory attribute structure is configurable at build time of the processing system (paragraph 82; where memory attributes including priority information is configured by the programmer. Since the configuration is done when programmed, this is done when the is built).
Steely, Talwar, and Weaver are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely, Talwar, and Weaver before the time of the effective filing of the claimed invention to incorporate configuring some of the attributes of the memory when it is programmed in the combination of Steely and Talwar as taught in Weaver. Their motivation would have been to increase the flexibility of the system.
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
Applicant argues with respect to independent claims 1, 19, and 20, that Steely does not disclose, “prioritising the memory access transaction over one or more respective memory access transactions associated with respective priority levels having a lower priority than the determined priority level, wherein said prioritising comprises prioritising acceptance of the memory transaction into buffer space,” as allegedly (1) Steely does not prioritize data requests into a buffer space, but prioritizes data into a cache, (2) Steely does not prioritize a high priority memory access transaction being accepted into buffer space over a lower priority memory access transaction. The examiner disagrees.
The applicant’s application does not provide a specific definition of the term “buffer.” A buffer is defined by The American Heritage Dictionary of the English Language as, “[a] device or area used to store data temporarily.” Cache memories are used in computer to temporarily store data. Furthermore, The American Heritage Dictionary of the English Language defines cache as, “[a] fast storage buffer in the central processing unit of a computer. Also called cache memory,” explicitly identifying cache memory as a buffer. Thus, the cache memory disclosed by Steely is a buffer.
In paragraph 33, Steely specifies that the address range priority assigner (ARP) assigns priorities to data requests based on the address range of the data the request is for. Paragraphs 14-15 of Steely also indicate that the data and the request for the data are both assigned a priority based on the address range that the requested data corresponds to. Therefore, Steely’s prioritization is prioritizing memory access transactions and not just the data that corresponds to the memory access transactions.
Paragraph 35-37 specify that Steely’s system determines whether the retrieved data should be stored in the cache based on the priority assigned to the retrieved data’s associated request. Retrieved data with a request that is a high priority may replace any cache line that is normal priority and any high priority cache line when all the cache lines in the cache contain high priority data (see paragraph 36). Retrieved data with a request that is a normal priority may replace any cache line with normal priority (see paragraph 37). Thus, when retrieved data with a normal priority request occurs and all the cache lines contain high priority data, the normal priority data request can’t replace any of the cache lines. A request for retrieved data with a high priority is able to replace a high priority cache line and be stored in the cache. This shows that the high priority memory access transaction is prioritized over the normal priority memory access transaction into the cache of Steely. Thus, Steely reads on the limitations at issue.
Applicant also argues that the double patenting rejection should be held in abeyance until the claims are indicated as allowable. The examiner disagrees.
As indicated by MPEP 804 (I)(B)(1), a response to a nonstatutory double patenting rejection must either show “that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s).” The present response does neither. Furthermore, MPEP 804 (I)(B)(1) explicitly states, “such a filing should not be held in abeyance.”
The examiner notes that the proper action is to hold the applicant’s response, non-responsive in this situation. While presently the provisional double patenting rejection has been withdrawn in view of the amendments made to the independent claims. The examiner would like to put the applicant on notice that should a future double patenting rejection be made in response to any future amendments, any response that does not respond properly to the nonstatutory double patenting rejection will be held as non-responsive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138