Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 16 December 2024.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: processing devices to perform operations in claim 1, support for which was taken as FIG 1: 115 and [0033] of the Specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4,5,11,1218 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4,5,11,12, 18 recite limitations that are broader than or otherwise repeat limitations recited in claims 1, 8, 15, specifically regarding “the first programming metadata comprises first voltage data and first time data for a first signal waveform corresponding to the first segment.” It is unclear how claims 4,5,11,12, 18 are further limiting because they specify the first programming metadata comprise timing data and/or voltage data.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-5, 8-12, 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang (US PG PUB No. 20240094912) in view of Thiruvengadam (US PG PUB No. 20190139618)
As per claim [1,8,15], a memory sub-system (see Liang FIG 1: 100) comprising:
a memory device (see Liang FIG 1: 120); and
one or more processing devices operatively coupled to the memory device (see Liang FIG 1: 110), the one or more processing devices configured to perform operations comprising:
determining that a first segment of the memory device and a second segment of the memory device are to be programmed (see Liang FIG 4: 402 and [0032]);
[Each selected block is taken as a determined segment of the memory device as recited in the claims.]
determining first programming metadata for the first segment (see Liang [0032]: “the microprocessor 112 can directly refer to the block erase count data table to obtain the erase count of the selected block, and determine the appropriate encoding/decoding setting”);
[The erase count of a selected block is taken as a metadata of a segment as recited in the claims.]
determining second programming metadata for the second segment (see Liang [0032]: “the microprocessor 112 can directly refer to the block erase count data table to obtain the erase count of the selected block, and determine the appropriate encoding/decoding setting”); and
responsive to determining the first programming metadata and the second programming metadata, causing the first segment and the second segment to be programmed based on the first programming metadata and the second programming metadata (see Liang [0032]: “ In response to the erase count of the selected block being smaller than “100”, the microprocessor 112 determines to utilize the first set of encoding/decoding settings to set the encoder 132. In response to the erase count of the selected block being between “100”-“200”, the microprocessor 112 determines to utilize the second set of encoding/decoding settings to set the encoder 132.”).
However, Liang does not expressly disclose but in the same field of endeavor Thiruvengadam discloses
wherein the first programming metadata comprises first voltage data and first time data for a first signal waveform corresponding to the first segment (see Thiruvengadam FIG 3: 370,375 and [0025]).
It would have been before the effective filing date of the invention to modify Liang to utilize metadata comprising voltage and timing metadata as taught by Thiruvengadam.
The suggestion/motivation for doing so would have been for the benefit of a more fine grain programming method (see Thiruvengadam [0027]).
Therefore it would have been obvious before the effective filling date of the invention to modify Liang to use programming metadata as taught by Thiruvengadam for the benefit of a more fine grain programming method to arrive at the invention as specified in the claims.
As per claim [2,9,16], the memory sub-system of claim 1, the operations further comprising:
determining that a third segment of the memory device is to be programmed with the first segment and the second segment; determining third programming metadata for the third segment; and causing the third segment to be programmed with the first segment and the segment based on the third programming metadata (see Liang [0032]: “In response to the erase count of the selected block being smaller than “100”, the microprocessor 112 determines to utilize the first set of encoding/decoding settings to set the encoder 132. In response to the erase count of the selected block being between “100”-“200”, the microprocessor 112 determines to utilize the second set of encoding/decoding settings to set the encoder 132.”).
As per claim [3,10,17] the memory sub-system of claim 1,
wherein determining the first programming metadata for the first segment is based on one or more characteristics of the first segment of the memory device (see Liang [0032]: “erase count”)
As per claim [4,11], the memory sub-system of claim 1,
wherein the first programming metadata comprises timing metadata for a programming operation to be performed on the first segment (see Thiruvengadam FIG 3: 375 and [0025])
As per claim [5,12], the memory sub-system of claim 1,
wherein the first programming metadata comprises voltage biasing metadata for a programming operation to be performed on the first segment (see Thiruvengadam FIG 3: 370 and [0025])
As per claim 18, the computer-readable non-transitory storage medium of claim 17,
wherein the first programming metadata comprises timing metadata for a programming operation to be performed on the first segment, and wherein the first programming metadata comprises voltage biasing metadata for a programming operation to be performed on the first segment (see Thiruvengadam FIG 3: 370,375 and [0025])
Claim 6-7, 13-14, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang (US PG PUB No. 20240094912) in view of Barrell (US PG PUB No. 20150046605 )
As per claim [6,13,19], the memory sub-system of claim 1, wherein determining that the first segment and the second segment are to be programmed comprises:
identifying a set of programming operations from a plurality of memory access operations, the set of programming operations comprising a first programming operation for the first segment and a second programming operation for the second segment (see Liang FIG 4: 406 and [0033]);
[The encoding operations for the respective write operations are taken as part of the programming operations as recited in the claims.]
However, Liang does not expressly disclose but in the same field of endeavor Barrel disclose
sorting the first programming operation into a first position of a programming queue; and sorting the second programming operation into a second position of the programming queue, wherein the second position is subsequent to the first position (see Barrell [0010]: “Yet another advantage of the present invention is it sorts all storage device commands in an LBA-sorted list as well as a time-sorted list. The two lists provide increased efficiency when processing sequential commands (LBA-sorted list), while making sure that unrelated commands (time-sorted list) do not get stalled.”)
It would have been obvious before the effective filing date of the invention to modify Liang to further queue and sort commands as taught by Barrell.
The suggestion/motivation for doing so would have been for the benefit of improved scheduling (See Barrell [0010]).
Therefore it would have been obvious before the effective filing date of the invention to modify Liang to queue and sort commands as taught by Barrell for the benefit of improved scheduling to arrive at the invention as specified in the claims.
As per claim [7,14, 20], the memory sub-system of claim 6, the operations further comprising:
determining programming metadata for the set of programming operations (see e.g., Liang FIG 8: 802), the programming metadata comprising the first programming metadata, the second programming metadata, and respective programming metadata for each segment corresponding to each programming operation of the set of programming operations (see Liang [0032]).
[Liang discloses the metadata to select the programming scheme comprises type of data and characteristics of the block.]
RESPONSE TO ARGUMENTS
1st ARGUMENT:
Liang is directed to "accessing a flash memory module." (Liang, Abstract). The Office Action asserts that Liang teaches, "determining first programming metadata for the first segment," based on Liang's description, "the microprocessor 112 can directly refer to the block erase count data table to obtain the erase count of the selected block, and determine the appropriate encoding/decoding setting." (Office Action, pg. 4; Liang at [0032]). Applicant respectfully disagrees. Liang discloses that "the encoder 132 is configured with various encoding settings to generate error correction codes (ECCs) with different numbers of bits" and "[t]he decoder 134 may also be configured with various decoding settings to decode chunks with different numbers of bits, wherein each chunk includes a data and a corresponding ECC." (Id. at [0027]). Accordingly, Liang's "encoding/decoding settings" relate to ECC bit lengths, which are not the same as the "first programming metadata" recited in claim 1
Liang discloses generating “an encoded data with a suitable size by setting the encoder according to the type of data to be written and/or the erase count and type of the block that needs to be written (see Liang [0082]).” The programming metadata was taken as erase count not the encoding/decoding settings as argued.
2nd ARGUMENT:
Even assuming arguendo that Liang describes "determining first programming metadata for the first segment," Liang does not disclose the amended claim language "wherein the first programming metadata comprises first voltage data and first time data for a first signal waveform corresponding to the first segment" as recited in claim 1. Liang's "encoding/decoding settings" pertain to ECC bit lengths, which is different from at least "voltage data," "time data," and/or "a first signal waveform" recited in claim 1 as currently presented.
Examiner notes Thiruvengadam was further relied upon to teach the argued subject matter. Thiruvengadam discloses selecting trim settings according to a number of metadata including voltage and time data for a signal waveform as argued.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137