Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 10 April 2026.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: processing devices to perform operations in claim 1, support for which was taken as FIG 1: 115 and [0033] of the Specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-5, 8-12, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang (US PG PUB No. 20240094912) in view of Thiruvengadam (US PG PUB No. 20190139618)
As per claim [1,8,15], a memory sub-system (see Liang FIG 1: 100) comprising:
a memory device (see Liang FIG 1: 120); and
one or more processing devices operatively coupled to the memory device (see Liang FIG 1: 110), the one or more processing devices configured to perform operations comprising:
determining that a first segment of the memory device and a second segment of the memory device are to be programmed (see Liang FIG 4: 402 and [0032]);
[Each selected block is taken as a determined segment of the memory device as recited in the claims.]
determining first programming metadata for the first segment (see Liang [0032]: “the microprocessor 112 can directly refer to the block erase count data table to obtain the erase count of the selected block, and determine the appropriate encoding/decoding setting”);
[The erase count of a selected block is taken as a metadata of a segment as recited in the claims.]
determining second programming metadata for the second segment (see Liang [0032]: “the microprocessor 112 can directly refer to the block erase count data table to obtain the erase count of the selected block, and determine the appropriate encoding/decoding setting”); and
wherein the first programming metadata and the second programming metadata are determined during a single prologue operation before causing the first segment and the second segment to be programmed (see [0044]: “ In other embodiments, the microprocessor 112 can directly refer to the highest erase count among the erase counts recorded in the above-mentioned block erase count data table (i.e. the highest erase count among the erase counts of all blocks) for determining the encoding/decoding setting required to be subsequently utilized by the encoder 132 or the decoder 134.”); and
responsive to determining the first programming metadata and the second programming metadata, causing the first segment and the second segment to be programmed based on the first programming metadata and the second programming metadata (see Liang [0032]: “ In response to the erase count of the selected block being smaller than “100”, the microprocessor 112 determines to utilize the first set of encoding/decoding settings to set the encoder 132. In response to the erase count of the selected block being between “100”-“200”, the microprocessor 112 determines to utilize the second set of encoding/decoding settings to set the encoder 132.”).
However, Liang does not expressly disclose but in the same field of endeavor Thiruvengadam discloses
wherein the first programming metadata comprises first voltage data and first time data for a first signal waveform corresponding to the first segment (see Thiruvengadam FIG 3: 370,375 and [0025]).
It would have been before the effective filing date of the invention to modify Liang to utilize metadata comprising voltage and timing metadata as taught by Thiruvengadam.
The suggestion/motivation for doing so would have been for the benefit of a more fine grain programming method (see Thiruvengadam [0027]).
Therefore it would have been obvious before the effective filling date of the invention to modify Liang to use programming metadata as taught by Thiruvengadam for the benefit of a more fine grain programming method to arrive at the invention as specified in the claims.
As per claim [2,9,16], the memory sub-system of claim 1, wherein the one or or more processing devices are configured to perform operations further comprising:
determining that a third segment of the memory device is to be programmed with the first segment and the second segment; determining third programming metadata for the third segment; and causing the third segment to be programmed with the first segment and the segment based on the third programming metadata (see Liang [0032]: “In response to the erase count of the selected block being smaller than “100”, the microprocessor 112 determines to utilize the first set of encoding/decoding settings to set the encoder 132. In response to the erase count of the selected block being between “100”-“200”, the microprocessor 112 determines to utilize the second set of encoding/decoding settings to set the encoder 132.”).
As per claim [3,10,17] the memory sub-system of claim 1,
wherein determining the first programming metadata for the first segment is based on one or more characteristics of the first segment of the memory device (see Liang [0032]: “erase count”)
Claim 6-7, 13-14, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang (US PG PUB No. 20240094912) in view of Barrell (US PG PUB No. 20150046605 )
As per claim [6,13,19], the memory sub-system of claim 1, wherein determining that the first segment and the second segment are to be programmed comprises:
identifying a set of programming operations from a plurality of memory access operations, the set of programming operations comprising a first programming operation for the first segment and a second programming operation for the second segment (see Liang FIG 4: 406 and [0033]);
[The encoding operations for the respective write operations are taken as part of the programming operations as recited in the claims.]
However, Liang does not expressly disclose but in the same field of endeavor Barrel disclose
sorting the first programming operation into a first position of a programming queue; and sorting the second programming operation into a second position of the programming queue, wherein the second position is subsequent to the first position (see Barrell [0010]: “Yet another advantage of the present invention is it sorts all storage device commands in an LBA-sorted list as well as a time-sorted list. The two lists provide increased efficiency when processing sequential commands (LBA-sorted list), while making sure that unrelated commands (time-sorted list) do not get stalled.”)
It would have been obvious before the effective filing date of the invention to modify Liang to further queue and sort commands as taught by Barrell.
The suggestion/motivation for doing so would have been for the benefit of improved scheduling (See Barrell [0010]).
Therefore it would have been obvious before the effective filing date of the invention to modify Liang to queue and sort commands as taught by Barrell for the benefit of improved scheduling to arrive at the invention as specified in the claims.
As per claim [7,14, 20], the memory sub-system of claim 6, the operations further comprising:
determining programming metadata for the set of programming operations (see e.g., Liang FIG 8: 802), the programming metadata comprising the first programming metadata, the second programming metadata, and respective programming metadata for each segment corresponding to each programming operation of the set of programming operations (see Liang [0032]).
[Liang discloses the metadata to select the programming scheme comprises type of data and characteristics of the block.]
RESPONSE TO ARGUMENTS
1st ARGUMENT:
The specification provides ample structural context for the term "processing
device." For example, the specification discloses that "processing device 602 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like" and "can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor" or "special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like." (As-Filed Specification, Paragraph [0075].) The specification further identifies the processing device as structural hardware, stating that "the memory sub-system controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119." (As-Filed Specification, Paragraph [0033].) Additionally, the specification states that "the memory sub-system controller 115 can include hardware such as one or more integrated circuits and/or discrete components" and "can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor." (As-Filed Specification, Paragraph [0032].)
Examiner notes the claims do not specify the structures Applicant is pointing to, and instead suggest the processing device, because it encompasses a host of structures, does not inherently suggest a specific structure pointed in the Specification.
2nd ARGUMENT:
Liang describes a sequential, per-block process for writing data to a flash memory
module. As shown in FIG. 4 and described in paragraph [0032], the microprocessor 112
"selects a block from the flash memory module 120 for data writing" (Step 402), then
"determines an encoding/decoding setting according to the erase count of the selected
block" (Step 404), then the encoder "encodes the data according to the
encoding/decoding setting" (Step 406), and finally "writes the encoded data into the block" (Step 408). (Liang, FIG. 4 and Paragraphs [0031]-[0034].) The flowchart in FIG. 4 of Liang shows a sequential process where each block is fully processed (i.e., metadata determined, data encoded, and data written) before moving to the next block. In Liang, the encoding/decoding setting for a block is determined immediately before that block is programmed, not in advance together with settings for other blocks. Thus, Liang does not teach or suggest determining programming metadata for multiple segments together in a single prologue operation before programming any of the segments.
Examiner maintains the claim language is sufficiently broad to encompass Liang determining the highest erase count among the blocks to determine programming settings as pointed out in the rejection above. Liang discloses embodiments including determining erase counts of the blocks to determine programming settings, where the determination is taken as a single prologue operation as recited in the claims (see Liang [0044]).
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
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