Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-7, 9, and 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130215689 A1 (Joshi, et al., hereinafter Joshi).
Regarding claim 1, Joshi teaches a clocking scheme (Joshi, “clocking functions…clocking signals”; [0007-0010]: “associated logic circuitry…”) for driving a multi-port memory device, (Joshi, [0004]: “two-port functionality”; [0033]: “an example of an 8T memory bit cell 90 having a structure that can achieve high performance and two-port functionality,”) the clocking scheme including at least two separate clocking phases (Joshi, [0011]: “positive phase of clock”…[0038]: “low phase of clock”, etc.) and comprising: providing a clock configured to control timing of operations within the multi-port memory device; (“a method for operating an 8T memory bit cell is described. The method includes applying a clock signal…”) activating a first signal line in a first clock phase, (Joshi, [0011]: “in the positive phase of clock…read word lines can be activated based on the value of the read address (AW/EZR) and write address (AR/EZR) signals on respective read address line 40 and write address line 52. Thus, the bit cell in the array having both word lines on can be selectively addressed, allowing data from the data latch/decoding logic circuit 56 to be written into the bit cell 10, and allowing the internal value of the bit cell 10 to be read through the single ended sensing mechanism provided by the NMOS transistors 34 and 36 in the transistor stack 37…”) and activating a write word line in a second clock phase, (Joshi, [0038]: “the low phase of the memory clock may be extended for a relatively long duration, which may unintentionally enable the write word line”) the first clock phase and the second clock phase being different clock phases of the at least two separate clocking phases of the clocking scheme. (“positive phase of clock…negative phase of clock”)
Joshi does not appear to explicitly set forth the first signal line being a write bit line or an OR write word line.
However, although Joshi does not appear to specifically set forth the language that “the first signal line” may be “a write bit line” or “an OR write word line”, one of ordinary skill in the art would recognize that this arrangement of “write bit lines” and/or “write word lines” are merely arrangements of the signals as taught in Joshi and would not achieve any new unexpected, functional, or synergistic result, and are merely a modification of the teachings of Joshi. Re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a "convenient and obvious location of elements in space" that does not yield an unexpected, functional, or synergistic result is unpatentable as obvious. In particular, as relating to claim 1, the use of different obvious modifications of “the signal line” would not achieve any new result and would be obvious to one of ordinary skill in the art.
Regarding claim 2, Joshi teaches the clocking scheme of claim 1, wherein the clock is configured to generate a clock signal having a rising edge in the first clock phase and a falling edge in the second clock phase. (Joshi teaches wherein the clock signals are generated by a rising and falling edge, for example Joshi, [0039]: “The rising clock edge 126 triggers the write word line signal 128 to go low 130, initiating a write precharge operation. The rising clock edge 126 also triggers the read word line signal 132 to go high 134, initiating a read operation.”)
Regarding claim 4, Joshi teaches the clocking scheme of claim 1, wherein the first signal line is a write bit line and wherein the write bit line is triggered to rise at a rising edge of a clock signal and the write word line is triggered to rise at a falling edge of the clock signal. (Joshi teaches that a rising and/or falling edge (i.e., a clock signal) is received and triggers: Joshi, [0021]: “Each 8T memory bit cell has a read word line and a write word line. A read address latch/clock circuit for receives the clock signal and the read address signals to initiate a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals to initiate a write operation during a second clock cycle state. In one embodiment, an inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. In one embodiment, the read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state.”)
Regarding claim 5, Joshi teaches the clocking scheme of claim 4, wherein a write word line rise triggers a writing of data from the write bit line to a storage node of a bit cell. (Joshi, [0010]: “Data to be written to the memory cell 10 is applied from data input line 54 via data latch/decoding logic circuit 56 to the write bit lines 16 and 18. The output to be read from the circuit is sensed on line 38 by sensing logic and output driver circuitry 58, and delivered on output line 60.”)
Regarding claim 6, Joshi teaches the clocking scheme of claim 5, wherein the writing of data is a state of a 0 or 1. (Joshi teaches writing of data to a bit cell, which is a memory cell that stores one bit of binary data, 0 or 1)
Regarding claim 7, Joshi teaches the clocking scheme of claim 4, wherein a falling time of the write word line is determined by self-timed path delay. (Joshi, [0020]: “In one embodiment, the write address flip-flop/clock circuit includes a loose self-timer, wherein if the low clock cycle state continues beyond a first predetermined time, the loose self-timer ends the write operation at a second predetermined time less than the first predetermined time.”)
Regarding claim 9, Joshi teaches the clocking scheme of claim 1, but does not appear to specifically set forth wherein the first signal line is an OR write word line and wherein the OR write word line is triggered to rise at a rising edge of a clock signal and the write word line is triggered to rise at a falling edge of the clock signal.
However, although Joshi does not appear to specifically set forth that “the first signal line is an OR write word line and wherein the OR write word line is triggered to rise at a rising edge of a clock signal and the write word line is triggered to rise at a falling edge of the clock signal.”, one of ordinary skill in the art would recognize that this arrangement of “OR write word line” and/or “write word lines” to serve as signal lines and to be triggered by rising and/or falling edges of a clock signal are merely arrangements of signal lines and would not achieve any new unexpected, functional, or synergistic result, and are merely a modification of the teachings of Joshi. Re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a
"convenient and obvious location of elements in space" that does not yield an
unexpected, functional, or synergistic result is unpatentable as obvious. In particular, as relating to claim 9, the use of different obvious modifications of “the first signal line” and whether it is triggered by a rising edge or a falling edge would not achieve any new result and would be obvious to one of ordinary skill in the art.
Regarding claim 12, Joshi teaches the clocking scheme of claim 1, wherein the clock is coupled to both a read clock and a write clock. Although Joshi does not explicitly set forth the terms a “read clock” and a “write clock”, one of ordinary skill in the art would conclude that a clock coupled to a read clock and a write clock would comprise a clock that can be used to synchronize both read and write operations. Further, the instant specification provides that “In techniques, the clocking scheme may comprise a clock coupled to a both a read clock and a write clock, wherein for a read operation the read clock rises to trigger a read word line rise followed by the read clock falling to trigger the read word line fall.”, which is performed by the “clocks” of Joshi. (Joshi, [0021]: “A read address latch/clock circuit for receives the clock signal and the read address signals to initiate a read operation during a first clock cycle state.”…Joshi, [0012]: “In this scenario, parallel read and write operations can be concurrently performed successfully.”, etc.)
Regarding claim 13, Joshi teaches the clocking scheme of claim 12, and although not set forth explicitly by Joshi, one of ordinary skill in the art would recognize that wherein for a read operation the read clock rises to trigger a read word line rise followed by the read clock falling to trigger a read word line fall as standard and well-known clock functionality.
Regarding claim 14, Joshi teaches the clocking scheme of claim 12, and although not set forth explicitly by Joshi, one of ordinary skill in the art would recognize wherein for a write operation the write clock rises to trigger a write bit line rise or fall as standard and well-known clock functionality.
Regarding claim 15, Joshi teaches the clocking scheme of claim 14, and although not explicitly set forth by Joshi, one of ordinary skill in the art would recognize that wherein for a write operation the write clock falls to trigger write word line rise at a falling edge of the write clock as standard and well-known clock functionality.
Regarding claim 16, Joshi teaches a logic circuit (Joshi, “logic circuitry”…[0010}: logic circuit 56) for driving signals (Joshi, “clocking functions…clocking signals”; [0007-0010]: “associated logic circuitry…”) to a multi-port memory device, (Joshi, [0004]: “two-port functionality”; [0033]: “an example of an 8T memory bit cell 90 having a structure that can achieve high performance and two-port functionality,”) the logic circuit comprising: a first signal line, (Joshi, [0011]: “in the positive phase of clock…read word lines can be activated) a write word line; (Joshi, “write word line”) circuitry for a clocking scheme including a clock configured to control timing of operations within the multi-port memory device, (“a method for operating an 8T memory bit cell is described. The method includes applying a clock signal…”) wherein the clocking scheme includes at least two separate clocking phases; (“positive phase of clock…negative phase of clock”)
and wherein the clocking scheme activates the first signal line in a first clock phase (Joshi, [0011]: “in the positive phase of clock…read word lines can be activated based on the value of the read address (AW/EZR) and write address (AR/EZR) signals on respective read address line 40 and write address line 52. Thus, the bit cell in the array having both word lines on can be selectively addressed, allowing data from the data latch/decoding logic circuit 56 to be written into the bit cell 10, and allowing the internal value of the bit cell 10 to be read through the single ended sensing mechanism provided by the NMOS transistors 34 and 36 in the transistor stack 37…”) and activates the write word line in a second clock phase, (Joshi, [0038]: “the low phase of the memory clock may be extended for a relatively long duration, which may unintentionally enable the write word line”) the first clock phase and the second clock phase being different clock phases of the at least two separate clocking phases of the clocking scheme. (“positive phase of clock…negative phase of clock”)
Joshi does not appear to explicitly teach the first signal line being a write bit line or an OR write word line.
However, although Joshi does not appear to specifically teach that “the first signal line” may be “a write bit line” or “an OR write word line”, one of ordinary skill in the art would recognize that this arrangement of “write bit lines” and/or “write word lines” are merely arrangements of the signals as taught in Joshi and would not achieve any new unexpected, functional, or synergistic result, and are merely a modification of the teachings of Joshi. Re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a "convenient and obvious location of elements in space" that does not yield an
unexpected, functional, or synergistic result is unpatentable as obvious. In particular, as relating to claim 16, the use of different obvious modifications of “the signal line” would not achieve any new result and would be obvious to one of ordinary skill in the art.
Regarding claim 17, Joshi teaches the logic circuit as claimed in claim 16, but does not appear to explicitly set forth wherein the first signal line is an OR write word line configured as an OR of write word lines of respective different write ports.
However, although Joshi does not appear to explicitly set forth the language “wherein the first signal line is an OR write word line configured as an OR of write word lines of respective different write ports”, one of ordinary skill in the art would recognize that configuring signal lines and write word lines with “OR” logic circuitry for respective write ports would not achieve any new unexpected, functional, or synergistic result, and are merely a modification of the teachings of Joshi. Re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a "convenient and obvious location of elements in space" that does not yield and unexpected, functional, or synergistic result is unpatentable as obvious. In particular, as relating to claim 17, indicating a reference to “OR” logic circuitry would be merely an obvious modification to one of ordinary skill in the art.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130215689 A1 (Joshi, et al., hereinafter Joshi) in view of 20210407575 A1 (Brox, et al., hereinafter Brox).
Regarding claim 20, Joshi teaches a first signal line, (Joshi, [0011]: “in the positive phase of clock…read word lines can be activated based on the value of the read address (AW/EZR) and write address (AR/EZR) signals on respective read address line 40 and write address line 52.) a write word line; (Joshi, “write word line”) circuitry for a clocking scheme including a clock configured to control timing of operations within the multi-port memory device, (“a method for operating an 8T memory bit cell is described. The method includes applying a clock signal…”) wherein the clocking scheme includes at least two separate clocking phases; (“positive phase of clock…negative phase of clock”) and wherein the clocking scheme activates the first signal line in a first clock phase (Joshi, [0011]: “in the positive phase of clock…read word lines can be activated based on the value of the read address (AW/EZR) and write address (AR/EZR) signals on respective read address line 40 and write address line 52. Thus, the bit cell in the array having both word lines on can be selectively addressed, allowing data from the data latch/decoding logic circuit 56 to be written into the bit cell 10, and allowing the internal value of the bit cell 10 to be read through the single ended sensing mechanism provided by the NMOS transistors 34 and 36 in the transistor stack 37…”) and activates the write word line in a second clock phase, (Joshi, [0038]: “the low phase of the memory clock may be extended for a relatively long duration, which may unintentionally enable the write word line”) the first clock phase and the second clock phase being different clock phases of the at least two separate clocking phases of the clocking scheme. (“positive phase of clock…negative phase of clock”)
Joshi does not appear to explicitly teach the first signal line being a write bit line or an OR write word line.
However, although Joshi does not appear to specifically teach that “the first signal line” may be “a write bit line” or “an OR write word line”, one of ordinary skill in the art would recognize that this arrangement of “write bit lines” and/or “write word lines” are merely arrangements of the signals as taught in Joshi and would not achieve any new unexpected, functional, or synergistic result, and are merely a modification of the teachings of Joshi. Re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a "convenient and obvious location of elements in space" that does not yield an
unexpected, functional, or synergistic result is unpatentable as obvious. In particular, as relating to claim 20, the use of different obvious modifications of “the signal line” would not achieve any new result and would be obvious to one of ordinary skill in the art.
Joshi does not appear to explicitly teach wherein such a method is implemented on a non-transitory computer-readable medium to store computer-readable code for fabrication of such a logic circuit.
Brox cures the deficiencies of Joshi. Brox teaches wherein a clocking scheme for a register file is implemented on a non-transitory computer-readable medium to store computer-readable code for fabrication of such a logic circuit. (Brox, [0113]: “In some examples, an apparatus as described herein may perform a method or methods, such as the method 1000. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for…”)
Both Joshi and Brox are directed to clocking schemes for a memory system. It
would have been obvious to one of ordinary skill in the art to combine the clocking
scheme for a multi-port memory file of Joshi with the teachings of Brox in order to
implement the invention of Joshi with a non-transitory computer readable medium
storing code. One of ordinary skill in the art would have motivation to combine in order
to implement the invention and clocking schemes of Joshi and fabricate the circuit with
a non-transitory computer readable medium storing code in order to increase
functionality of the invention.
Allowable Subject Matter
Claims 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 18, the prior art of record does not appear to teach a logic circuit for driving signals to a multi-port memory device, the logic circuit comprising: a first signal line, the first signal line being a write bit line or an OR write word line; a write word line; circuitry for a clocking scheme including a clock configured to control timing of operations within the multi-port memory device, wherein the clocking scheme includes at least two separate clocking phases; and wherein the clocking scheme activates the first signal line in a first clock phase and activates the write word line in a second clock phase, the first clock phase and the second clock phase being different clock phases of the at least two separate clocking phases of the clocking scheme, wherein the first signal line is an OR write word line configured as an OR of the write word lines of all respective different write ports, wherein the OR of the write word line is generated by an input array of write ports each coupled to an input of a first NOR gate, wherein at least three first NOR gates are coupled to an input of a second NOR gate coupled to an input of a NAND gate and wherein the NAND gate is coupled to an input of a third NOR gate connected to an input of a NOT gate.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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