Final Rejection
This office action is in response to Applicants Amendment filed 2/4/26.
Response to Applicants arguments
The Applicants arguments have been fully considered, however are not found persuasive.
Response to Applicants remarks
With respect to claims 1, 8, 15 on 6-8, the applicant argues the Northcott does not teach programming any of the user data in the main area to the spare area of the page. Rather, the Northcott reference appears to teach that the spare area of the page is provided to store ECC parity data. (Column 2, lines 6-7; Figure 1A).
The Examiner respectfully disagrees with the statement, and points to (column 2, lines 4-10), wherein as stated, a region is provided for user data or information data in the main area of the flash, and a spare area is provided to provide room for ECC parity and other data, hence the other data can be for example user data, which can easily be programmed. Also, as stated the user data 103, metadata 104, such as data integrity feature (DIF) and Journaling Engine management data, and the manufacturer's recommended amount of ECC parity data 105 may be stored interleaved within the page as illustrated in FIG. 1B, which can also be programmed. Thus, it would be obvious for the Northcott reference to teach wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data (column 2, lines 4-10).
35 U.S.C 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14-16 and 18-20 are rejected under 35 U.S.C 103 as being unpatentable over McGlaughlin et al. (US Pub. No. – 2019/0303283) in view of Northcott (US Patent No. – 9,183,085).
With respect to claim 1, the McGlaughlin et al. reference teaches a memory having a plurality of groups of memory cells ([0025] – memory cells); and all other ones of the plurality of groups of memory cells have data stored therein ([0045] - stored threshold voltages, stored resistance values, and/or other characteristics of the constituent memory cells corresponding to neighboring PMUAs ); and a controller coupled to the memory and having circuitry configured to: determine one of the plurality of groups of memory cells that has data stored therein is a bad group of memory cells ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes); recover the data stored in the bad group of memory cells ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes); and retire the bad group of memory cells. ([0034] - quarantine scrubber can be responsible for evaluating PMUAs in the quarantine list to determine whether to retire the PMUAs (e.g., from further use).
The McGlaughlin et al. reference does not teach wherein: one of the plurality of groups of memory cells does not have data stored therein; program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein, wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data.
The Northcott reference teaches wherein: one of the plurality of groups of memory cells does not have data stored therein (see fig. 1A, 102) and (column 2, lines 4-10); program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein (see fig. 1A, 102) and (column 2, lines 4-10), wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data (column 2, lines 4-10).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references McGlaughlin et al. and Northcott to incorporate wherein: one of the plurality of groups of memory cells does not have data stored therein; program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein, wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the McGlaughlin et al. and Northcott references for reduced uncorrectable errors (column 2, lines 16-21 - Northcott ).
With respect to claim 2, all of the limitations of claim 1 have been addressed.
The McGlaughlin et al. reference does not teach wherein the one of the plurality of groups of memory cells that does not have data stored therein is addressable.
The Northcott reference teaches wherein the one of the plurality of groups of memory cells that does not have data stored therein is addressable (see fig. 1A, 102) and (column 2, lines 4-10).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references McGlaughlin et al. and Northcott to incorporate wherein the one of the plurality of groups of memory cells that does not have data stored therein is addressable into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the McGlaughlin et al. and Northcott references for reduced uncorrectable errors (column 2, lines 16-21 - Northcott ).
With respect to claim 3, the McGlaughlin et al. reference teaches wherein the circuitry is configured to map a logical address associated with the bad group of memory cells to a physical address associated with the one of the plurality of groups of memory cells to which the recovered data was programmed ([0035] - can be initialized for direct mapping (e.g., LMUA =PMUA) and can be updated for indirect mapping as wear leveling “swaps” are performed).
With respect to claim 4, the McGlaughlin et al. reference teaches wherein the circuitry is configured to determine the bad group of memory cells during a scrub operation performed on the memory ([0034] - quarantine scrubber can be responsible for evaluating PMUAs in the quarantine list to determine whether to retire the PMUAs (e.g., from further use).
With respect to claim 5, the McGlaughlin et al. reference teaches wherein the memory cells of the plurality of groups are ferroelectric memory cells ([0002 - 0003] – can be different types of memory).
With respect to claim 6, the McGlaughlin et al. reference teaches wherein the groups of memory cells are pages of memory cells ([0030] - For example, the MU size can be a multiple of a physical page size of the memory, a multiple of a codeword size associated with the memory).
With respect to claim 7, the McGlaughlin et al. reference teaches wherein the pages of memory cells are physical pages of memory cells ([0030] - For example, the MU size can be a multiple of a physical page size of the memory, a multiple of a codeword size associated with the memory).
With respect to claim 8, the McGlaughlin et al. reference teaches determining, by a controller coupled to a memory, one of the plurality of groups of memory cells of the memory is a bad group of memory cells ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes); recovering, by the controller, data stored in the bad group of memory cells ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes); retiring, by the controller, the bad group of memory cells ([0034] - quarantine scrubber can be responsible for evaluating PMUAs in the quarantine list to determine whether to retire the PMUAs (e.g., from further use); and mapping, by the controller, a logical address associated with the bad group of memory cells to a physical address associated with the one of the plurality of groups of memory cells to which the recovered data was programmed ([0035] - can be initialized for direct mapping (e.g., LMUA =PMUA) and can be updated for indirect mapping as wear leveling “swaps” are performed).
The McGlaughlin et al. reference does not teach programming, by the controller, the recovered data to another one of the plurality of groups of memory cells that does not have data stored therein, wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data.
The Northcott reference teaches teach programming, by the controller, the recovered data to another one of the plurality of groups of memory cells that does not have data stored therein (see fig. 1A, 102) and (column 2, lines 4-10), wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data (column 2, lines 4-10).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references McGlaughlin et al. and Northcott to incorporate programming, by the controller, the recovered data to another one of the plurality of groups of memory cells that does not have data stored therein, wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data therein into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the McGlaughlin et al. and Northcott references for reduced uncorrectable errors (column 2, lines 16-21 - Northcott ).
With respect to claim 9, the McGlaughlin et al. reference wherein the method includes recovering the data stored in the bad group of memory cells by performing an error correction operation on the data stored in the bad group of memory cells ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes) and ([0027] - the memory management component includes a wear leveling component, a neighbor disturb mitigation component, and an error detection/correction component (e.g., an error correction code (ECC) engine).
With respect to claim 10, the McGlaughlin et al. reference wherein the method includes copying data stored in one of the plurality of groups of memory cells to another one of the plurality of groups of memory cells that has data stored therein ([0018] - writes resulting in a swap operation between “hot” and “cold” managed units) and ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes).
With respect to claim 11, the McGlaughlin et al. reference wherein the method includes erasing the one of the plurality of groups of memory cells from which the data was copied ([0023] - controller can communicate with the memory devices to control data read, write, and erase operations, among other operations).
With respect to claim 12, the McGlaughlin et al. reference teaches wherein the method includes disabling on-die wear leveling operations in the memory ([0024] - the controller can be responsible for, among other operations, memory management operations such as wear leveling operations, error detection and/or correction operations, disturb mitigation operations, encryption operations, caching operations, and address translation operations, among various other operations associated with the memory devices).
With respect to claim 14, all of the limitations of claim 8 have been addressed.
The McGlaughlin et al. reference does not wherein retiring the bad group of memory cells comprises storing no data in the bad group of memory cells.
The Northcott reference teaches wherein retiring the bad group of memory cells comprises storing no data in the bad group of memory cells (see fig. 1A, 102) and (column 2, lines 4-10).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references McGlaughlin et al. and Northcott to incorporate wherein retiring the bad group of memory cells comprises storing no data in the bad group of memory cells into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the McGlaughlin et al. and Northcott references for reduced uncorrectable errors (column 2, lines 16-21 - Northcott ).
With respect to claim 15, the McGlaughlin et al. reference teaches a host ([0018]- host); and a memory device, wherein the memory device includes: a memory having a plurality of groups of memory cells ([0025] – memory cells); all other ones of the plurality of groups of memory cells have data stored therein ([0045] - stored threshold voltages, stored resistance values, and/or other characteristics of the constituent memory cells corresponding to neighboring PMUAs ); and the memory device has a different respective physical address associated with each respective one of the plurality of groups of memory cells ([0027] - the data structures 114 can include a logical to physical (L2P) address mapping data structure (e.g., table) for mapping logical managed unit (MUA) addresses to physical managed units (PMUs) stored in memory 110, a physical managed unit address (PMUA) table, a disturb list, a hot list, a cold list, and a quarantine list) and ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes); and a controller coupled to the memory and having circuitry configured to: determine one of the plurality of groups of memory cells that has data stored therein is a bad group of memory cells ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes); recover the data stored in the bad group of memory cells ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes); and map a logical address of the host associated with the bad group of memory cells to the physical address associated with the one of the plurality of groups of memory cells to which the recovered data was programmed ([0053] - swap operation can include swapping the data stored at the respective PMUAs such that, subsequent to the swap, the data stored initially at a first of the PMUAs is stored at the second of the PMUAs and the data stored initially at the second of the PMUAs is stored at the first of the PMUAs) and ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes).
The McGlaughlin et al. reference does not teach wherein: one of the plurality of groups of memory cells does not have data stored therein; program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein, wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data.
The Northcott reference teaches wherein: one of the plurality of groups of memory cells does not have data stored therein (see fig. 1A, 102) and (column 2, lines 4-10) ; program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein (see fig. 1A, 102) and (column 2, lines 4-10), wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data (column 2, lines 4-10).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references McGlaughlin et al. and Northcott to incorporate wherein: one of the plurality of groups of memory cells does not have data stored therein; program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein, wherein the recovered data programmed to the one of the plurality of groups of memory cells that does not have data stored therein comprises user data into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the McGlaughlin et al. and Northcott references for reduced uncorrectable errors (column 2, lines 16-21 - Northcott ).
With respect to claim 16, the McGlaughlin et al. reference wherein the circuitry is configured to retire the bad group of memory cells ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes).
With respect to claim 18, the McGlaughlin et al. reference teaches wherein the host has a different respective logical address associated with all but one of the plurality of groups of memory cells that have data stored therein ([0035] - replace bad PMUs on the memory and/or for wear leveling purposes).
With respect to claim 19, all of the limitations of claim 15 have been addressed.
The McGlaughlin et al. reference does not teach wherein the host does not have a logical address associated with the one of the plurality of groups of memory cells that does not have data stored therein.
The Northcott reference teaches wherein the host does not have a logical address associated with the one of the plurality of groups of memory cells that does not have data stored therein (see fig. 1A, 102) and (column 2, lines 4-10).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references McGlaughlin et al. and Northcott to incorporate wherein the host does not have a logical address associated with the one of the plurality of groups of memory cells that does not have data stored therein into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the McGlaughlin et al. and Northcott references for reduced uncorrectable errors (column 2, lines 16-21 - Northcott ).
With respect to claim 20, the McGlaughlin et al. reference wherein the bad group of
memory cells is a group of memory cells that is not reliable for storing or retrieving data ([0034 - 0035] - quarantine scrubber can be responsible for evaluating PMUAs in the quarantine list to determine whether to retire the PMUAs (e.g., from further use)) .
Claim 13 is rejected under 35 U.S.C 103 as being unpatentable over McGlaughlin et al. (US Pub. No. – 2019/0303283), Northcott (US Patent No. – 9,183,085) in view of Lin et al. (US Pub. No. – 2009/0204824).
With respect to claim 13, all of the limitations of claim 8 have been addressed.
The McGlaughlin et al. reference does not teach wherein the method includes disabling random data scrambling operations in the memory..
The Lin et al. reference teaches wherein the method includes disabling random data scrambling operations in the memory. ([0102] – data scrambling can be disabled).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references McGlaughlin et al. and Lin et al. to incorporate wherein the method includes disabling random data scrambling operations in the memory. into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the McGlaughlin et al. and Lin et al. references for reduced power consumption ([0123] - Lin et al.).
Claim 17 is rejected under 35 U.S.C 103 as being unpatentable over McGlaughlin et al. (US Pub. No. – 2019/0303283), Northcott (US Patent No. – 9,183,085) in view of Vigilante (US Pub. No. – 2021/0065838).
With respect to claim 17, all of the limitations of claim 15 have been addressed.
The McGlaughlin et al. reference does not teach wherein the physical address associated with each respective one of the plurality of groups of memory cells corresponds to a different pin of the memory.
The Vigilante reference teaches wherein the physical address associated with each respective one of the plurality of groups of memory cells corresponds to a different pin of the memory ([0075] – first and second pins).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references McGlaughlin et al. and Vigilante to incorporate wherein the physical address associated with each respective one of the plurality of groups of memory cells corresponds to a different pin of the memory into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the McGlaughlin et al. and Vigilante references for improved testing ([0009] - Vigilante).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729. The examiner can normally be reached on Mon-Fri from 8:30 A.M. to 5:30 P.M.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady, can be reached on 571-272-3819.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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EA
5/31/26
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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