DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendment filed on 12/29/2025.
The title and claims 1, 5-7, and 9-10 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 5-7 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely, Jr. et al. (US 2013/0339621) and Bell, Jr. et al. (US 2017/0308468).
With respect to claim 1, Steely teaches of a method of configuring a memory attribute structure for use when processing memory access transactions through an execution path of a processing system, comprising: configuring one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels (fig. 5; paragraphs 39-40; where the mapping maps multiple address ranges to priorities. As this mapping is used, it must have been configured to map the address ranges to the priorities),
wherein a central processing unit is configured to use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction (fig. 1, 3, 5; paragraph 22, 33, 39-40, 62; where the ARP of the processor determines the priority of the data/request using the mapping of virtual addresses to priorities), and
process the respective memory access transactions based on the respective priority levels (paragraph 15, 34-37; where the cache memory is managed based on the priorities assigned to the requests).
Steely fails to explicitly teach of associating, for each respective priority level, one or more respective reserved buffer spaces reserved for use by memory access transactions associated with the respective priority level.
However, Bell teaches of associating, for each respective priority level, one or more respective reserved buffer spaces reserved for use by memory access transactions associated with the respective priority level (fig. 3, 5; abstract; paragraph 42-44; where the reorder queue and bus command queue contain high priority and low priority queues where requests are placed in the queue for their priority level).
Steely and Bell are analogous art because they are from the same field of endeavor, as they are directed to prioritizing data/transactions.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely and Bell before the time of the effective filing of the claimed invention to incorporate the bus command and reorder queues of Bell into Steely. Their motivation would have been to more quickly retrieve high priority data from the memory.
With respect to claim 9, the combination of Steely and Bell teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Steely also teaches of a non-transitory computer-readable storage medium having stored thereon computer readable code that, when run on a processing system, causes the processing system to perform the method of claim 1 (paragraph 62; where the operations are carried out by a processing element executing firmware stored in memory).
With respect to claim 10, the combination of Steely and Bell teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Steely also teaches of a processing system for processing a memory access transaction through an execution path of the processing system, wherein the processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels (fig. 3, 5; paragraph 39-40; where a TLB stores the mappings that are used by the ARP).
With respect to claim 2, Steely teaches of configuring a respective upper and/or respective lower address of at least one of the one or more respective memory address ranges (fig. 5; paragraph 39-40; as each memory address range contains a start and end address, it’s start and end addresses must have been set).
With respect to claim 3, Steely teaches of configuring a number of priority levels of the set of priority levels (fig. 5; paragraph 39-40; as each memory address range is mapped to a priority level and there can be any number of priority levels, the number of priority levels must have been set).
With respect to claim 5, the combination of Steely and Bell teaches of wherein the memory attribute structure comprises, for each respective priority level of the set of priority levels, a respective indication of one or more respective reserved buffer spaces (Steely, fig. 5; paragraph 39-40; Bell, fig. 3, 5; abstract; paragraph 42-44; wherein the combination the map maps the virtual address ranges to a priority level, in the combination with Bell’s priority level queues, the priority level in the map is an indication that corresponds to the buffer of that priority level).
The reasons for obviousness are the same as indicated above with respect to claim 4.
With respect to claim 6, the combination of Steely and Bell teaches of configuring a number of reserved buffer spaces for each respective priority level (Bell, fig. 3, 5; abstract; paragraph 42-44; where as there are multiple queues for each priority level, the number of them must have been set).
The reasons for obviousness are the same as indicated above with respect to claim 4.
With respect to claim 7, the combination of Steely and Bell teaches of configuring a total number of reserved buffer spaces reserved for memory access transactions associated with any of the set of priority levels (Bell, fig. 3, 5; abstract; paragraph 42-44; where as there are multiple queues for each priority level, the number of all of the queues must have been established).
The reasons for obviousness are the same as indicated above with respect to claim 4.
With respect to claim 11, Bell teaches of wherein the processing system comprises one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level (fig. 3, 5; abstract; paragraph 42-44; where the reorder queue and bus command queue contain high priority and low priority queues where requests are placed in the queue for their priority level), and
wherein processing the respective memory access transactions comprises allocating the respective memory access transactions to one of said reserved buffer spaces (fig. 3, 5; abstract; paragraph 42-44; where the requests are placed in the queue for their priority level).
The reasons for obviousness are the same as indicated above with respect to claim 4.
With respect to claim 12, Steely teaches of wherein the processing system is embodied in hardware on an integrated circuit (fig. 1; paragraph 16-18; where the processor is an integrated circuit).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Steely, Bell, as applied to claim 1 and in further view of Weaver et al. (US 2020/0285408).
With respect to claim 8, Steely and Bell fails to explicitly teach of configuring the memory attribute structure at build time of the processing system.
However, Weaver teaches of configuring the memory attribute structure at build time of the processing system (paragraph 82; where memory attributes including priority information is configured by the programmer. Since the configuration is done when programmed, this is done when the is built).
Steely, Bell, and Weaver are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Steely, Bell, and Weaver before the time of the effective filing of the claimed invention to incorporate configuring some of the attributes of the memory when it is programmed in the combination of Steely and Bell as taught in Weaver. Their motivation would have been to increase the flexibility of the system.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5-6 and 8-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9, 12-13, 16-20 of copending Application No. 18/791,035 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of 18/791,035 anticipate and include the limitations of the rejected claims of 18/791,162. See the chart below for a mapping of the rejected claims.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Application 18/791,162
Application 18/791,035
Claim 1: A method of configuring a memory attribute structure for use when processing memory access transactions through an execution path of a processing system, comprising: configuring one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, and
Claim 1: A method of processing a memory access transaction through an execution path of a processing system, wherein a memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels,
associating, for each respective priority level, one or more respective reserved buffer spaces reserved for use by memory access transactions associated with the respective priority level,
Claim 9: wherein the processing system comprises one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level, and wherein processing the memory access transaction comprises allocating the memory access transaction to one of said reserved buffer spaces.
wherein a central processing unit is configured to use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction, and
Claim 1: the method comprising: determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; and
process the respective memory access transactions based on the respective priority levels.
processing the memory access transaction based on the determined priority level.
wherein processing the memory access transaction comprises: associating the memory access transaction with the determined priority level; and prioritising the memory access transaction over one or more respective memory access transactions associated with respective priority levels having a lower priority than the determined priority level, and wherein said prioritising comprises prioritising acceptance of the memory transaction into buffer space
Claim 2
Claim 13
Claim 3
Claim 16
Claim 5
Claim 12
Claim 6
Claim 17
Claim 8
Claim 18
Claim 9: A non-transitory computer-readable storage medium having stored thereon computer readable code that, when run on a processing system, causes the processing system to configure a memory attribute structure for use when processing memory access transactions through an execution path of the processing system,
Claim 19 & 1: A non-transitory computer-readable storage medium having computer code stored thereon, which when run on a processing system, causes the processing system to process a memory access transaction through an execution path of the processing system,
wherein the configuring comprises: configuring one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels,
wherein a memory attribute structure comprises one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, and
associating, for each respective priority level, one or more respective reserved buffer spaces reserved for use by memory access transactions associated with the respective priority level
Claim 9: wherein the processing system comprises one or more buffer spaces reserved for use by memory access transactions associated with a predetermined priority level, and wherein processing the memory access transaction comprises allocating the memory access transaction to one of said reserved buffer spaces.
wherein a central processing unit is configured to use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction, and
Claim 19 & 1: wherein said processing a memory access transaction comprises: determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; and
process the respective memory access transactions based on the respective priority levels.
processing the memory access transaction based on the determined priority level.
Claim 10: A processing system for processing a memory access transaction through an execution path of the processing system, wherein the processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries,
Claim 20 &1: A processing system for processing a memory access transaction through an execution path of the processing system, wherein the processing system has stored, in memory, a memory attribute structure comprising one or more memory address entries,
each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, the processing system being configured to: configure one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels; use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction; and
each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels, the processing system being configured to: determine a memory address of the memory access transaction;
associate, for each respective priority level, one or more respective reserved buffer spaces reserved for use by memory access transactions associated with the respective priority level;
Claim 19 & 1: wherein said processing a memory access transaction comprises: determining a memory address of the memory access transaction; using the memory attribute structure to determine a priority level mapped to the determined memory address; and
use the memory attribute structure to determine a priority level mapped to the determined memory address; and
Claim 20 &1: use the memory attribute structure to determine a priority level mapped to the determined memory address; and
process the memory access transaction based on the determined priority level.
process the memory access transaction based on the determined priority level.
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
Applicant argues with respect to independent claims 1, 9, and 10, that the combination of Steely and Bell does not teach of (1) associating, for each respective priority level, one or more respective reserved buffer spaces reserved for use by memory access transactions associated with the respective priority level as allegedly Bell’s placement of requests into high or low priority queues is not the same as having specific dedicated spaces in a buffer for priority transactions, and (2) configuring one or more memory address entries, each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels; wherein a central processing unit is configured to use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction, and process the respective memory access transactions based on the respective priority levels as allegedly Steely’s address range priority assigner (ARP) is not a memory attribute structure because virtual addresses are not memory addresses. The examiner disagrees.
Regarding (1), Bell discloses in figures 3, 5, and 7, the abstract, and paragraphs 42-44 and 52 that the reorder queue and the bus command queue are made up of queues dedicated to high priority requests and queues dedicated to low priority requests. When a requested sector address corresponds to a high priority, the request is placed into a high priority reorder queue. When the requested sector isn’t a high priority, it is a low priority and is placed into a low priority reorder queue, see figure 7, paragraph 52. Thus, it is clear to one or ordinary skill in the art that Bell’s reorder queue and bus command queue are made up of dedicated high priority queues and low priority queues which reads on the claimed, “associating, for each respective priority level, one or more respective reserved buffer spaces reserved for use by memory access transactions associated with the respective priority level.”
Regarding (2), a virtual address is a type of memory address. A virtual address is defined by the “Free On-Line Dictionary of Computing” as, “[a] memory location accessed by an application program in a system with virtual memory such that intervening hardware and/or software maps the virtual address to real (physical) memory. During the course of execution of an application, the same virtual address may be mapped to many different physical addresses as data and programs are paged out and paged in to other locations.” Thus, a virtual address is commonly known in the art as a memory address. Virtual address and physical address are both types of memory address.
Thus, when Steely’s ARP maps the ranges of virtual addresses to corresponding priorities for each of the ranges in paragraphs 39-40, those virtual addresses are memory addresses which reads on the limitations at issue.
The examiner recommends that the applicant specify that the memory address is a physical address if that is really what the applicant desires the claimed memory address provided there is support for the memory address being a physical address in the applicant’s disclosure.
Applicant also argues that the double patenting rejection should be held in abeyance until the claims are indicated as allowable. The examiner disagrees.
As indicated by MPEP 804 (I)(B)(1), a response to a nonstatutory double patenting rejection must either show “that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s).” The present response does neither. Furthermore, MPEP 804 (I)(B)(1) explicitly states, “such a filing should not be held in abeyance.”
The examiner notes that the proper action is to hold the applicant’s response, non-responsive in this situation. The examiner would like to put the applicant on notice that any further response that does not respond properly to the nonstatutory double patenting rejection will be held as non-responsive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138