Prosecution Insights
Last updated: July 15, 2026
Application No. 18/791,177

ADAPTIVE READ DISTURB SCAN FOR ASYMMETRIC BLOCKS

Non-Final OA §102§103
Filed
Jul 31, 2024
Examiner
TECHANE, MUNA A
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
523 granted / 560 resolved
+25.4% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
17 currently pending
Career history
572
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
46.9%
+6.9% vs TC avg
§102
7.0%
-33.0% vs TC avg
§112
13.8%
-26.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 560 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings received on 07/31/2024 have been accepted by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-4, 9-12 & 17-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhou et al (US20240029802). Regarding claim 1, Zhou discloses a system(FIG 1; 101), comprising: a memory device(104); and a processing device(102), operatively coupled with the memory device(102 couped to 104), to perform operations comprising: receiving a request to perform a read disturb scan for a block of the memory device(FIG 3; 331), wherein the block is partially programmed; determining whether the block is asymmetric(FIG 2;[0026] discloses comprising a die 222, having regions, wherein part of the region is more asymmetric e.g., parts of regions distance that are close from the center 224) ; responsive to determining the block is asymmetric(FIG 2; [0026] determining which region is further out from center 224), identifying a target section of the block(FIG 2; [0026] 222-5 being the further out from the center 224); and executing the read disturb scan on an unprogrammed wordline of the target section (FIG 3; [0028-0030] discloses performing a read disturb operation on region with pa particular window size of data, wherein the read disturb operation is initiated to correct errors that where a read to one row of memory cells impacts the vts of unread memory cells in different rows of memory in same block). Regarding claim 2, Zhou discloses wherein the block determined to be asymmetric comprises a plurality of sections, and wherein each section comprises memory cells corresponding to a different physical block in the memory device (FIG 2-4; [0026-0032] discloses 222 die comprising A-E sections, each comprising e.g., performing the read disturb operation the memory die within the window size 445, suggests plurality of memory dies comprising memory cells). Regarding claim 3, Zhou discloses wherein the block comprises a top section and a bottom section (FIG 2; 222 comprising top and bottom section). Regarding claim 4, Zhou discloses wherein the block comprises a top section, a middle section, and a bottom section (FIG 2; 222 comprising top, middle and bottom section). Regarding claim 9, Zhou discloses a method, comprising: receiving a request to perform a read disturb scan for a block of a memory device(FIG 1 & 3; 331), wherein the block is partially programmed; determining whether the block is asymmetric (FIG 2;[0026] discloses comprising a die 222, having regions, wherein part of the region is more asymmetric e.g., parts of regions distance that are close from the center 224); responsive to determining the block is asymmetric(FIG 2; [0026] determining which region is further out from center 224), identifying a target section of the block FIG 2; [0026] 222-5 being the further out from the center 224); and executing the read disturb scan on an unprogrammed wordline of the target section(FIG 3; [0028-0030] discloses performing a read disturb operation on region with particular window size of data, wherein the read disturb operation is initiated to correct errors that where a read to one row of memory cells impacts the vts of unread memory cells in different rows of memory in same block). Regarding claim 10, Zhou discloses wherein the block determined to be asymmetric comprises a plurality of sections, and wherein each section comprises memory cells corresponding to a different physical block in the memory device(FIG 2-4; [0026-0032] discloses 222 die comprising A-E sections, each comprising e.g., performing the read disturb operation the memory die within the window size 445, suggests plurality of memory dies comprising memory cells). Regarding claim 11, Zhou discloses wherein the block comprises a top section and a bottom section(FIG 2; 222 comprising top and bottom section). Regarding claim 12, Zhou discloses wherein the block comprises a top section, a middle section, and a bottom section(FIG 2; 222 comprising top, middle and bottom section). Regarding claim 17, Zhou discloses a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: comprising: receiving a request to perform a read disturb scan for a block of a memory device(FIG 1 & 3; 331), wherein the block is partially programmed; determining whether the block is asymmetric (FIG 2;[0026] discloses comprising a die 222, having regions, wherein part of the region is more asymmetric e.g., parts of regions distance that are close from the center 224); responsive to determining the block is asymmetric(FIG 2; [0026] determining which region is further out from center 224), identifying a target section of the block FIG 2; [0026] 222-5 being the further out from the center 224); and executing the read disturb scan on an unprogrammed wordline of the target section(FIG 3; [0028-0030] discloses performing a read disturb operation on region with particular window size of data, wherein the read disturb operation is initiated to correct errors that where a read to one row of memory cells impacts the vts of unread memory cells in different rows of memory in same block). Regarding claim 18, Zhou discloses Zhou discloses wherein the block determined to be asymmetric comprises a plurality of sections, and wherein each section comprises memory cells corresponding to a different physical block in the memory device (FIG 2-4; [0026-0032] discloses 222 die comprising A-E sections, each comprising e.g., performing the read disturb operation the memory die within the window size 445, suggests plurality of memory dies comprising memory cells). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5, 13 & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al in view of Miller et al (US20200004465). Regarding claim 5, Zhou discloses wherein identifying the target section of the block comprises (FIG 2; [0026] 222). However, Zhou does not disclose obtaining an identifier of a last-written page (LWP) of the block; and identifying the target section corresponding to the identifier of the LWP in the memory device. In the same field of endeavor, Miller discloses obtaining an identifier of a last-written page (LWP) of the block; and identifying the target section corresponding to the identifier of the LWP in the memory device (FIG 5-6; [0072] discloses 520 memory device, and determining last written physical page is less than a threshold S606). Zhou and Miller are analogous art because they are all directed to a non-volatile memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Zhou to include Miller because they are from the same field of endeavor. Therefore, it would be obvious to include the teachings of Miller in the teachings of Zhou for the benefits avoiding a high-power consumption and incorrectly programmed during a programming operation of the non-volatile memory device [0014 Miller]. Regarding claim 13, Zhou discloses wherein identifying the target section of the block comprises (FIG 2; [0026] 222). However, Zhou does not disclose obtaining an identifier of a last-written page (LWP) of the block; and identifying the target section corresponding to the identifier of the LWP in the memory device. In the same field of endeavor, Miller discloses obtaining an identifier of a last-written page (LWP) of the block; and identifying the target section corresponding to the identifier of the LWP in the memory device (FIG 5-6; [0072] discloses 520 memory device, and determining last written physical page is less than a threshold S606). Zhou and Miller are analogous art because they are all directed to a non-volatile memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Zhou to include Miller because they are from the same field of endeavor. Therefore, it would be obvious to include the teachings of Miller in the teachings of Zhou for the benefits avoiding a high-power consumption and incorrectly programmed during a programming operation of the non-volatile memory device [0014 Miller]. Regarding claim 19, Zhou discloses wherein identifying the target section of the block comprises (FIG 2; [0026] 222). However, Zhou does not disclose obtaining an identifier of a last-written page (LWP) of the block; and identifying the target section corresponding to the identifier of the LWP in the memory device. In the same field of endeavor, Miller discloses obtaining an identifier of a last-written page (LWP) of the block; and identifying the target section corresponding to the identifier of the LWP in the memory device (FIG 5-6; [0072] discloses 520 memory device, and determining last written physical page is less than a threshold S606). Zhou and Miller are analogous art because they are all directed to a non-volatile memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Zhou to include Miller because they are from the same field of endeavor. Therefore, it would be obvious to include the teachings of Miller in the teachings of Zhou for the benefits avoiding a high-power consumption and incorrectly programmed during a programming operation of the non-volatile memory device [0014 Miller]. Allowable Subject Matter Claims 6-8, 14-16 & 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kim et al (US20240020037 FIG 3; discloses identified if last write WL is greater than a threshold in step 312). Sheperek et al (US20220115079 FIG 1 & 8). Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MUNA A TECHANE/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Jul 31, 2024
Application Filed
Apr 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12682969
ONE-TIME PROGRAMMABLE (OTP) ARRAYS WITH METAL-SEMICONDUCTOR-METAL (MSM) SELECTORS FOR INTEGRATED CIRCUITRY
3y 11m to grant Granted Jul 14, 2026
Patent 12675571
Guard Rows To Protect Regions Of Memory
2y 3m to grant Granted Jul 07, 2026
Patent 12676173
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH MULTI-WAY SHARING OF GAIN ELEMENT WITH SERIES TRANSISTOR
1y 9m to grant Granted Jul 07, 2026
Patent 12666957
ANTI-FUSE CELLS WITH BACKSIDE POWER RAILS
2y 4m to grant Granted Jun 23, 2026
Patent 12665034
MEMORY DEVICE, MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD THEREOF
1y 10m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+6.8%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 560 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month