DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 11-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2008/0211534).
In regards to claim 1, Jeong discloses of a circuit, comprising: a memory (207) configured to store an offset code (POFFSET, NOFFSET) that is predetermined (see Paragraph 0053); and a logic circuit (see 205, 206) configured to receive an impedance equilibrium (ZQ) calibration code as a first input (UP/DN, UP/DN’) and the offset code (POFFSET, NOFFSET) as a second input (see Fig 2), and provide a resistor code (PCONDE, NCODE) as an output based on the ZQ calibration code (UP/DN, UP/DN’) and the offset code (PFFSET, NOFFSET), wherein the offset code (POFFSET, NOFFSET) is independent from the ZQ calibration code (UP/DN, UP/DN’, see Fig 2).
In regards to claim 2, Jeong discloses of the circuit of claim 1, wherein the logic circuit (205, 206) is configured to convert the ZQ calibration code (UP/DN, UP/DN’) to the resistor code (PCODE, NCODE) by performing at least one of add, subtract, or shift on the ZQ calibration code (see Fig 2 and Paragraphs 0036, 0049).
In regards to claim 3, Jeong discloses of the circuit of claim 1, wherein the resistor code is a sum of the ZQ calibration code (UP/DN, UP/DN’) and the offset code (POFFSET, NOFFSET, see Fig 2 and Paragraphs 0036, 0049).
In regards to claim 4, Jeong discloses of the circuit of claim 1, wherein a number of digits of the offset code (POFFSET, NOFFSET) is less than or equal to a number of digits of the ZQ calibration code (see Paragraphs 0048, 0053; 6-bit code examples).
In regards to claim 5, Jeong discloses of the circuit of claim 1, wherein the offset code (POFFSET, NOFFSET) comprises one binary digit, two binary digits or three binary digits (see Paragraph 0054, 3-bit code example).
In regards to claim 6, Jeong discloses of the circuit of claim 1, wherein the offset code (POFFSET, NOFFSET) comprises at least one of a factory default code or a user-defined code (see Paragraphs 0029, 0029, 0053; initial values).
In regards to claim 7, Jeong discloses of the circuit of claim 1, wherein the memory (207) comprises a register (see Fig 2 and Paragraphs 0038, 0043, 0045).
In regards to claim 8, Jeong discloses of the circuit of claim 1, wherein the logic circuit (205, 206) comprises at least one of an adder, a subtractor, or a shifter (see Fig 2 and Paragraph 0049; a counter acts are an adder, subtractor and/or shifter).
In regards to claim 11, Jeong discloses of the circuit of claim 1, wherein the circuit is configured to receive the ZQ calibration code from a ZQ calibration circuit (see Figs 2-3 and Paragraphs 0023-0047).
In regards to claim 12, Jeong discloses of a method, comprising: receiving, as a first input of a logic circuit (205, 206), an impedance equilibrium (ZQ) calibration code (UP/DN, UP/DN’); receiving, as a second input of the logic circuit (205, 206), an offset code (POFFSET, NOFFSET) from a memory (207, see Fig 2), the offset code (POFFSET, NOFFSET) being predetermined and stored in the memory (207, see Paragraph 0053), wherein the offset code (POFFSET, NOFFSET) is independent from the ZQ calibration code (UP/DN, UP/DN’ see Fig 2); and providing, as an output of the logic circuit (205, 206), a resistor code (PCODE, NCODE) based on the ZQ calibration code (UP/DN, UP/DN’) and the offset code (POFFSET, NOFFSET, see Fig 2).
In regards to claim 13, Jeong discloses of the method of claim 12, wherein providing, as the output of the logic circuit (205, 206), the resistor code (PCODE, NCODE) comprises: converting the ZQ calibration code (UP/DN, UP/DN’) to the resistor code (PCODE, NCODE) by performing at least one of add, subtract, or shift on the ZQ calibration code (UP/DN, UP/DN’, see Fig 2 and Paragraphs 0036, 0049).
In regards to claim 14, Jeong discloses of the method of claim 12, wherein the resistor code (PCODE, NCODE) is a sum of the ZQ calibration code (UP/DN, UP/DN’) and the offset code (POFFSET, NOFFSET; see Fig 2 and Paragraphs 0036, 0049).
In regards to claim 15, Jeong discloses of the method of claim 12, wherein the offset code (POFFSET, NOFFSET) comprises one binary digit, two binary digits or three binary digits (see Paragraph 0054, 3-bit code example).
In regards to claim 16, Jeong discloses of the method of claim 12, wherein the offset code (POFFSET, NOFFSET) comprises at least one of a factory default code or a user-defined code (see Paragraphs 0029, 0029, 0053; initial values).
In regards to claim 17, Jeong discloses of the method of claim 12, comprising: transmitting the resistor code (PCODE, NCODE) to a buffer circuitry (see 210, 220); and adjusting a resistance of one or more resistors in the buffer circuitry (210, 220) based on the resistor code (PCODE, NCODE, see Fig 2).
In regards to claim 20, Jeong discloses of a memory system, comprising: a memory device configured to store data and comprising a memory array and a circuit, the circuit comprising: a memory (207) configured to store an offset code (POFFSET, NOFFSET) that is predetermined (see Paragraph 0053); and a logic circuit (205, 206) configured to receive a ZQ calibration code (UP/DN, UP/DN’) as a first input and the offset code (POFFSET, NOFFSET) as a second input, and provide a resistor code (PCODE, NCODE) as an output based on the ZQ calibration code (UP/DN, UP/DN’) and the offset code (POFFSET, NOFFSET), wherein the offset code (POFFSET, NOFFSET) is independent from the ZQ calibration code (UP/DN, UP/DN’, see Fig 2); and a memory controller coupled to the memory device and configured to operate the memory device (see Paragraphs 0002-0006, 0012-0014, 0016-0018).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2008/0211534) in view of Zhang et al. (US 2022/0321122).
In regards to claims 9-10 and 18-19, Jeong discloses of the circuit of claim 1 and method of claim 12 as found within the respective explanations above.
However, Jeong does not explicitly disclose of wherein the resistor code is a RON_CODE and/or RTT_CODE, and the circuit is configured to provide the RON_CODE and/or RTT_CODE to one or more resistors in buffer circuitry for adjusting the resistance of the one or more resistors to output data from a memory array.
Zhang discloses of a circuit, comprising: a memory (1300) configured to provide an offset code (POFSC, NOFSC); and a logic circuit (comprised of 110, 310a-b and 210, 220, see Figs 1-3) configured to receive an impedance equilibrium (ZQ) calibration code (ZQ Calibration) as a first input and another code (Factory Setting) as a second input, and provide a resistor code (Resistor Code) as an output based on the ZQ calibration code (ZQ Calibration) and the other code (Factory Setting); adjusting a resistance of one or more resistors based on the resistor code (Resistor Code, Ron Resistor Code, Rtt Resistor code, see Figs 1-3); wherein the resistor code is a RON_CODE and/or RTT_CODE (see Figs 2 and 3), and the circuit is configured to provide the RON_CODE and/or RTT_CODE (see Figs 2 and 3) to one or more resistors or adjusting the resistance of the one or more resistors to output data from a memory array (see Figs 1-3 and Paragraphs 0023-0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have the resistor code being labeled/indicated as RON_CODE and/or RTT_CODE as taught by Zhang for providing resistor calibration signals Ron and Rtt signals to resistance devices in NAND flash memory devices for achieving the desired value for calibration of the memory device.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844