The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 11/12/2025.
Claims 1, 2, 4, 5, 8, 9, 11, 12, 15, 16, 18 and 19 are amended. Claims 1-20 are pending.
Claims 1, 3-8, 10-15 and 17-20 are rejected. Claims 2, 9 and 16 are objected to.
Response to Arguments
Applicant`s arguments filed November 12, 2025 have been fully considered and they are persuasive with respect to prior art rejection.
As per the 103 rejection of claims 1, 8 and 15, Applicant argued Sharon fails to disclose or suggest the feature of " determining a position for the memory portion within the partial block"; where examiner relies on a newly cited reference Zhang to disclose the claimed limitation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-8, 10, 13-15, 17 and 20 rejected under 35 U.S.C. 103(a) as being unpatentable over Muchherla et al. (US PGPUB 2022/0375530 hereinafter referred to as Muchherla), and further in view of Zhang et al. (US PGPUB 2024/0170090) (hereinafter ‘Zhang’).
As per independent claim 1, Muchherla discloses a method comprising: receiving, by a memory subsystem, a read command from a host device to read data from a memory portion of the memory subsystem [(Paragraphs 0020 and 0030 ; FIGs 1 and 2 and related text) where Muchherla teaches where the host system can initiate a data operation (e.g., write, read, erase, etc.) on a memory sub-system. The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data on a memory device at the memory sub-system and to read data from the memory device on the memory sub-system. The data to be read or written, as specified by a host request, is hereinafter referred to as “host data.” A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data to correspond to the claimed limitation]; determining that the memory portion comprises a partial block [(Paragraphs 0024 and 0054 ; FIGs 1 and 3 and related text) where Muchherla teaches where the temporal voltage shift is selectively tracked for a programmed set of memory cells grouped by block families, and appropriate voltage offsets, which are based on block affiliation with a certain block family, are applied to the base read levels in order to perform read operations. “Block family” herein shall refer to a possibly non-contiguous set of memory cells (which can reside in one or more full and/or partial blocks, the latter referred to as “partitions” herein) that have been programmed within a specified time window and temperature window, and thus are expected to exhibit similar or correlated changes in their respective data state metrics to correspond to the claimed limitation]; determining a memory bin for the memory portion in response to determining that the memory portion comprises the partial block [(Paragraphs 0024 and 0054-0057 ; FIGs 1 and 3 and related text) where Muchherla teaches where the pages or blocks (or groups of memory cells at another granularity) of the memory device are grouped into block families 330A-330N, such that each block family includes one or more pages or blocks that have been programmed within a specified time window, potentially varied by average temperature while the block family is open (FIG. 4). As noted herein above, since the time elapsed after programming and temperature are the main factors affecting the temporal voltage shift, all pages, blocks, and/or partitions within a single block family are presumed to exhibit similar distributions of threshold voltages in memory cells, and thus would require the same voltage offsets for read operations as time passes to correspond to the claimed limitation], wherein the memory bin corresponds to an age of data stored in the memory portion [(Paragraphs 0024 and 0054-0057 ; FIGs 1 and 3 and related text) where Muchherla teaches where FIG. 3 is an example graph 300 illustrating the dependency of a threshold voltage offset 310 on the time after program 320, e.g., the period of time elapsed since a page had been programmed, in accordance with some embodiments. FIG. 4 is an example graph 400 illustrating the dependency of the threshold voltage offset on both time after program (TAP) and average temperature, in accordance with some embodiments. As schematically illustrated by FIG. 3, pages or blocks (or groups of memory cells at another granularity) of the memory device are grouped into block families 330A-330N, such that each block family includes one or more pages or blocks that have been programmed within a specified time window, potentially varied by average temperature while the block family is open (FIG. 4). As noted herein above, since the time elapsed after programming and temperature are the main factors affecting the temporal voltage shift, all pages, blocks, and/or partitions within a single block family are presumed to exhibit similar distributions of threshold voltages in memory cells, and thus would require the same voltage offsets for read operations as time passe to correspond to the claimed limitation]; determining a position for the memory portion [(Paragraphs 0024 and 0067-0068 ; FIGs 1 and 3 and related text) where Muchherla teaches where the data state metrics 626 include a quantity that is measured or inferred from the behavior of data within the memory cells (e.g., of a page or block) of the block family. The data state metrics 626 reflect the voltage state of the data stored on the memory device 130. For example, to perform a high-frequency scan of multi-level cells, the memory scanner 614 can measure a position of a first specified voltage level distribution (e.g., a seventh voltage level distribution, or L7), a center of a valley of a second specified voltage level distribution (e.g., a sixth voltage level distribution, or L6) or of the first specified voltage level distribution, a fifth valley location, a seventh distribution median voltage, a temporal voltage shift, a degree of read disturb, or the like. The position metric can be measured by performing at least one of a soft bit read, a margin read, a read, or an extrapolation-based read of the memory cells. Other highly accurate, position-based measurements are envisioned, including at other tails or median locations of voltage level distributions and/or valleys therebetween. FIG. 7A and FIG. 7B provide examples of how position metrics for a seventh voltage level distribution (L7) can be determined for purposes of explanation. FIG. 7A is a graph that illustrates a measurement of a left position metric for a specified voltage level distribution, according to an embodiment. For purposes of explanation, the specified voltage level distribution is the seventh voltage level distribution in multi-level cells. The left position metric can be identified by counting bits from the left and measuring the voltage level of the curve of the seventh voltage level distribution at 2,000 bits. Thus, the location of the left position metric can be located by counting 2,000 bits from the left-most boundary (or tail) to correspond to the claimed limitation]; and applying a voltage offset to a read voltage for the memory portion using the memory bin and the position [(Paragraphs 0065-0067 and 0071-0076 ; FIGs 1 and 6 and related text) where Muchherla teaches where the multi-tier bin calibrator 618 can then assign (or verify the assignment of) a threshold voltage offset bin to the measured memory units (e.g., page(s), blocks, or block families) based on a comparison of the measured data state metric to state metric values corresponding to one or more threshold voltage offset value(s) within a set of threshold voltage offset bins. Over time, these state metric values (e.g., TVS) can shift and thus end up more closely correlating with the threshold voltage offset value(s) of a different bin. Thus, the block family manager 113 directs additional, periodic sampling to continue to calibrate the assignment of threshold voltage offset bins to these memory units, usually with the goal to assign each block family to a threshold voltage offset bin that minimizes RBER to correspond to the claimed limitation].
Muchherla does not appear to explicitly disclose determining a position for the memory portion within the partial block.
Zhang discloses determining a position for the memory portion within the partial block [(Paragraphs 0022, 0029 and 0089) where Zhang teaches wherein the method 900 may include determining an LWP location associated with an LWP of a block of a memory of the memory device (block 920). As further shown in FIG. 9, the method 900 may include determining one of: a WLG associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a PB fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio (block 930). As further shown in FIG. 9, the method 900 may include performing a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage associated with the power loss error detection procedure (block 940) to correspond to the claimed limitation].
Muchherla and Zhang are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Muchherla and Zhang before him or her, to modify the system of Muchherla to include the location determination within the partial block of Zhang because it will improve data storage access performance.
The motivation for doing so would be to [ power loss error detection using partial block handling (Paragraph 0002 by Zhang)].
Therefore, it would have been obvious to combine Muchherla and Zhang to obtain the invention as specified in the instant claim.
Therefore, it would have been obvious to combine Muchherla and Zhang to obtain the invention as specified in the instant claim.
As per claim 3, Muchherla discloses wherein applying the voltage offset to the read voltage further uses a memory state level of the read voltage [(Paragraphs 0024 and 0065 ; FIGs 1 and 6 and related text) where Muchherla teaches where the temporal voltage shift is selectively tracked for a programmed set of memory cells grouped by block families, and appropriate voltage offsets, which are based on block affiliation with a certain block family, are applied to the base read levels in order to perform read operations. “Block family” herein shall refer to a possibly non-contiguous set of memory cells (which can reside in one or more full and/or partial blocks, the latter referred to as “partitions” herein) that have been programmed within a specified time window and temperature window, and thus are expected to exhibit similar or correlated changes in their respective data state metrics. A block family can be made with any granularity, containing only whole codewords, whole pages, whole super pages, or whole superblocks, or any combination of these. “Data state metric” herein shall refer to a quantity that is measured or inferred from the state of data stored on a memory device. Specifically, the data state metrics can reflect the state of the temporal voltage shift, the degree of read disturb, and/or other measurable functions of the data state as will be discussed in more detail. A composite data state metric is a function (e.g., a weighted sum) of a set of component state metrics; the multi-tier bin calibrator 618 can then assign (or verify the assignment of) a threshold voltage offset bin to the measured memory units (e.g., page(s), blocks, or block families) based on a comparison of the measured data state metric to state metric values corresponding to one or more threshold voltage offset value(s) within a set of threshold voltage offset bins. Over time, these state metric values (e.g., TVS) can shift and thus end up more closely correlating with the threshold voltage offset value(s) of a different bin to correspond to the claimed limitation].
As per claim 6, Muchherla discloses determining an updated age of data for the memory portion; and updating the memory bin using the updated age [(Paragraphs 0024, 0054 and 0081 ; FIGs 1 and 3 and related text) where Muchherla teaches where the temporal voltage shift is selectively tracked for a programmed set of memory cells grouped by block families, and appropriate voltage offsets, which are based on block affiliation with a certain block family, are applied to the base read levels in order to perform read operations. “Block family” herein shall refer to a possibly non-contiguous set of memory cells (which can reside in one or more full and/or partial blocks, the latter referred to as “partitions” herein) that have been programmed within a specified time window and temperature window, and thus are expected to exhibit similar or correlated changes in their respective data state metrics; when the multi-bin calibrator 618 updates a threshold voltage offset bin to which a memory unit (e.g., page, block, partition, or block family) are assigned by way of bin calibration, the multi-bin calibrator 618 can update either the indexing from the superblock table 910 to a different vector of die-based bin pointers in the block family table 920 or update the vector itself in the block family table 920 (to which the memory unit is indexed) to include different values for the threshold voltage offset bin(s) depending on die. In either case, the result to update the pointer for the memory unit to the correct threshold voltage offset bin within the offset table 930 that includes the threshold voltage offset values that closest match a measured value of a data state metric and/or exhibit the lowest RBER during read operations to correspond to the claimed limitation].
As per claim 7, Muchherla discloses wherein the memory bin further corresponds to a temperature of the memory portion during storage of the data [(Paragraphs 0054-0055 and 0054; FIGs 1 and 3 and related text) where Muchherla teaches where Block families can be created asynchronously with respect to page programming events. In an illustrative example, the memory sub-system controller 115 of FIG. 1 can create a new block family whenever a specified period of time (e.g., a predetermined number of minutes) has elapsed since creation of the last block family, which time period can vary significantly depending on an average temperature associated with pages during programming. More specifically, the entire asymptotic curve illustrated in FIG. 3 can be shifted to have a steeper curve with respect to time, as illustrated in FIG. 4, as average temperature increases. In FIG. 4, the curve associated with T1 decreases with time at a much slower rate (e.g., about 100 times slower) compared to the curve associated with T3. The curves in FIG. 4 look differently from the curve in FIG. 3 due to being graphed at log 10 scale in order to illustrate the difference in slow charge loss as temperature varies. Slow charge loss is illustrated along the vertical access for the seventh valley (V7) based on digital-to-analog (DAC) converted voltage values, also referred to as DACs. Each DAC can represent a certain number of millivolts (mV), here about 10 mV to correspond to the claimed limitation].
As per independent claim 15, Muchherla discloses a system comprising: a plurality of memory devices; and a processing device, operatively coupled with the plurality of memory devices, to: receive, by a memory subsystem, a read command from a host device to read data from a memory portion of the memory subsystem [(Paragraphs 0020 and 0030 ; FIGs 1 and 2 and related text) where Muchherla teaches where the host system can initiate a data operation (e.g., write, read, erase, etc.) on a memory sub-system. The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data on a memory device at the memory sub-system and to read data from the memory device on the memory sub-system. The data to be read or written, as specified by a host request, is hereinafter referred to as “host data.” A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data to correspond to the claimed limitation]; determining that the memory portion comprises a partial block [(Paragraphs 0024 and 0054 ; FIGs 1 and 3 and related text) where Muchherla teaches where the temporal voltage shift is selectively tracked for a programmed set of memory cells grouped by block families, and appropriate voltage offsets, which are based on block affiliation with a certain block family, are applied to the base read levels in order to perform read operations. “Block family” herein shall refer to a possibly non-contiguous set of memory cells (which can reside in one or more full and/or partial blocks, the latter referred to as “partitions” herein) that have been programmed within a specified time window and temperature window, and thus are expected to exhibit similar or correlated changes in their respective data state metrics to correspond to the claimed limitation]; determining a memory bin for the memory portion in response to determining that the memory portion comprises the partial block [(Paragraphs 0024 and 0054-0057 ; FIGs 1 and 3 and related text) where Muchherla teaches where the pages or blocks (or groups of memory cells at another granularity) of the memory device are grouped into block families 330A-330N, such that each block family includes one or more pages or blocks that have been programmed within a specified time window, potentially varied by average temperature while the block family is open (FIG. 4). As noted herein above, since the time elapsed after programming and temperature are the main factors affecting the temporal voltage shift, all pages, blocks, and/or partitions within a single block family are presumed to exhibit similar distributions of threshold voltages in memory cells, and thus would require the same voltage offsets for read operations as time passes to correspond to the claimed limitation], wherein the memory bin corresponds to an age of data stored in the memory portion and a temperature of the memory portion during storage of the data [(Paragraphs 0024 and 0054-0057 ; FIGs 1 and 3 and related text) where Muchherla teaches where FIG. 3 is an example graph 300 illustrating the dependency of a threshold voltage offset 310 on the time after program 320, e.g., the period of time elapsed since a page had been programmed, in accordance with some embodiments. FIG. 4 is an example graph 400 illustrating the dependency of the threshold voltage offset on both time after program (TAP) and average temperature, in accordance with some embodiments. As schematically illustrated by FIG. 3, pages or blocks (or groups of memory cells at another granularity) of the memory device are grouped into block families 330A-330N, such that each block family includes one or more pages or blocks that have been programmed within a specified time window, potentially varied by average temperature while the block family is open (FIG. 4). As noted herein above, since the time elapsed after programming and temperature are the main factors affecting the temporal voltage shift, all pages, blocks, and/or partitions within a single block family are presumed to exhibit similar distributions of threshold voltages in memory cells, and thus would require the same voltage offsets for read operations as time passe; where Block families can be created asynchronously with respect to page programming events. In an illustrative example, the memory sub-system controller 115 of FIG. 1 can create a new block family whenever a specified period of time (e.g., a predetermined number of minutes) has elapsed since creation of the last block family, which time period can vary significantly depending on an average temperature associated with pages during programming. More specifically, the entire asymptotic curve illustrated in FIG. 3 can be shifted to have a steeper curve with respect to time, as illustrated in FIG. 4, as average temperature increases. In FIG. 4, the curve associated with T1 decreases with time at a much slower rate (e.g., about 100 times slower) compared to the curve associated with T3 to correspond to the claimed limitation]; determining a position for the memory portion [(Paragraphs 0024 and 0067-0068 ; FIGs 1 and 3 and related text) where Muchherla teaches where the data state metrics 626 include a quantity that is measured or inferred from the behavior of data within the memory cells (e.g., of a page or block) of the block family. The data state metrics 626 reflect the voltage state of the data stored on the memory device 130. For example, to perform a high-frequency scan of multi-level cells, the memory scanner 614 can measure a position of a first specified voltage level distribution (e.g., a seventh voltage level distribution, or L7), a center of a valley of a second specified voltage level distribution (e.g., a sixth voltage level distribution, or L6) or of the first specified voltage level distribution, a fifth valley location, a seventh distribution median voltage, a temporal voltage shift, a degree of read disturb, or the like. The position metric can be measured by performing at least one of a soft bit read, a margin read, a read, or an extrapolation-based read of the memory cells. Other highly accurate, position-based measurements are envisioned, including at other tails or median locations of voltage level distributions and/or valleys therebetween. FIG. 7A and FIG. 7B provide examples of how position metrics for a seventh voltage level distribution (L7) can be determined for purposes of explanation. FIG. 7A is a graph that illustrates a measurement of a left position metric for a specified voltage level distribution, according to an embodiment. For purposes of explanation, the specified voltage level distribution is the seventh voltage level distribution in multi-level cells. The left position metric can be identified by counting bits from the left and measuring the voltage level of the curve of the seventh voltage level distribution at 2,000 bits. Thus, the location of the left position metric can be located by counting 2,000 bits from the left-most boundary (or tail) to correspond to the claimed limitation]; and applying a voltage offset to a read voltage for the memory portion using the memory bin and the position [(Paragraphs 0065-0067 and 0071-0076 ; FIGs 1 and 6 and related text) where Muchherla teaches where the multi-tier bin calibrator 618 can then assign (or verify the assignment of) a threshold voltage offset bin to the measured memory units (e.g., page(s), blocks, or block families) based on a comparison of the measured data state metric to state metric values corresponding to one or more threshold voltage offset value(s) within a set of threshold voltage offset bins. Over time, these state metric values (e.g., TVS) can shift and thus end up more closely correlating with the threshold voltage offset value(s) of a different bin. Thus, the block family manager 113 directs additional, periodic sampling to continue to calibrate the assignment of threshold voltage offset bins to these memory units, usually with the goal to assign each block family to a threshold voltage offset bin that minimizes RBER to correspond to the claimed limitation].
Muchherla does not appear to explicitly disclose determining a position for the memory portion within the partial block.
Zhang discloses determining a position for the memory portion within the partial block [(Paragraphs 0022, 0029 and 0089) where Zhang teaches wherein the method 900 may include determining an LWP location associated with an LWP of a block of a memory of the memory device (block 920). As further shown in FIG. 9, the method 900 may include determining one of: a WLG associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a PB fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio (block 930). As further shown in FIG. 9, the method 900 may include performing a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage associated with the power loss error detection procedure (block 940) to correspond to the claimed limitation].
Muchherla and Zhang are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Muchherla and Zhang before him or her, to modify the system of Muchherla to include the location determination within the partial block of Zhang because it will improve data storage access performance.
The motivation for doing so would be to [ power loss error detection using partial block handling (Paragraph 0002 by Zhang)].
Therefore, it would have been obvious to combine Muchherla and Zhang to obtain the invention as specified in the instant claim.
As for independent claim 8, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claims 10 and 17, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
As for dependent claims 13 and 20, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
As for dependent claim 14, the applicant is directed to the rejections to claim 7 set forth above, as they are rejected based on the same rationale.
Claims 4, 5, 11, 12, 18 and 19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Muchherla, as applied to claims 1, 8 and 15 above, in view of Muchherla et al. (US PGPUB 2023/0214133) (hereinafter ‘Muchherla133’) and in view of Sheperek et al. (US PGPUB 2022/0237094) (hereinafter ‘Sheperek’).
As per claim 4, Muchherla discloses the method of claim 1.
Muchherla does not appear to explicitly disclose wherein the position comprises an inner position or a boundary position.
However, Muchherla133 discloses wherein the position comprises an inner position or a boundary position [(Paragraphs 0055-0056 ; FIGs 1 and 2 and related text) where Muchherla133 teaches where the first active data wordline(s) 210A include a first active boundary wordline 211A, which can be adjacent to a first retired boundary wordline 212A. A first retired inner wordline 214A can be located on an “inner” side of the first retired boundary wordline 212A, e.g., adjacent to the first retired boundary wordline 212A. The first retired inner wordline 214A can be adjacent to one of the non-programmed retired wordline(s) 216. Adjacent wordlines can be, e.g., wordlines that are not separated by another wordline between the adjacent wordlines to correspond to the claimed limitation].
Muchherla and Muchherla133 are analogous art because they are from the same field of endeavor of data storage management.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Muchherla and Muchherla133 before him or her, to modify the method of Muchherla to include the charge loss prevention method of Muchherla133 because it will enhance system performance.
The motivation for doing so would be for the wear of these blocks is leveled and accordingly the life of the non-volatile memory is prolonged (Paragraph 0018 by Muchherla133)].
Muchherla does not appear to explicitly disclose wherein a first voltage offset for earlier memory bins with the inner position is greater than a second voltage offset for later memory bins with the inner position.
However, Sheperek discloses wherein a first voltage offset for earlier memory bins with the inner position is greater than a second voltage offset for later memory bins with the inner position [(Paragraphs 0019-0024 and 0060-0062 ; FIGs 1 and 4A-B and related text) where Sheperek teaches where BF28 is identified as the oldest (i.e., the least recently created) block family in Bin 1 because at least a part of the data in BF28 is still within the time after program (TAP) defined by Bin 1. Further, BF30 has just been created (e.g., closed as a BF) and is the youngest (i.e., the most recently created) block family in Bin 1. Similarly, BF27 is identified as the youngest block family in the second threshold voltage offset bin (Bin 2) and BF24 as the oldest block family in Bin 2 to correspond to the claimed limitation].
Muchherla and Sheperek are analogous art because they are from the same field of endeavor of data storage management.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Muchherla and Sheperek before him or her, to modify the method of Muchherla to include the adaptive voltage offset adjustment method of Sheperek because it will enhance system performance.
The motivation for doing so would be for to ensure that read error is minimized at any given time by performing the scans frequently enough to identify the appropriate time to assign the BF to a new voltage bin (Paragraph 0025 by Sheperek)].
Therefore, it would have been obvious to combine Muchherla and Sheperek to obtain the invention as specified in the instant claim.
As per claim 5, Sheperek discloses wherein the position comprises an inner position or a boundary position and wherein a first voltage offset for earlier memory bins with the boundary position is less than a second voltage offset for later memory bins with the boundary position [(0019-0025 and 0060-0062 ; FIGs 1 and 4A-B and related text) where Sheperek teaches wherein the “Calibration” herein shall refer to the process of altering a read level value (possibly by adjusting a read level offset or read level base) to better match the ideal read levels for a read or set of reads. If the BF scan indicates it is necessary to adjust the read level, the calibration process can then update a bin pointer associated with the die and block family to point to a voltage bin that corresponds to the measured value of the data state metric. Each voltage bin is associated with a voltage offset to be applied for read operations to correspond to the claimed limitation].
As for dependent claims 9 and 16, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
As for dependent claims 11 and 18, the applicant is directed to the rejections to claim 4 set forth above, as they are rejected based on the same rationale.
As for dependent claims 12 and 19, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 6-10 and 15-16, but would be allowable if claims are amended to overcome the 112 rejections.
The reason for allowance of claims 2, 9 and 16 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 2, the limitations of “wherein the position comprises an inner position or a boundary position of the memory portion within the partial block, wherein the memory bin comprises an early memory bin or a late memory bin, wherein an estimated charge loss for a memory portion of the early memory bin is less than an estimated charge loss for a memory portion of the late memory bin, and wherein applying the voltage offset comprises: applying a first voltage offset if the position is the inner position or if the position is the boundary position and the memory bin is the early memory bin; and applying a second voltage offset if the position is the boundary position and the memory bin is the late memory bin, wherein the second voltage offset is greater than the first voltage offset”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohamed Gebril whose telephone number is (571)270-1857 and email address is mohamed.gebril @uspto.gov. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135