DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/31/2024 and 12/01/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
2 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3 Claim(s) 1-10, 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liktor et al. (US 20170287100 A1) in view of Doyle et al (US 20200211147 A1).
4 Regarding claim 1, Liktor teaches an apparatus for graphics processing, comprising: a memory; and a processor coupled to the memory and, based at least in part on information stored in the memory, the processor is configured to ([0025] reciting “A cache line aware reordering method considers bounding volume (BV) memory footprints that are comparably small to quantized Bounding Volume Hierarchy (BVH) nodes.”; [0059] reciting “The L1 caches fetch missing cache lines from a higher latency L2 cache 48, which is banked and shared across all traversal clusters. This L2 cache may be shared with last level cache on current processor graphics, which may cache nodes as well as shading data.”):
obtain a first indication of a low-resolution bounding volume hierarchy (BVH) comprising a set of conservative candidate nodes that are associated with corresponding internal nodes of conventional BVH T, using e.g. depth-first layout, given the desired child (small) pointer size is n bits.”; [0150] reciting “One example embodiment may be a method comprising implementing reduced precision ray traversal for a bounding volume-node hierarchy in a graphics processor, using address clustering as one clustering level, and using cache clustering as another clustering level. The method may also include generating low resolution child pointers between clustered nodes… The method may also include only loading glue nodes when crossing a border between clusters. The method may also include merging child nodes in a cluster until the cluster is full.”);
traverse the low-resolution BVH by: determining whether a ray intersects a primitive leaf of a conservative candidate node of the set of conservative candidate nodes in response to a first determination that the ray intersects the conservative candidate node ([0031] reciting “The impact of memory layout on bandwidth is also illustrated in FIG. 1 where a simple traversal path accessing nodes through two different node orderings is depicted. Traversal of a ray that intersects two leaf nodes n and o is shown in the top depiction.”; [0056] reciting “Leaf Unit (LU) 34 fetches and processes leaf as well as glue nodes. It includes a node fetch and a dispatch stage. The node fetch stage is identical to the TU. The node data includes a bit flag which indicates if a primitive leaf or a glue node was fetched. For primitive leaves, the LU issues a request to the PU 36 for triangle intersection. If a glue node is received, the root offset of the new address cluster is sent back to the TU that initiated the request.”); and
5 Liktor does not explicitly teach to obtain a first indication of a low-resolution bounding volume hierarchy (BVH) comprising a set of conservative candidate nodes that are associated with corresponding internal nodes of a full-resolution BVH; … traversing an internal node of the full-resolution BVH that corresponds with the conservative candidate node in response to a second determination that the ray does not intersect the primitive leaf; and output a second indication of a ray trace hit or a ray trace miss based on at least one of a third determination that the ray intersects the primitive leaf of the conservative candidate node or a traversal of the internal node of the full-resolution BVH that corresponds with the conservative candidate node.
6 Doyle teaches to obtain a first indication of a low-resolution bounding volume hierarchy (BVH) comprising a set of conservative candidate nodes that are associated with corresponding internal nodes of a full-resolution BVH ([0250] reciting “The convolutional layers are sparsely connected, which differs from traditional neural network configuration found in the fully connected layers 2608. Traditional neural network layers are fully connected, such that every output unit interacts with every input unit.”; [0275] reciting “During operation, the media processor 3102 and vision processor 3104 can work in concert to accelerate computer vision operations. The media processor 3102 can enable low latency decode of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip-memory 3105.”; [0288] reciting “In one embodiment, the ray tracing cores 3150 accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing cores 3150 include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes.”); …
traversing an internal node of the full-resolution BVH that corresponds with the conservative candidate node in response to a second determination that the ray does not intersect the primitive leaf ([0304] reciting “In ray tracing architectures, rays are traversed through a BVH to determine ray-primitive intersections. For example, if a ray does not pass through the root node of the BVH, then the ray does not intersect any of the primitives enclosed by the BVH and no further processing is required for the ray with respect to this set of primitives.”);
and output a second indication of a ray trace hit or a ray trace miss based on at least one of a third determination that the ray intersects the primitive leaf of the conservative candidate node or a traversal of the internal node of the full-resolution BVH that corresponds with the conservative candidate node ([0290] reciting “In one embodiment, each ray tracing core 3150 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, in one embodiment, the multi-core group 3100A can simply launch a ray probe, and the ray tracing cores 3150 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc) to the thread context.”).
7 It would have been obvious to one with ordinary skill before the effective filing date of the claimed invention, to have modified the method (taught by Liktor) to incorporate the teachings of Doyle to provide a full resolution based on the BVH and conservative nodes provided by the teachings of Liktor, as well as traversing internal nodes to determine that the ray does not intersect and to provide additional indications regarding various intersections. Doing so would save the graphics core from being overloaded with thousands of instructions per ray as stated by Doyle ([0290] recited).
8 Regarding claim 2, Liktor in view of Doyle teaches the apparatus of claim 1 (see claim 1 rejection above), wherein the conservative candidate node comprises a first set of primitive leaves and is associated with an axis-aligned bounding box (AABB) that bounds a second set of primitive leaves, wherein the first set of primitive leaves is a subset of the second set of primitive leaves, wherein the internal node of the full-resolution BVH that corresponds with the conservative candidate node comprises a third set of child primitive leaves comprising the second set of primitive leaves (Doyle; [0197] reciting “To improve the above techniques, one embodiment of the invention augments the denoising phase to generate new training data every frame or a subset of frames (e.g., every N frames where N=2, 3, 4, 10, 25, etc).”; [0368] reciting “Each inner node 4610 corresponds to a bounding volume which is typically an axis-aligned bounding box. In one embodiment, a in a first sequence of operations, the node refitting circuitry 4509 iterates over all leaf nodes 4620 which point to leaf data and updates their bounding volume. In a second sequence of operations, the node refitting circuitry 4509 iterates in reverse order over the inner node array. In the illustrated example, this means the order C, E, D, B, and A.”; [0439] reciting “Most recently, there has been a move towards clustering-based BVH construction techniques, which involve local optimizations of treelets (small sub-sections of a tree) or clustering of small subsets of primitives/nodes.”).
9 Regarding claim 3, Liktor in view of Doyle teaches the apparatus of claim 1, wherein the processor is further configured to: traverse the low-resolution BVH by at least one of (see claim 1 rejection above):
traversing a second internal node of the low-resolution BVH (Liktor; [0035] reciting “The number of glue nodes is much less than the number of internal nodes. Assuming that the original BVH contains 2N+1 nodes (N internal), and the average size of an AC is √{square root over (2N+1)}, the number of glue nodes is at the magnitude of √{square root over (N)}. Using regular pointers would increase the size of at least N nodes. Furthermore, glue nodes only generate bandwidth when the child node is traversed, not when accessing the parent node.”); or
traversing the conservative candidate node of the set of conservative candidate nodes in response to a fourth determination that the ray intersects the second internal node of the low-resolution BVH (Doyle; [0288] reciting “In one embodiment, the ray tracing cores 3150 accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing cores 3150 include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes”; [0350] reciting “Inner traversal computes ray-BVH intersections by traversing the BVH and computing ray-box and ray-triangle intersections. Inner traversal is spawned in the same manner as shaders by sending a message to the messaging circuitry 4004 which relays the corresponding spawn message to the ray-BVH intersection circuitry 4005 which computes ray-BVH intersections.”); and
output a third indication of a second ray trace hit or a second ray trace miss based on at least one of a fifth determination that the ray does not intersect the second internal node of the low-resolution BVH (Doyle; [0290] reciting “In one embodiment, each ray tracing core 3150 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, in one embodiment, the multi-core group 3100A can simply launch a ray probe, and the ray tracing cores 3150 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc) to the thread context.”), or a sixth determination that the ray does not intersect the conservative candidate node.
10 Regarding claim 4, Liktor in view of Doyle teaches the apparatus of claim 1 (see claim 1 rejection above), wherein the processor is further configured to: determine whether a second traversal of the ray intersects on a first hit (Doyle; [0290] reciting “In one embodiment, each ray tracing core 3150 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, in one embodiment, the multi-core group 3100A can simply launch a ray probe, and the ray tracing cores 3150 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc) to the thread context.”); and
traverse the internal node of the full-resolution BVH that corresponds with the conservative candidate node in response to a fourth determination that the traversal of the ray does not end on the first hit wherein the ray intersects the primitive leaf (Doyle; [0294] reciting “In general, the various cores 3150, 3140, 3130 may support a ray tracing instruction set that includes instructions/functions for ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions. More specifically, one embodiment includes ray tracing instructions…”; [0300] reciting “Miss—Indicates that a ray misses all geometry within a scene, or specified region of a scene.”).
11 Regarding claim 5, Liktor in view of Doyle teaches the apparatus of claim 1 (see claim 1 rejection above), wherein a first ray trace miss of any of the set of conservative candidate nodes of the low-resolution BVH corresponds with a second ray trace miss of every internal node of the full-resolution BVH (Doyle; [0356] reciting “The traversal shader, intersection shader and outer stack handler are all spawned by the ray-BVH intersection circuitry 4005. The traversal shader allocates on the call stack 4405 before initiating a new inner traversal for the second level BVH. The outer stack handler is a shader that is responsible for updating the hit information and resuming any pending inner traversal tasks. The outer stack handler is also responsible for spawning hit or miss shaders when traversal is complete. Traversal is complete when there are no pending inner traversal queries to spawn. When traversal is complete and an intersection is found, a hit shader is spawned; otherwise a miss shader is spawned.”).
12 Regarding claim 6, Liktor in view of Doyle teaches the apparatus of claim 1 (see claim 1 rejection above), wherein a first ray trace miss of any internal node of the low-resolution BVH corresponds with a second ray trace miss of every internal node of the full-resolution BVH (Liktor; [0047] reciting “Full clusters that exactly match the line size can be moved to the beginning of the AC. If the line size is known, this optimization may yield a significant reduction in the cache misses in some embodiments.”).
13 Regarding claim 7, Liktor in view of Doyle teaches the apparatus of claim 1 (see claim 1 rejection above), wherein the internal node of the full-resolution BVH that corresponds with the conservative candidate node comprises a set of child primitives that are constrained by an axis-aligned bounding box (AABB) of the conservative candidate node ([0368] reciting “Each inner node 4610 corresponds to a bounding volume which is typically an axis-aligned bounding box. In one embodiment, a in a first sequence of operations, the node refitting circuitry 4509 iterates over all leaf nodes 4620 which point to leaf data and updates their bounding volume. In a second sequence of operations, the node refitting circuitry 4509 iterates in reverse order over the inner node array. In the illustrated example, this means the order C, E, D, B, and A.”; [0388] reciting “Any node in the upper BVH level would not need an immediate bounding box update for expanding. Thus, the BVH nodes are saved for traversal without further refitting. However, the BVH tree quality may deteriorate over time since the upper level bounding box may no longer tightly cover its child nodes.”).
14 Regarding claim 8, Liktor teaches an apparatus for graphics processing, comprising: a memory; and a processor coupled to the memory and, based at least in part on information stored in the memory, the processor is configured to ([0025] reciting “A cache line aware reordering method considers bounding volume (BV) memory footprints that are comparably small to quantized Bounding Volume Hierarchy (BVH) nodes.”; [0059] reciting “The L1 caches fetch missing cache lines from a higher latency L2 cache 48, which is banked and shared across all traversal clusters. This L2 cache may be shared with last level cache on current processor graphics, which may cache nodes as well as shading data.”):
obtain a first indication of a full-resolution bounding volume hierarchy (BVH) comprising a set of primitives ([0039] reciting “An example algorithm shown in FIG. 2 takes as its input the conventional BVH T, using e.g. depth-first layout, given the desired child (small) pointer size is n bits.”; [0056] reciting “Leaf Unit (LU) 34 fetches and processes leaf as well as glue nodes. It includes a node fetch and a dispatch stage. The node fetch stage is identical to the TU. The node data includes a bit flag which indicates if a primitive leaf or a glue node was fetched. For primitive leaves, the LU issues a request to the PU 36 for triangle intersection. If a glue node is received, the root offset of the new address cluster is sent back to the TU that initiated the request.”; [0150] reciting “One example embodiment may be a method comprising implementing reduced precision ray traversal for a bounding volume-node hierarchy in a graphics processor, using address clustering as one clustering level, and using cache clustering as another clustering level. The method may also include generating low resolution child pointers between clustered nodes… The method may also include only loading glue nodes when crossing a border between clusters. The method may also include merging child nodes in a cluster until the cluster is full.”);
obtain a set of primitive clusters and a set of representative primitives, wherein each of the set of primitive clusters is associated with a representative primitive of the set of representative primitives, wherein each primitive of the set of primitive clusters comprises a primitive from the set of primitives ([0056] reciting “For primitive leaves, the LU issues a request to the PU 36 for triangle intersection. If a glue node is received, the root offset of the new address cluster is sent back to the TU that initiated the request.”; [0057] reciting “Primitive Unit (PU) 36 performs the ray-triangle intersection tests 42. This can be an arbitrary full-floating point precision algorithm. The vertex indices and position data for this test are fetched by triangle fetch units 38 using 4 successive 12-byte accesses, backed by a separate L1 cache 40. The received vertex positions go through a pipelined triangle test unit 42, which sends the intersection results back to the requesting TU.”);
generate a low-resolution BVH based on the set of representative primitives ([0150] reciting “One example embodiment may be a method comprising implementing reduced precision ray traversal for a bounding volume-node hierarchy in a graphics processor, using address clustering as one clustering level, and using cache clustering as another clustering level. The method may also include generating low resolution child pointers between clustered nodes.”);
associate each conservative internal node of the low-resolution BVH to a corresponding internal node of the full-resolution BVH based on the corresponding primitive cluster of the set of primitive clusters ([0040] reciting “This is followed by a conventional cache-aware node-reordering within each address cluster, as indicated at step 3. An address cluster with a continuous range of memory and a cache cluster within a cache line size are shown at step 3 in FIG. 2.”); and
15 Liktor does not explicitly teach to assign an axis-aligned bounding box (AABB) to each conservative internal node associated with each representative primitive of the set of representative primitives based on a corresponding primitive cluster of the set of primitive clusters; … and output a second indication of the low-resolution BVH and a third indication of an association of each conservative internal node of the low-resolution BVH to the corresponding internal node of the full-resolution BVH.
16 Doyle teaches to assign an axis-aligned bounding box (AABB) to each conservative internal node associated with each representative primitive of the set of representative primitives based on a corresponding primitive cluster of the set of primitive clusters ([0368] reciting “Each inner node 4610 corresponds to a bounding volume which is typically an axis-aligned bounding box. In one embodiment, a in a first sequence of operations, the node refitting circuitry 4509 iterates over all leaf nodes 4620 which point to leaf data and updates their bounding volume. In a second sequence of operations, the node refitting circuitry 4509 iterates in reverse order over the inner node array. In the illustrated example, this means the order C, E, D, B, and A.”; [0294] reciting “In general, the various cores 3150, 3140, 3130 may support a ray tracing instruction set that includes instructions/functions for ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions.”); … and
output a second indication of the low-resolution BVH and a third indication of an association of each conservative internal node of the low-resolution BVH to the corresponding internal node of the full-resolution BVH ([0290] reciting “In one embodiment, each ray tracing core 3150 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, in one embodiment, the multi-core group 3100A can simply launch a ray probe, and the ray tracing cores 3150 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc) to the thread context.”).
17 It would have been obvious to one with ordinary skill before the effective filing date of the claimed invention, to have modified the method (taught by Liktor) to incorporate the teachings of Doyle to provide a method to assign an AABB for each of the conservative nodes associated with primitives provided by Liktor. Doing so would allow all inner-nodes to be correctly updated when iterating over an inner node array as stated by Doyle ([0368] recited).
18 Regarding claim 9, Liktor in view of Doyle teaches the apparatus of claim 8 (see claim 8 rejection above), wherein, to assign the AABB to each conservative internal node associated with the representative primitive based on the corresponding primitive cluster of the set of primitive clusters (Doyle; [0299] reciting “Per-primitive Bounding box Construction—This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).”), the processor is configured to:
assign the AABB to each conservative internal node such that the assigned AABB encompasses each primitive of the corresponding primitive cluster (Doyle; [0372] reciting “For example, each primitive may be surrounded by its own bounding box to create the leaf bounding boxes which are then merged to form the first level of inner nodes.”).
19 Regarding claim 10, Liktor in view of Doyle teaches the apparatus of claim 8 (see claim 8 rejection above), wherein, to obtain the set of primitive clusters and the set of representative primitives, the processor is configured to: obtain a fourth indication of a space-fit sorted array of the set of primitives; cluster adjacent primitives of the space-fit sorted array into the set of primitive clusters; and select the representative primitive for each primitive cluster of the set of primitive clusters (Doyle; [Abstract] reciting “…a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes…”; [0355] reciting “As illustrated in FIG. 44, before inner traversal is spawned, space is allocated on the call stack 4405 for the fixed-function circuitry 4010 to store the truncated inner stack 4410. Offsets 4403-4404 to the top of the call stack and the inner stack are maintained in the traversal state 4400 which is also stored in memory 2511. The traversal state 4400 also includes the ray in world space 4401 and object space 4402 as well as hit information for the closest intersecting primitive.”).
20 Regarding claim 13, Liktor in view of Doyle teaches the apparatus of claim 8 (see claim 8 rejection above), wherein the corresponding internal node of the full-resolution BVH that corresponds with each conservative candidate node comprises a set of child primitives that are constrained by an AABB of the conservative candidate node (Doyle; [0368] reciting “Each inner node 4610 corresponds to a bounding volume which is typically an axis-aligned bounding box. In one embodiment, a in a first sequence of operations, the node refitting circuitry 4509 iterates over all leaf nodes 4620 which point to leaf data and updates their bounding volume. In a second sequence of operations, the node refitting circuitry 4509 iterates in reverse order over the inner node array. In the illustrated example, this means the order C, E, D, B, and A. In one embodiment, the node refitting circuitry 4509 computes the bounding volume for each inner node 4610 in this order by merging the bounding volumes of its children. Because of the depth first order in which the nodes are stored in memory 4698, all inner-nodes 4610 will be correctly updated when iterating over the inner node array in the refit direction indicated in FIG. 46B.”).
21 Regarding claim 14, Liktor in view of Doyle teaches the apparatus of claim 8, wherein the third indication of the association of each conservative internal node of the low-resolution BVH to the corresponding internal node of the full-resolution BVH comprises an index comprising a first set of identifiers for a set of conservative internal nodes of the low-resolution BVH and a second set of identifiers for a set of corresponding internal nodes of the full-resolution BVH (Doyle; [0126] reciting “The native instructions available in the 64-bit format 730 vary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field 713. The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format 710.”).
22 Claim 15 has similar limitations as of claim 1, therefore it is rejected under the same rationale as claim 1.
23 Claim 16 has similar limitations as of claim 2, therefore it is rejected under the same rationale as claim 2.
24 Claim 17 has similar limitations as of claim 3, therefore it is rejected under the same rationale as claim 3.
25 Claim 18 has similar limitations as of claim 4, therefore it is rejected under the same rationale as claim 4.
26 Claim 19 has similar limitations as of claim 5, therefore it is rejected under the same rationale as claim 5.
27 Claim 20 has similar limitations as of claim 6, therefore it is rejected under the same rationale as claim 6.
28 Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liktor et al. (US 20170287100 A1) in view of Doyle et al (US 20200211147 A1) as of claims 8 and 10, further in view of Garanzha et al. (US 20130033507 A1).
29 Regarding claim 11, Liktor in view of Doyle teaches the apparatus of claim 10 (see claims 8 and 10 rejections above), wherein, to obtain the second indication of the space-fit sorted array of the set of primitives, the processor is configured to (see claims 8 and 10 rejections above), but does not explicitly teach to sort the set of primitives based on a Morton space-filling curve.
30 Garanzha teaches to sort the set of primitives based on a Morton space-filling curve ([0054] reciting “For example, a 3D extent of a scene may be discretized using n bits per dimension, and each point may be assigned a linear coordinate along a space-filling Morton curve of order n (which may be computed by interleaving the binary digits of the discretized coordinates). In another embodiment, primitives may then be sorted according to the Morton code of their centroid. In still another embodiment, the hierarchy may be built by grouping the primitives in clusters with the same 3n bit code, then grouping the clusters with the same 3(n-1) high order bits, and so on, until a complete tree is built. In yet another embodiment, the 3m high order bits of a Morton code may identify the parent voxel in a coarse grid with 2.sup.m divisions per side, such that this process may correspond to splitting the primitives recursively in the spatial middle, from top to bottom.”).
31 It would have been obvious to one with ordinary skill before the effective filing date of the claimed invention, to have modified the method (taught by Liktor in view of Doyle) to incorporate the teachings of Garanzha to provide a method that incorporates the Morton space-filling curve for sorting the primitives and the space-filled arrays provided by the teachings of Liktor in view of Doyle. Doing so would allow each thread to be allowed to find its own split plane as stated by Garanzha ([0030] recited).
32 Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liktor et al. (US 20170287100 A1) in view of Doyle et al (US 20200211147 A1) as of claims 8 and 10, further in view of Havran et al. (US 20170200303 A1).
33 Regarding claim 12, Liktor in view of Doyle teaches the apparatus of claim 10 (see claims 8 and 10 rejections above), wherein, to select the representative primitive for each primitive cluster of the set of primitive clusters, the processor is configured to (see claims 8 and 10 rejections above), but does not explicitly teach to select the representative primitive based on a largest comparative diagonal size.
34 Havran teaches to select the representative primitive based on a largest comparative diagonal size ([0016] reciting “The processor may be further configured to classify the primitives in the 3D space into first bounding boxes comprising primitives having a size greater than a critical value and second bounding boxes comprising primitives having a size less than the critical value. The processor may be further configured to determine sizes of the first or second, or both, bounding boxes and indicate the sizes of the primitives based on the sizes of the first or second, or both, bounding boxes. The processor may be further configured to calculate diagonal lengths of the first or second, or both, bounding boxes and determine the sizes of the first or second, or both, bounding boxes based on the diagonal lengths.”; [0052] reciting “The acceleration structure generating apparatus 200 may generate various types of acceleration structures. For example, an acceleration structure may be generated by splitting 3D space in a hierarchical tree structure, and the acceleration structure generating apparatus 200 may generate a structure indicating a relationship between objects in 3D space by applying BVH or KD tree. The acceleration structure generating apparatus 200 may determine a maximum number of primitives of a leaf node and a depth of tree and generate an acceleration structure based on the determined maximum number and the determined depth of tree.”; [0084] reciting “For example, the apparatus 200 for generating an acceleration structure may calculate a diagonal length of the bounding box. The apparatus 200 for generating an acceleration structure may determine the size of the bounding box based on the diagonal length thereof.”).
35 It would have been obvious to one with ordinary skill before the effective filing date of the claimed invention, to have modified the method (taught by Liktor in view of Doyle) to incorporate the teachings of Havran to provide a method that can select a primitive based on the maximum diagonal size, with the primitives being provided by the teachings of Liktor in view of Doyle. Doing so would determine the size of the bounding box as stated by Havran ([0084] recited).
Conclusion
36 Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHNNY TRAN LE whose telephone number is (571)272-5680. The examiner can normally be reached Mon-Thu: 7:30am-5pm; First Fridays Off; Second Fridays: 7:30am-4pm.
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/JOHNNY T LE/ Examiner, Art Unit 2614
/KENT W CHANG/ Supervisory Patent Examiner, Art Unit 2614