Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
This FINAL action is in response to Applicant’s amendment of 17 March 2028. Claims 1-20 are pending and have been considered as follows.
Response to Arguments
Applicants’ amendments and/or arguments with respect of the Claim Objections of claim 15 as set forth in the office action of 18 December 2025 have been considered and are persuasive. Therefore, the Claim Objections as set forth in the office action of 18 December 2025 have been withdrawn.
Applicants’ amendments and/or arguments with respect of the rejection of claims 1-20 under 35 USC 102 and 103 as set forth in the office action of 18 December 2025 have been considered-
Regarding Applicant’s arguments associated with the amended limitation “wherein an index associated with the common interlace resource block is configured for each resource pool”, Applicant’s arguments have been considered and are moot because the new ground(s) of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. See 35 USC 103 below.
Regarding Applicant’s arguments associated with the limitation “the set of candidate PSFCH resource blocks including a common interlace resource block and a set of dedicated resource blocks for PSFCH transmissions”, Examiner has carefully considered Applicant’s arguments and respectfully disagrees. Examiner points to at least paragraph [0071] of Liu-1 which teaches that “the mapping may be a one-to-one mapping such that a PSSCH communication is mapped to the same RB-sets and a same PSFCH interlace in the RB-sets corresponding to the PSSCH interlace.” This “same PSFCH interlace” is a common interlace resource block that is used across the mapping. Examiner also points to paragraph [0107] which teaches that “the indexes of the PSSCH interlaces 904.sub.i may be the same as the indexes of the PSFCH interlaces 910.sub.k”, which explicitly teaching that the common interlace resource block (the PSFCH interlace) is associated with an index (k).
Claim Objections
Claim 3 is objected to because of the following informalities: Claim 3 should be amended to recite “a total number of interlaces for the candidate resource blocks for …” since such limitation is previously recited. Appropriate correction is required.
Claim 5 is objected to because of the following informalities: Claim 5 should be amended to recite “multiplexing a hybrid automatic repeat request acknowledgement …” for grammatical correctness. Appropriate correction is required.
Claim 20 is objected to because of the following informalities: Claim 20 should be amended to recite “the set of dedicated resource blocks [[is]] are indexed …” for grammatical correctness. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu-1 (US 20240048329 A1); hereinafter Liu-1, in view of Liu-2 (US 20230371089 A1); hereinafter Liu-2.
Regarding claim 1, Liu-1 teaches one or more processors configured for wireless communication by performing operations comprising: receiving configuration data specifying a mapping for sidelink resource blocks to respective candidate physical sidelink feedback channel (PSFCH) resource blocks, the mapping specifying, for a sidelink transmission, a set of candidate PSFCH resource blocks, the set of candidate PSFCH resource blocks including a common interlace resource block and a set of dedicated resource blocks for PSFCH transmissions ([0070-0071], [0106-0107], and [0109] The sidelink communication module 408 may be configured to receive a sidelink resource configuration from a BS (e.g., the BSs 105 and/or 205) for sidelink communication and communicate sidelink data (e.g., PSSCH data), sidelink control information (e.g., PSSCH control information), and/or sidelink feedback (e.g., PSFCH information) with another UE based on the sidelink resource configuration. [0071] The sidelink communication module 408 may be configured to map the PSSCH resources of a wideband PSSCH communication to one or more PSFCH interlaces in one or more RB-sets based on the mapping. In some aspects, the mapping may be a one-to-one mapping such that a PSSCH communication is mapped to the same RB-sets and a same PSFCH interlace in the RB-sets corresponding to the PSSCH interlace. In another aspect, the mapping may include a mapping to one or more cyclic shift pair sets); encoding the sidelink transmission ([0099] In this regard, the first UE and/or the second UE may generate a CP-OFDM transmission signal by mapping encoded PSSCH control information and the encoded PSSCH data onto subcarriers (e.g., the subcarriers 612) of corresponding RBs of the frequency interlace 608.sub.I(0) and performing an inverse fast Fourier transform (IFFT). Liu-1 teaches encoding a sidelink transmission and describes generating a sidelink transmission by applying the mapping to the PSSCH resources and performing the necessary signal-domain processing (e.g., mapping to subcarriers and applying an IFFT)); and decoding, based on the mapping, a PSFCH transmission, the PSFCH transmission being transmitted in a PFSCH slot using a PSFCH resource block of the set of candidate PSFCH resource blocks ([0071] The sidelink communication module 408 may be configured to map the PSSCH resources of a wideband PSSCH communication to one or more PSFCH interlaces in one or more RB-sets based on the mapping. [0073] The transceiver 410 may provide the demodulated and decoded data (e.g., the frequency interlace configuration, PSSCH data, PSCCH control information, and/or PSFCH information) to the sidelink communication module 408 for processing. Liu-1 teaches how PSFCH transmissions are allocated within the RB-sets and the decoding of the PSFCH transmission using the mapped PSFCH resource block(s) defined by the sidelink resource configuration), but does not explicitly teach wherein an index associated with the common interlace resource block is configured for each resource pool.
Liu-2 in the same field of wireless communications, teaches wherein an index associated with the common interlace resource block is configured for each resource pool (See at least [0104-0105] As shown in Equation 2, NCS PSFCH may be a quantity of cyclic shift pairs, configured per resource pool (where a pair is for indicating either ACK or NACK, such that one pair is capable of conveying 1 bit of information). Within a PSFCH resource pool, a PSFCH resource may be indexed by PRB index first and by cyclic shift pair index second. [0123] In other words, NPSFCH may be set equal to a quantity of CS pairs, which may be configured per resource pool. As such, if UE 104-b supports two CS pairs, NPSFCH=2. In such aspects, within a PSFCH resource pool, a PSFCH resource 615 may be indexed by RBG index first and by cyclic shift pair index second; Liu-2 teaches that within a PFSCH resource pool, specifically the PRB/RBG index associated with the interlace resource block is set and applied on a per-resource-pool basis).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing, and indexing based on configuration data with Liu-2’s teaching of configuring an index associated with the common interlace resource block on a per-resource-pool basis. The motivation to do so would have been to avoid index collisions between UEs operating in different pools, accurately determine a number or PSFCH resource blocks available for multiplexing and improving resource block allocation.
Regarding claim 2, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 1, wherein the set of candidate PSFCH resource blocks are in a same resource block set (See at least Liu-1 [0071] The sidelink communication module 408 may be configured to map the PSSCH resources of a wideband PSSCH communication to one or more PSFCH interlaces in one or more RB-sets. The mapping may be a one-to-one mapping such that a PSSCH communication is mapped to the same RB-sets and a same PSFCH interlace in the RB-sets corresponding to the PSSCH interlace).
Regarding claim 3, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 1, wherein the mapping specifies, for a resource block set, a total number of interlaces for candidate dedicated resource blocks for the PFSCH transmissions and a total number of resource blocks in each of the interlaces (See at least Liu-1; [0005], [0038] Accordingly, if a wideband PSSCH communication occupies resources in X number of RB-sets, the second UE may be configured with X number of PSFCH resource pools. In some aspects, all PSFCH resource pools may be associated with and/or based on a same interlace of RBs. [0106] Although a single RB-set 902 is shown in FIGS. 9A and 9B, it will be understood that the PSSCH communications 906.sub.i(j) may span more than one RB-set, such as two RB-sets, three RB-sets, four RB-sets, eight RB-sets, and/or any other suitable number of RB-sets. In some aspects, each PSSCH communication 906.sub.i(j) may correspond to one of a plurality of interlaces of RBs 904.sub.i. [0109] If the PSSCH resources 930 include the same number of RB-sets and the same number of interlaces as the PSFCH resources 940, the mapping may include a one-to-one mapping between the PSSCH interlace and RB-set, and the PSFCH interlace in the same RB-set).
Regarding claim 4, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 1, wherein the mapping specifies, for a resource block set, a total number of candidate dedicated resource blocks for the PSFCH transmissions (See at least Liu-1; [0119] Although two RB-sets 1002.sub.k are shown in FIG. 10A, it will be understood that the PSSCH resources 1030 may span more than two RB-sets, such as three RB-sets, four RB-sets, eight RB-sets, and/or any other suitable number of RB-sets).
Regarding claim 5, Liu-1 teaches the one or more processors of claim 1, but does not explicitly teach wherein a number of dedicated resource blocks available for multiplexing a hybrid automatic repeat request acknowledgement HARQ-ACK for is determined as Msubch,slot,reTxPSFCH=MPRB,setPSFCHNsubch⋅NPSSCHPSFCH⋅NreTx, where M,PSFCH,PRBset is a total number of candidate resource blocks in a resource set, Nsubch is the number of PSFCH sub-channels in the resource block set, NPSSCHPSFCH is a periodicity of the PSFCH transmissions having values of {1,2,4}, and NreTx is a number of candidate PSFCH occasions having values of {1,2,3,4}.
Liu-2 in the same field of wireless communications, teaches wherein a number of dedicated resource blocks available for multiplexing a hybrid automatic repeat request acknowledgement HARQ-ACK for is determined as Msubch,slot,reTxPSFCH=MPRB,setPSFCHNsubch⋅NPSSCHPSFCH⋅NreTx ([0118]
PNG
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), where M,PSFCH,PRBset is a total number of candidate resource blocks in a resource set (See at least [0118-0120] where Msubch,slot PSFCH is defined in accordance with Equation 4:Msubch,slotPSFCH=MPRB,setPSFCHX×NPSSCHPSFCH×Nsubch(4)where MPRB,set PSFCH represents the number of the set of PRBs 535 that are allocated for a PSFCH in a slot.
), where Nsubch is the number of PSFCH sub-channels in the resource block set ([0104] this quantity may be split between NPSSCH PSFCH (a quantity of PSSCH slots corresponding to a PSFCH slot) N.sub.subch (a quantity of sub-channels for a resource pool)), NPSSCHPSFCH is a periodicity of the PSFCH transmissions having values of {1,2,4} ([0104] For example, a periodPSFCHresource parameter may indicate or define a period in slots for a PSFCH transmission in a resource pool. The supported periods may be 0, 1, 2, or 4 (where 0 means that there is no PSFCH available), among other examples), and NreTx is a number of candidate PSFCH occasions having values of {1,2,3,4} ([0114] Generally, UE 104-b may use X PRBs 535 for the feedback message 525, where X may be configured (such as via RRC signaling) per resource pool or may be preconfigured (such as hardcoded or defined in a specification) at UE 104-b. X may be 2, 4, or other values).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing, and indexing based on configuration data with Liu-2’s PSFCH resource-block calculation and to incorporate the parameter corresponding to the number of candidate PSFCH occasions, as claimed, in view of the secondary reference’s teaching of selecting a quantity of PFSCH PRBs per feedback occasion X. The motivation to do so would have been to accurately determine a number or PSFCH resource blocks available for multiplexing and improving resource block allocation.
Regarding claim 6, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 1, wherein the set of dedicated resource blocks is indexed, based on the mapping of the configuration data (See at least Liu-1; [0071] The sidelink communication module 408 may be configured to map the PSSCH resources of a wideband PSSCH communication to one or more PSFCH interlaces in one or more RB-sets based on the mapping. [0088] Each RB 610 may span about twelve contiguous subcarriers 612 in frequency and a time period 614. The subcarriers 612 are indexed from 0 to 11).
Regarding claim 7, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 6, wherein the set of dedicated resource blocks is indexed in a first interlace before being indexed in a second interlace (See at least Liu-1; [0106] The PSSCH resources 930 include a plurality of interlaces 904.sub.i in one or more RB-sets 902. Although a single RB-set 902 is shown in FIGS. 9A and 9B, it will be understood that the PSSCH communications 906.sub.i(j) may span more than one RB-set, such as two RB-sets, three RB-sets, four RB-sets, eight RB-sets, and/or any other suitable number of RB-sets. In some aspects, each PSSCH communication 906.sub.i(j) may correspond to one of a plurality of interlaces of RBs 904.sub.i. [0109] The mapping may include a one-to-one mapping between the PSSCH interlace and RB-set, and the PSFCH interlace in the same RB-set).
Regarding claim 8, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 6, wherein the set of dedicated resource blocks is indexed in a frequency domain (See at least Liu-1; [0033] Each frequency domain PRB interlace may include a set of PRBs uniformly spaced in the shared radio frequency band. [0106] Although a single RB-set 902 is shown in FIGS. 9A and 9B, it will be understood that the PSSCH communications 906.sub.i(j) may span more than one RB-set, such as two RB-sets, three RB-sets, four RB-sets, eight RB-sets, and/or any other suitable number of RB-sets).
Regarding claim 19, Liu-1 teaches an apparatus comprising one or more processors configured for wireless communication by performing operations comprising: receiving configuration data specifying a mapping for sidelink resource blocks to respective candidate physical sidelink feedback channel (PSFCH) resource blocks, the mapping specifying, for a sidelink transmission, a set of candidate PSFCH resource blocks, the set of candidate PSFCH resource blocks including a common interlace resource block and a set of dedicated resource blocks for PSFCH transmissions([0070] The sidelink communication module 408 may be configured to receive a sidelink resource configuration from a BS (e.g., the BSs 105 and/or 205) for sidelink communication and communicate sidelink data (e.g., PSSCH data), sidelink control information (e.g., PSSCH control information), and/or sidelink feedback (e.g., PSFCH information) with another UE based on the sidelink resource configuration. [0071] The sidelink communication module 408 may be configured to map the PSSCH resources of a wideband PSSCH communication to one or more PSFCH interlaces in one or more RB-sets based on the mapping. In some aspects, the mapping may be a one-to-one mapping such that a PSSCH communication is mapped to the same RB-sets and a same PSFCH interlace in the RB-sets corresponding to the PSSCH interlace. In another aspect, the mapping may include a mapping to one or more cyclic shift pair sets); encoding the sidelink transmission ([0099] In this regard, the first UE and/or the second UE may generate a CP-OFDM transmission signal by mapping encoded PSSCH control information and the encoded PSSCH data onto subcarriers (e.g., the subcarriers 612) of corresponding RBs of the frequency interlace 608.sub.I(0) and performing an inverse fast Fourier transform (IFFT) Liu-1 teaches encoding a sidelink transmission and describes generating a sidelink transmission by applying the mapping to the PSSCH resources and performing the necessary signal-domain processing (e.g., mapping to subcarriers and applying an IFFT)); and decoding, based on the mapping, a PSFCH transmission, the PSFCH transmission being transmitted in a PFSCH slot using a PSFCH resource block of the set of candidate PSFCH resource blocks ([0071] The sidelink communication module 408 may be configured to map the PSSCH resources of a wideband PSSCH communication to one or more PSFCH interlaces in one or more RB-sets based on the mapping. [0073] The transceiver 410 may provide the demodulated and decoded data (e.g., the frequency interlace configuration, PSSCH data, PSCCH control information, and/or PSFCH information) to the sidelink communication module 408 for processing. Liu-1 teaches how PSFCH transmissions are allocated within the RB-sets and the decoding of the PSFCH transmission using the mapped PSFCH resource block(s) defined by the sidelink resource configuration), but does not explicitly teach wherein an index associated with the common interlace resource block is configured for each resource pool.
Liu-2 in the same field of wireless communications, teaches wherein an index associated with the common interlace resource block is configured for each resource pool (See at least [0104-0105] As shown in Equation 2, NCS PSFCH may be a quantity of cyclic shift pairs, configured per resource pool (where a pair is for indicating either ACK or NACK, such that one pair is capable of conveying 1 bit of information). Within a PSFCH resource pool, a PSFCH resource may be indexed by PRB index first and by cyclic shift pair index second. [0123] In other words, NPSFCH may be set equal to a quantity of CS pairs, which may be configured per resource pool. As such, if UE 104-b supports two CS pairs, NPSFCH=2. In such aspects, within a PSFCH resource pool, a PSFCH resource 615 may be indexed by RBG index first and by cyclic shift pair index second; Liu-2 teaches that within a PFSCH resource pool, specifically the PRB/RBG index associated with the interlace resource block is set and applied on a per-resource-pool basis).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing, and indexing based on configuration data with Liu-2’s teaching of configuring an index associated with the common interlace resource block on a per-resource-pool basis. The motivation to do so would have been to avoid index collisions between UEs operating in different pools, accurately determine a number or PSFCH resource blocks available for multiplexing and improving resource block allocation.
Regarding claim 20, Liu-1 as modified by Liu-2 teaches the apparatus of claim 19, wherein the set of dedicated resource blocks are indexed based on the mapping of the configuration data (See at least Liu-1; [0104-0106], [0109-0110], [0071] The sidelink communication module 408 may be configured to map the PSSCH resources of a wideband PSSCH communication to one or more PSFCH interlaces in one or more RB-sets based on the mapping. [0088] Each RB 610 may span about twelve contiguous subcarriers 612 in frequency and a time period 614. The subcarriers 612 are indexed from 0 to 11) and wherein the set of dedicated resource blocks is indexed in a first interlace before being indexed in a second interlace (See at least Liu-1; [0106] The PSSCH resources 930 include a plurality of interlaces 904.sub.i in one or more RB-sets 902. Although a single RB-set 902 is shown in FIGS. 9A and 9B, it will be understood that the PSSCH communications 906.sub.i(j) may span more than one RB-set, such as two RB-sets, three RB-sets, four RB-sets, eight RB-sets, and/or any other suitable number of RB-sets. In some aspects, each PSSCH communication 906.sub.i(j) may correspond to one of a plurality of interlaces of RBs 904.sub.i. [0109] The mapping may include a one-to-one mapping between the PSSCH interlace and RB-set, and the PSFCH interlace in the same RB-set).
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu-1 (US 20240048329 A1), in view of Liu-2 (US 20230371089 A1) and further in view of Zhao-1 (WO 2021/037235 A1).
Regarding claim 9, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 1, but does not explicitly teach wherein the set of dedicated resource blocks is allocated to physical sidelink shared channel (PSSCH) slots with a first index, PSFCH sub-channels with a second index, and retransmission instances with a third index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the first index over the PSSCH slots, (ii) the second index over the PSFCH sub- channels, and (iii) the third index over the retransmission instances, and wherein the PSSCH slots, the PSFCH sub-channels, and the retransmission instances are associated with the PSFCH slot.
Zhao-1, in the same field of wireless communications, teaches wherein the set of dedicated resource blocks is allocated to physical sidelink shared channel (PSSCH) slots with a first index, PSFCH sub-channels with a second index, and retransmission instances with a third index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the first index over the PSSCH slots, (ii) the second index over the PSFCH sub- channels, and (iii) the third index over the retransmission instances, and wherein the PSSCH slots, the PSFCH sub-channels, and the retransmission instances are associated with the PSFCH slot (See at least [Page 5, lines 22-28], [Page 5, lines 33-38] In some embodiments, the PSFCH resource sets are allocated to the PSSCH transmission resources comprises that: a PSFCH resource set is allocated to slot i and subchannel j, in an ascending order of i and then in an ascending order of j; wherein i=1, 2, ...N, j=1, 2, ...M, and the PSFCH resource sets are allocated from lower frequency to higher frequency. In some embodiments, the processor 11 or 21 is configured to determine a number of PSFCH resources available for multiplexing hybrid automatic repeat request-acknowledgement (HARQ-ACK) information in the PSFCH transmission).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing, and indexing based on configuration data with Zhao-1’s indexing scheme over PSSCH slots, subchannels, and retransmission instances. The motivation to do so would have been to improve resource allocation efficiency, reduce collision, and ensure systematic mapping.
Regarding claim 10, Liu-1 teaches the one or more processors of claim 1, but does not explicitly teach wherein the set of dedicated resource blocks is allocated to PSSCH slots with a first index, retransmission instances with a third index, and PSFCH sub-channels with a second index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the first index over the PSSCH slots, (ii) the third index over the retransmission instances, and (iii) the second index over the PSFCH sub-channels, and wherein the PSSCH slots, the PSFCH sub-channels, and the retransmission instances are associated with the PSFCH slot.
Zhao-1, in the same field of wireless communications, teaches wherein the set of dedicated resource blocks is allocated to PSSCH slots with a first index, retransmission instances with a third index, and PSFCH sub-channels with a second index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the first index over the PSSCH slots, (ii) the third index over the retransmission instances, and (iii) the second index over the PSFCH sub-channels, and wherein the PSSCH slots, the ([Page 5, lines 33-38] In some embodiments, the PSFCH resource sets are allocated to the PSSCH transmission resources comprises that: a PSFCH resource set is allocated to slot i and subchannel j, in an ascending order of i and then in an ascending order of j; wherein i=1, 2, ...N, j=1, 2, ...M, and the PSFCH resource sets are allocated from lower frequency to higher frequency. In some embodiments, the processor 11 or 21 is configured to determine a number of PSFCH resources available for multiplexing hybrid automatic repeat request-acknowledgement (HARQ-ACK) information in the PSFCH transmission. [Page 6, lines 8-11] In some embodiments, PSFCH transmission resources in a PSFCH resource set are indexed with numbers in an ascending order firstly in the frequency domain, and then in the code domain. In some embodiments, the RX UEs select different resources firstly in the frequency domain for PSFCH transmission and then in a code domain.)
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping and interlacing with Zhao-1’s indexing scheme over PSSCH slots, retransmission, and subchannels instances associated with a PFSCH slot. It would have been obvious to one of the ordinary skill in the art to recognize that the traversal of indexing over slots, retransmission, and subchannel is a routine implementation choice that yields the same allocation result of the PFSCH resource blocks. The motivation to do so would have been to improve resource allocation efficiency, reduce collision, and ensure systematic mapping
Regarding claim 11, Liu-1 teaches the one or more processors of claim 1, but does not explicitly teach wherein the set of dedicated resource blocks is allocated to PSFCH sub-channels with a second index, PSSCH slots with a first index, and retransmission instances with a third index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the second index over the PSFCH sub-channels, (ii) the first index over the PSSCH slots, and (iii) the third index over the retransmission instances, and wherein the PSSCH slots, the PSFCH sub-channels, and the retransmission instances are associated with the PSFCH slot.
Zhao-1, in the same field of wireless communications, teaches wherein the set of dedicated resource blocks is allocated to PSFCH sub-channels with a second index, PSSCH slots with a first index, and retransmission instances with a third index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the second index over the PSFCH sub-channels, (ii) the first index over the PSSCH slots, and (iii) the third index over the retransmission instances, and wherein the PSSCH slots, the PSFCH sub-channels, and the retransmission instances are associated with the PSFCH slot ([Page 6, lines 33-38] In some embodiments, the PSFCH resource sets are allocated to the PSSCH transmission resources comprises that: a PSFCH resource set is allocated to slot i and subchannel j, in an ascending order of i and then in an ascending order of j; wherein i=1, 2, ...N, j=1, 2, ...M, and the PSFCH resource sets are allocated from lower frequency to higher frequency. In some embodiments, the processor 11 or 21 is configured to determine a number of PSFCH resources available for multiplexing hybrid automatic repeat request-acknowledgement (HARQ-ACK) information in the PSFCH transmission. [Page 6, lines 8-11] In some embodiments, PSFCH transmission resources in a PSFCH resource set are indexed with numbers in an ascending order firstly in the frequency domain, and then in the code domain. In some embodiments, the RX UEs select different resources firstly in the frequency domain for PSFCH transmission and then in a code domain.)
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing and indexing based on configuration data with Zhao-1’s indexing scheme over subchannels, slots, and retransmission instances associated with a PFSCH slot. It would have been obvious to one of the ordinary skill in the art to recognize that the traversal of indexing over slots, retransmission, and subchannel is a routine implementation choice that yields the same allocation result of the PFSCH resource blocks. The motivation to do so would have been to improve resource allocation efficiency, reduce collision, and ensure systematic mapping.
Regarding claim 12, Liu-1 teaches the one or more processors of claim 1, but does not explicitly teach wherein the set of dedicated resource blocks is allocated to PSSCH slots with a first index and PSFCH sub-channels with a second index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the first index over the PSSCH slots and (ii) the second index over the PSFCH sub-channels, and wherein the PSSCH slots and the PSFCH sub-channels are associated with the PSFCH slot.
Zhao-1, in the same field of wireless communications, teaches teach wherein the set of dedicated resource blocks is allocated to PSSCH slots with a first index and PSFCH sub-channels with a second index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the first index over the PSSCH slots and (ii) the second index over the PSFCH sub-channels, and wherein the PSSCH slots and the PSFCH sub-channels are associated with the PSFCH slot. ([Page 5, lines 33-38] In some embodiments, the PSFCH resource sets are allocated to the PSSCH transmission resources comprises that: a PSFCH resource set is allocated to slot i and subchannel j, in an ascending order of i and then in an ascending order of j; wherein i=1, 2, ...N, j=1, 2, ...M, and the PSFCH resource sets are allocated from lower frequency to higher frequency. In some embodiments, the processor 11 or 21 is configured to determine a number of PSFCH resources available for multiplexing hybrid automatic repeat request-acknowledgement (HARQ-ACK) information in the PSFCH transmission.)
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing and indexing based on configuration data with Zhao-1’s indexing scheme over PSSCH slots and subchannels. The motivation to do so would have been to improve resource allocation efficiency, reduce collision, and ensure systematic mapping.
Regarding claim 13, Liu-1 teaches the one or more processors of claim 1, but does not explicitly teach wherein the set of dedicated resource blocks is allocated to PSFCH sub-channels with a second index and PSSCH slots with a first index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the second index over the PSFCH sub-channels and (ii) the first index over the PSSCH slots, and wherein the PSSCH slots and the PSFCH sub-channels are associated with the PSFCH slot.
Zhao-1, in the same field of wireless communications, teaches wherein the set of dedicated resource blocks is allocated to PSFCH sub-channels with a second index and PSSCH slots with a first index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the second index over the PSFCH sub-channels and (ii) the first index over the PSSCH slots, and wherein the PSSCH slots and the PSFCH sub-channels are associated with the PSFCH slot.
([Page 5, lines 33-38] In some embodiments, the PSFCH resource sets are allocated to the PSSCH transmission resources comprises that: a PSFCH resource set is allocated to slot i and subchannel j, in an ascending order of i and then in an ascending order of j; wherein i=1, 2, ...N, j=1, 2, ...M, and the PSFCH resource sets are allocated from lower frequency to higher frequency. In some embodiments, the processor 11 or 21 is configured to determine a number of PSFCH resources available for multiplexing hybrid automatic repeat request-acknowledgement (HARQ-ACK) information in the PSFCH transmission.)
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing and indexing based on configuration data with Zhao-1’s indexing scheme over subchannels and PSSCH slots. It would have been obvious to one of the ordinary skill in the art to recognize that the traversal of indexing subchannels and PSSCH slots is a routine implementation choice that yields the same the same allocation result of the PFSCH resource block. The motivation to do so would have been to improve resource allocation efficiency, reduce collision, and ensure systematic mapping.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu-1 (US 20240048329 A1); herein after Liu-1, in view of Lin (WO 2021/098864 A1); hereinafter Lin.
Regarding claim 14, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 1, but does not explicitly teach wherein a number of PSFCH resources available for multiplexing HARQ-ACK in the PSFCH transmission is determined based on a resource block index and a cyclic shift pair index.
Lin, in the same field of wireless communications, teaches wherein a number of PSFCH resources available for multiplexing HARQ-ACK in the PSFCH transmission is determined based on a resource block index and a cyclic shift pair index ([Page 4, lines 18-28 ]
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; Lin describes the number of PSFCH resources available for multiplexing is based on the PRB index from the PRBS, and the cyclic shift pair index from the cyclic shift pairs).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing and indexing based on configuration data with Lin’s teachings of determining a number of PSFCH resources available based on a resource block index and a cyclic shift pair index. The motivation to do so would have been to improve resource allocation efficiency, reduce collision, and ensure multiplexing efficiency.
Regarding claim 15, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 14, but does not explicitly teach wherein the PSFCH resources are indexed first in ascending order based on the resource block index and second in ascending order based on the cyclic shift pair index.
Lin, in the same field of wireless communications, teaches wherein the PSFCH resources are indexed first in ascending order based on the resource block index and second in ascending order based on the cyclic shift pair index ([Page 3, lines 26-28]
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; Lin teaches the PSFCH resources are first indexed according in ascending order of the PRB index from the PRBs, then in ascending order based on the cyclic shift pair index from the cyclic shift pairs).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing and indexing based on configuration data with Lin’s teachings of indexing the PSFCH resource blocks first in ascending order and then indexing the cyclic shift pairs in ascending order. The motivation to do so would have been to improve allocation efficiency, reduce collision, and improved compatibility with sidelink configurations.
Regarding claim 16, Liu-1 as modified by Liu-2 teaches the one or more processors of claim 14, but does not explicitly teach wherein the PSFCH resources are indexed first in ascending order based on the cyclic shift pair index and second in ascending order based on the resource block index.
Lin, in the same field of wireless communications, teaches wherein the PSFCH resources are indexed first in ascending order based on the cyclic shift pair index and second in ascending order based on the resource block index ([Page 3, lines 26-28]
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;Lin teaches the PSFCH resources are first indexed according in ascending order of the PRB index from the PRBs, then in ascending order based on the cyclic shift pair index from the cyclic shift pairs).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing and indexing based on configuration data with Lin’s teachings of indexing the PSFCH resource blocks first in ascending order and then indexing the cyclic shift pairs in ascending order. The motivation to do so would have been to improve allocation efficiency, reduce collision, and improved compatibility with sidelink configurations.
Claim Rejections - 35 USC § 103
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu-1 (US 20240048329 A1); hereinafter Liu-1, in view of Zhao-2 (US20220110097A1); hereinafter Zhao-2.
Regarding claim 17, Liu-1 as modified Liu-2 teaches the one or more processors of claim 1, but does not explicitly teach wherein the set of dedicated resource blocks is allocated to PSSCH slots with a first index, PSFCH sub-channels with a second index, and RB sets with a third index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the first index over the PSSCH slots, (ii) the second index over the PSFCH sub- channels, and (iii) the third index over the RB sets, and wherein the PSSCH slots, the PSFCH sub-channels, and the RB sets are associated with the PSFCH slot.
Zhao-2, in the same field of wireless communications, teaches wherein the set of dedicated resource blocks is allocated to PSSCH slots with a first index, PSFCH sub-channels with a second index, and RB sets with a third index, wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the first index over the PSSCH slots, (ii) the second index over the PSFCH sub- channels, and (iii) the third index over the RB sets, and wherein the PSSCH slots, the PSFCH sub-channels, and the RB sets are associated with the PSFCH slot ([0059] In some embodiments, the PSFCH resource sets are allocated to the PSSCH transmission resources comprises that: a PSFCH resource set is allocated to slot i and subchannel j, in an ascending order of i and then in an ascending order of j; wherein i=1, 2, . . . N, j=1, 2, . . . M, and the PSFCH resource sets are allocated from lower frequency to higher frequency.
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).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing, and indexing based on configuration data with Zhao-2’s indexing scheme over the allocation of incrementing the index of PSSCH slots “i”, and then subchannels “j”, and the PFSCH resource block sets. The motivation to do so would have been to improve resource allocation efficiency, reduce collision, and ensure systematic mapping.
Regarding claim 18, Liu-1 teaches the one or more processors of claim 1, but does not explicitly teach wherein the set of dedicated resource blocks are allocated to PSFCH sub-channels with a second index, RB sets with a third index, and PSSCH slots with a first index, and wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the second index over the PSFCH sub-channels, (ii) the third index over the RB sets, and (iii) the first index over the PSSCH slots, and wherein the PSSCH slots, the PSFCH sub-channels, and the RB sets are associated with the PSFCH slot.
Zhao-2, in the same field of wireless communications, teaches wherein the set of dedicated resource blocks are allocated to PSFCH sub-channels with a second index, RB sets with a third index, and PSSCH slots with a first index, and wherein the allocation of the set of dedicated resource blocks comprises sequentially incrementing (i) the second index over the PSFCH sub-channels, (ii) the third index over the RB sets, and (iii) the first index over the PSSCH slots, and wherein the PSSCH slots, the PSFCH sub-channels, and the RB sets are associated with the PSFCH slot ([0081] In determining PSFCH candidate resources for a PSFCH format from the starting sub-channel index and the slot index used for the corresponding PSSCH for actual transmission, within the set of PRBs (pre-)configured for the actual PSFCH resources, the first Z PRBs are associated with the first sub-channel in the first slot associated with the PSFCH slot, the second Z PRBs are associated with the first sub-channel in the second slot associated with the PSFCH slot, and so on).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to combine Liu-1’s PSSCH to PSFCH mapping, interlacing, and indexing based on configuration data with Zhao-2’s indexing scheme over the allocation of incrementing the index of the first subchannel, then PRBS, and then associated with the slot associated with the PFSCH slot. The motivation to do so would have been to improve resource allocation efficiency, reduce collision, and ensure systematic mapping.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LABIBAH I. ALI whose telephone number is (571)272-6738. The examiner can normally be reached M-F 8:00-5:00.
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/LABIBAH ILMA ALI/Examiner, Art Unit 3667
/SAHAR MOTAZEDI/Primary Examiner, Art Unit 3667
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