DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC PATTERN DISPOSED BETWEEN CONDUCTIVE PATTERN AND GATE ELECTRODE
Claim Objections
Claim 12 is objected to because of the following informalities: “a lower surface of the ferroelectric pattern….an upper surface of the ferroelectric pattern” should be changed to “the lower surface of the ferroelectric pattern….the upper surface of the ferroelectric pattern”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation “at each of the different levels along the first direction, a thickness of the conductive pattern in the first direction and a thickness of the gate electrode in the first direction” would render the claim indefinite due to an incomplete sentence.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11, 13, and 16-17 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Heo et al. (US 2024/0008289 A1; hereinafter “Heo”).
Regarding claim 11, referring to Figs. 3-4, Heo teaches a semiconductor device comprising: a substrate (201) (paragraphs 52-54); a gate stacked structure (a structure including 220 and 211) including a plurality of interlayer insulating layers (211) and a plurality of gate electrodes (220) alternately stacked on the substrate (paragraphs 59-61); a channel structure (250) extending along a first direction (a z-direction) through the gate stacked structure and connected to the substrate (paragraphs 72-73); a plurality of conductive patterns (240) surrounding the channel structure and spaced apart from each other at different levels along the first direction (paragraphs 66-67); and a plurality of ferroelectric patterns (230) spaced apart from each other and each respectively surrounding and in contact with the conductive patterns at each of the different levels along the first direction (paragraphs 62-65), wherein, at each of the different levels along the first direction, a lower surface of the ferroelectric pattern is disposed farther from the substrate than a lower surface of the conductive pattern contacting the ferroelectric pattern (Figs. 3-4), and wherein, at each of the different levels along the first direction, an upper surface of the ferroelectric pattern is disposed closer to the substrate than an upper surface of the conductive pattern contacting the ferroelectric pattern (Figs. 3-4).
Regarding claim 13, Heo teaches wherein, at each of the different levels along the first direction, a thickness of the ferroelectric pattern in the first direction is thinner than a thickness in the first direction of the conductive pattern contacting the ferroelectric pattern (Figs. 3-4).
Regarding claim 16, Heo teaches wherein, at each of the different levels along the first direction, a thickness of the conductive pattern in the first direction and a thickness of the gate electrode in the first direction (Figs. 3-4).
Regarding claim 17, Heo teaches wherein, at each of the different levels along the first direction, a thickness of the conductive pattern in the first direction is thicker than a thickness of the gate electrode in the first direction (Figs. 3-4).
Claims 11, 13, and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Noh et al. (US 2025/0133742 A1; hereinafter “Noh”).
Regarding claim 11, referring to Figs. 2-3, 6, and 8, Noh teaches a semiconductor device comprising: a substrate (110) (paragraphs 37-38); a gate stacked structure (120) including a plurality of interlayer insulating layers (132) and a plurality of gate electrodes (130) alternately stacked on the substrate (paragraphs 49-52); a channel structure (CH) extending along a first direction (a z-direction) through the gate stacked structure and connected to the substrate (paragraphs 55-58); a plurality of conductive patterns (310) surrounding the channel structure and spaced apart from each other at different levels along the first direction (paragraphs 69-73); and a plurality of ferroelectric patterns (320) spaced apart from each other and each respectively surrounding and in contact with the conductive patterns at each of the different levels along the first direction (paragraphs 76-82), wherein, at each of the different levels along the first direction, a lower surface of the ferroelectric pattern is disposed farther from the substrate than a lower surface of the conductive pattern contacting the ferroelectric pattern (Fig. 8), and wherein, at each of the different levels along the first direction, an upper surface of the ferroelectric pattern is disposed closer to the substrate than an upper surface of the conductive pattern contacting the ferroelectric pattern (Fig. 8).
Regarding claim 13, Noh teaches wherein, at each of the different levels along the first direction, a thickness of the ferroelectric pattern in the first direction is thinner than a thickness in the first direction of the conductive pattern contacting the ferroelectric pattern (Fig. 8).
Regarding claim 16, Noh teaches wherein, at each of the different levels along the first direction, a thickness of the conductive pattern in the first direction and a thickness of the gate electrode in the first direction (Fig. 8).
Regarding claim 17, Noh teaches wherein, at each of the different levels along the first direction, a thickness of the conductive pattern in the first direction is thicker than a thickness of the gate electrode in the first direction (Fig. 8).
Allowable Subject Matter
Claims 12 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-10 and 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor device in claim 1 and an electronic system comprising a semiconductor device in claim 18, particularly in combination with the limitation that, at each of the different levels along the first direction, a thickness of the ferroelectric pattern in the first direction is thinner than a thickness in the first direction of the gate electrode.
Pertinent Arts
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (US 2025/0301644 A1, Figs. 8-9), Kim (US 2025/0220905 A1, Figs. 6A-8), Yoon (US 2024/0431114 A1, Fig. 3), and Lee et al. (US 2021/0111190 A1, Figs. 2A-5B) similarly teach the claimed semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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