Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/1/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 5, 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas (US 6,124,818) in view of Venkataraman et al. (US 2011/0012764).
With regard to claim 1
A pipelined analog-to-digital converter comprising (100 Fig. 1): a first stage circuit (302 Fig. 3) configured to perform an analog-to-digital conversion (308 Fig. 3) on an analog input voltage (Vin), generate a first output signal including m higher bits among (MSB and generate a residue voltage (314) corresponding to N lower bits among the (LSB Fig. 3) bits of the digital output code, wherein M and N are natural numbers; and a second stage circuit (350 Fig. 3) including a residue amplifier (212: Col. 2 lines 14-15) configured to sequentially amplify the residue voltage and a comparison voltage to generate an amplified residue voltage and an amplified comparison voltage respectively, wherein the second stage circuit is further configured to perform an analog-to-digital conversion (362 Fig. 3) on the amplified residue voltage based on the amplified comparison voltage to generate a second output signal including the lower bits (LSB Fig. 3) corresponding to the residue voltage.
Thomas fails to teach:
a residue amplifier (212: Col. 2 lines 14-15) configured to sequentially amplify the residue voltage and a comparison voltage (362 Fig. 3) to generate an amplified residue voltage and an amplified comparison voltage respectively.
Venkataraman discloses in Figure 2
A single amplifier (206 Fig. 2) that is configured to sequentially compare a residue voltage (output of 212 Fig. 2) and a comparison voltage output of 214 when S5 is on and S4 is off) (since the amplifier 206 operates as a preamplifier and as the residual gain stage). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use a single amplifier no amplifier both the comparison voltage and the residual input voltage as taught by Venkataraman in the pipeline converter of Thomas for the benefit to minimize the offset of the amplifier and greatly reduce interstage noise contribution.
With regard to claim 2 Thomas fails to teach:
The pipelined analog-to-digital converter of claim 1, wherein the residue amplifier is configured to amplify the residue voltage in a sampling period to generate the amplified residue voltage, and to amplify the comparison voltage in a conversion period following the sampling period to generate the amplified comparison voltage.
Venkataraman teaches
A residue amplifier (206 Fig. 2) that samples the residue voltage when (S2 Fig. 2) is closed) and amplify the comparison voltage when S5 is closed. Therefore, it would have been obvious to any artisan with working knowledge in the art before the effective filing date of the invention to use the teachings of Venkataraman in the pipeline converter of Thomas for the benefit to increase converter accuracy.
With regard to claim 5, Thomas discloses:
The pipelined analog-to-digital converter of claim 1, wherein the residue amplifier comprises an amplifier having an open loop structure (col. 3 lines 32-34).
With regard to claim 13, Thomas discloses:
The pipelined analog-to-digital converter of claim 1, wherein the first stage circuit includes: an analog-to-digital converter (308 Fig. 3) configured to perform the analog-to-digital conversion on the analog input voltage to generate the M higher bits (MSB Fig. 3); a digital-to-analog converter configured to perform a digital-to-analog conversion on the M higher bits to generate a coarse comparison voltage corresponding to the M higher bits (306 CDAC ); and a voltage subtractor (202 Fig. 2) configured to generate the residue voltage by subtracting the coarse comparison voltage from the analog input voltage.
With regard to claim 20, Thomas discloses:
A method of analog-to-digital conversion that comprises: performing an analog-to-digital conversion on an analog input voltage (Vin) to generate a first output signal including M higher bits among (MSB bits Fig.3) bits of a digital output code corresponding to the analog input voltage wherein M and N are natural numbers; generating a residue voltage corresponding to N lower bits (LSB Fig. 3) among the bits (314 Fig. 3) of the digital output code; sequentially amplifying the residue voltage and a comparison voltage using a single residue amplifier to generate an amplified residue voltage and an amplified comparison voltage; and performing an analog-to-digital conversion on the amplified residue voltage (362 Fig. 3) based on the amplified comparison voltage to generate a second output signal including the N lower bits corresponding to the residue voltage (Figs. 1 and/or 4).
Thomas fails to disclose:
sequentially amplifying the residue voltage and a comparison voltage using a single residue amplifier to generate an amplified residue voltage and an amplified comparison voltage.
Venkataraman discloses in Figure 2
A single amplifier (206 Fig. 2) that is configured to sequentially compare a residue voltage (output of 212 Fig. 2) and a comparison voltage output of 214 when S5 is on and S4 is off) (since the amplifier 206 operates as a preamplifier and as the residual gain stage). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use a single amplifier no amplifier both the comparison voltage and the residual input voltage as taught by Venkataraman in the pipeline converter of Thomas for the benefit to minimize the offset of the amplifier and greatly reduce interstage noise contribution.
Allowable Subject Matter
Claims 3-4, 6-12, 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 is allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsukamoto (US 2010/0039303) and Eschauzier (US 2011/0001560) disclose pipeline analog to digital converter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845