DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Miao et al. (A 1GSPS Open-Loop Track and Hold Circuit with 68dB SNDR in 65nm CMOS) (NPL cited by Applicants) in view of Dia et al. (US 2022/0223623 and Dia hereinafter).
Regarding claim 1, Miao discloses a sample and hold circuit [fig. 4] comprising: a first transistor [M1] connected between a first input terminal [drain terminal M1] configured to receive a first input signal [Vin] and a first output terminal [source terminal M1] configured to output a first sampled signal [Von]; a second transistor [M2] connected between a second input terminal [drain terminal M2] configured to receive a second input signal [Vip] and a second output terminal [source terminal M2] configured to output a second sampled signal [Vop]; a first dummy transistor [M2n] provided between the first input terminal and the second output terminal; and a second dummy transistor [M1n] provided between the second input terminal and the first output terminal, wherein a source region and a drain region of the first dummy transistor [source/region M2n] and a source region and a drain region of the first dummy transistor [source/region Mn]. Miao does not explicitly disclose source region and drain region of the first dummy transistor and source region and drain region of the second dummy transistor are electrically disconnected from a metal line connecting the first transistor with the second transistor.
However, Dia disclose [fig. 3B] where in source region [205a] and drain region [205b] of first dummy transistor [T1] and source region [205g] and drain region [205f] of second dummy transistor [T2] are electrically disconnected from a metal line [240] connecting the first transistor with the second transistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Miao by incorporating metal line electrically disconnected from source region and drain region as taught in Dia in order to utilize known semiconductor structure.
Regarding claim 2, Miao in view of Dia discloses [fig. 4] wherein the first input signal and the second input signal are a differential signal pair [Vin/Vip].
Regarding claim 3, Miao in view of Dia discloses [fig. 4] wherein each of the first input signal and the second input signal is a high-speed analog signal [see introduction section].
Regarding claim 7, Miao in view of Dia discloses [fig. 4] further comprising: a first capacitor [CH] having a node [node between M1 and CH] connected between the first transistor and the first output terminal; and a second capacitor [CH] having a node connected [node between M2 and CH] between the second transistor and the second output terminal.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Miao et al. in view of Dia et al. further in view of Kobatashi et al. (JP 2000132989A and Kobayashi hereinafter)
Regarding claim 5, Miao in view of Dia discloses all aspects of the instant invention with respect to claim 1 as outlined above. Miao further discloses [M1n and M2n is replica of Ml and M2, fig. 4, page 205]. Miao in view of Dia does not explicitly disclose wherein the first dummy transistor, the second dummy transistor, the first transistor, and the second transistor are a same size.
However, Kobayashi discloses [figs. 1-2] wherein first dummy transistor, second dummy transistor, first transistor, and second transistor of track and hold circuit are a same size [page 3]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Miao in view of Dia by incorporating same size transistors as taught in Kobayashi in order to provide highly accurate track and hold circuit [page 3].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Miao et al. in view of Dia et al. further in view of Soeraasen (US 7167029)
Regarding claim 6, Miao in view of Dia discloses all aspects of the instant invention with respect to claim 1 as outlined above. Miao in view of Dia does not explicitly disclose further comprising: a first signal line; and a second signal line, wherein a gate of the first dummy transistor and a gate of the first transistor are connected to the first signal line, and a gate of the second dummy transistor and a gate of the second transistor are connected to the second signal line.
However, Soeraasen discloses sampling circuit [fig. 2] wherein a gate of a first transistor [12’] and a gate of additional transistor [102] are connected to a first signal line [CKH_], and a gate of the second transistor [14’] and a gate of second additional transistor [104] are connected to a second signal line [CKL]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Miao in view of Dia by incorporating gate signal as taught in Soeraasen in order to provide cancellation of the charge-injection, and thus linearizing the charge transfer [cl. 2, ln. 30-64].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Miao et al. in view of Dia et al.
Regarding claim 4, Miao in view of Dia discloses all aspects of the instant invention with respect to claim 1 as outlined above. Miao in view of Dia further discloses 631MHZ [see introduction section]. Miao in view of Dia does not explicitly disclose wherein each of the first input signal and the second input signal has a speed of gigahertz or higher. One of ordinary skill in the art would have been motivated to have used the claimed range since such a range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
Prosecution Insights