DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/1/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING AIR GAP AND BACKBONE STRUCTURE.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. US PGPub. 2021/0343600. Regarding claim 13, Chen teaches a semiconductor device (200, fig. 29A-D) [0015] comprising: a substrate (206, fig. 29A) [0016] comprising a first active pattern (206’ on region 202A, fig. 29C; hereinafter called 206’A) and a second active pattern (206’ on left side of region 202B, fig. 29C; hereinafter called 206’B); a first channel pattern (220’ on region 202A, fig. 29C; hereinafter called 220’A) [0020] on the first active pattern (206’A) and a second channel pattern (220’ on left side of region 202B, fig. 29C; hereinafter called 220’B) [0020] on the second active pattern (206’B), each of the first channel pattern (220’A) and second channel pattern (220’B) comprising a plurality of semiconductor patterns (220’A and 220’B, fig. 29C, [0020]), which are vertically stacked and spaced apart from each other; a first source/drain pattern (320A, fig. 29D) [0041] connected (fig. 18-19, [0041]) to the first channel pattern (220’A) and a second source/drain pattern (320A, fig. 29D) [0041] connected (fig. 18-19, [0041]) to the second channel pattern (220’B); a first gate electrode (384A, fig. 29C) [0053] on the first channel pattern (220’A) and a second gate electrode (384A on the left side of region 202B, fig. 29C; hereinafter called 384AB) [0053] on the second channel pattern (220’B); and a backbone structure (280B-2, fig. 29C) [0045] provided between the first gate electrode (384A) and the second gate electrode (384AB), wherein the backbone structure (280B-2) comprises: a liner pattern (272, fig. 29C) [0045] on a side surface of each of the first gate electrode (384A) and the second gate electrode (384AB); and a backbone pattern (274, fig. 29c) [0045] provided in a space defined by the liner pattern (272), wherein the liner pattern (272) contacts the plurality of semiconductor patterns (220’A, 220’B) (Chen et al., fig. 29A-D). Regarding claim 14, Chen teaches the semiconductor device of claim 13, wherein each of the first source/drain pattern (320A) and the second source/drain pattern (320B) is provided on an NMOSFET region [0015] and comprises n-type impurities [0015], and wherein the liner pattern (272) comprises one or more of SiO2 [0031], BPSG [0031], or SiOC (Chen et al., fig. 29C).
Regarding claim 15, Chen teaches the semiconductor device of claim 13, wherein each of the first source/drain patterns (320A) and the second source/drain pattern (320B) is provided on a PMOSFET region [0015] and comprises p-type impurities [0015], and wherein the liner pattern (272) comprises one or more of Si3N4[0031], SiC, AlN, or Al2O3 (Chen et al., fig. 29C).
Regarding claim 16, Chen teaches the semiconductor device of claim 13, further comprising a device isolation layer (250, fig. 29C) [0025] defining the first active pattern (206’A) and the second active pattern (206’B), wherein the liner pattern (272) extends from the side surface of the first gate electrode (384A) to the side surface of the second gate electrode (384AB) via a top surface of the device isolation layer (250), and a top surface of the liner pattern (272), a top surface of the backbone pattern (280B-2), and a top surface of each of the first gate electrode (384A) and the second gate electrode (384AB) are substantially coplanar (fig. 29C) with each other (Chen et al., fig. 29C).
Regarding claim 17, Chen teaches the semiconductor device of claim 13, further comprising: a gate insulating layer (382, fig. 29C) [0050] on each of the plurality of semiconductor patterns (220’A, 220’B); and a high-k dielectric layer (combination of hi-K layers, [0051]; hereinafter called 382-Hi-K) provided between the gate insulating layer (382) and each of the first gate electrode (384A) and the second gate electrode (384AB), wherein the liner pattern (272) contacts the plurality of semiconductor patterns (220’A, 220’B), the gate insulating layer (382), and the high-k dielectric layer (382-Hi-K) (Chen et al., fig. 29C, [0050]-[0051]).
Allowable Subject Matter
The closest prior art Chen et al. above teaches a backbone structure but fails to teach air gaps between the backbone structures and the gate electrode, semiconductor pattern and/or source/drain patterns. Claims 1-12 and 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device comprising “a backbone structure on a side surface of the gate electrode; and a first air gap pattern between the backbone structure and each of the plurality of semiconductor patterns, wherein the first air gap pattern is provided on a second side surface of each of the plurality of semiconductor patterns” as recited in claim 1; and a semiconductor device comprising “a first air gap pattern provided between the gate insulating layer and the second backbone structure” in combination with the limitation wherein “the first backbone structure comprises: a first sub-backbone pattern on the device isolation layer; and a second backbone pattern filling a space defined by the first sub-backbone pattern, wherein the second backbone structure comprises: a second sub-backbone pattern on the device isolation layer; and the second backbone pattern on the second sub-backbone pattern, wherein an uppermost surface of the first sub-backbone pattern is located higher than an uppermost surface of the second sub-backbone pattern” as recited in claim 18. Claims 2-12 and 19-20 are also allowed for further limiting and depending upon allowed claims 1 and 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. US PGPub. 2022/0399463 teaches a generic semiconductor device (fig. 2A-2B) with no backbone structure over the STI. YU et al. US PGPub. 2022/0302275 teaches a semiconductor device comprising a backbone structure over the STI and air gaps (fig. 21) in between the semiconductor/channel patterns but no air gaps between the backbone structure and the gate electrode, semiconductor pattern and/or source/drain patterns. Kim et al. US PGPub. 2022/0223711 teaches a semiconductor device comprising a backbone structure (fig. 1) but fails to teach any air gaps between the backbone structure and the gate electrode, semiconductor pattern and/or source/drain patterns
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
