DETAILED ACTION
This action is in response to communications: Amendment filed July 7, 2026.
Claims 1-10 and 16-25 are pending in this case. Claims 1-4, 9, 10, 16, 17, 19, and 20 have been newly amended. Claims 11-15 have been newly cancelled. Claims 21-25 have been newly added. This action is made FINAL.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 5, 2026 and July 7, 2026 were filed after the mailing date of the Non-Final Office Action on April 15, 2026. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 7, and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUNDARAM et al. (US 2017/0060202) in view of Song (US 9,959,936).
As to claim 1, SUNDARAM et al. disclose a graphics processor (Figure 2, circuit 212, where [0046] notes one or more circuits 212 may be implemented as a graphics processing unit (GPU)) comprising: a graphics core cluster ([0046] notes circuit 212 may be a multi-core processor) including processing resources to execute instructions to perform graphics and compute operations ([0047] notes one or more circuits 212, e.g. multi-core GPU, to execute machine-readable instruction sets, where, by definition, a multi-core GPU performs graphics and compute operations); and a memory access pipeline (e.g. thermal management controller 150 of Figure 1, where [0014] notes thermal management controller 150 may include be a hardwired circuit within a processor, e.g. circuit 212 implemented as a GPU, [0042], [0043] further notes thermal management controller 150 may include one or more dedicated control circuits communicatively coupled to each memory resource 110 and may include one or more configurable circuits capable of reading and executing one or more sets or machine-readable instructions, which may be stored in a storage device or memory integrated with the thermal management controller 150) configured to access the memory devices (e.g. memory resources 110A-110n) on behalf of the graphics core cluster (e.g. circuit 212 as a multi-core processor)([0044] notes one or more communications buses may communicably couple the thermal management controller 150 to each of the memory resources 110, e.g. depicted in Figure 1 as three (3) buses communicably couple the thermal management controller 150 to each of the plurality of memory resources 110, where command (CMD) bus 152 permits the thermal management controller 150 to bidirectionally communicate with each of the plurality of memory resources 110, where such commands may include, but are not limited to, commands that limit, alter, adjust, restrict or halt the flow of data to/from memory resources 110 experiencing a high temperature thermal condition), each of the memory devices having a thermal status (Figure 1, [0020] notes each of memory resources 110A-110n includes at least one respective comparator 120A-120n that are communicatively coupled to at least one respective thermal sensor 122A-122n which provides a real-time signal that includes information indicative of the temperature of the memory resource 110 to the respective comparator 120, [0021] notes each memory resource 110A-110n further includes data indicative of a respective first, e.g. “HIGH SET,” temperature threshold 112A-112n, and a respective second, e.g. “LOW SET,” temperature threshold 114A-114n, [0022] notes each memory resource 110A-110n further includes a respective first output, e.g. “ALERT” pin 124A-124n, and [0024] notes each memory resource 110A-110n further includes a respective register, e.g. “STATUS REGISTER,” 126A-126n, which provides a data storage area in the memory resource where data indicative or representative of a thermal state of the memory resource 110 may be stored or written), the memory access pipeline including circuitry (e.g. thermal management controller 150 including one or more dedicated circuits and/or configurable circuits noted above) configured to: monitor the thermal status for the memory devices ([0044] notes an alert bus 154 permits alert signals generated by each of the memory resources 110 to reach the thermal management controller 150, the alert signal can be an unaddressed signal indicative of an occurrence of a high temperature thermal event in one or more of the memory resources 110 and/or thermal management controller 150 may use data accessed via the status bus 156 and/or thermal management controller 150 may access data stored in the register 126 in each of the memory resources 110, where the thermal management controller 150 may, via the status bus 156, bidirectionally communicate with the register 126 in each of the memory resources 110 to identify the memory resource 110 in which the high temperature event has occurred); and…balance a thermal impact of memory accesses to the memory devices ([0039], [0040], [0041] notes thermal management controller 150 for controlling, restricting, or otherwise adjusting the flow of data to and/or from each one of some or all of the plurality of memory resources 110 upon receipt of thermal event).
SUNDARAM et al. differ from the invention defined in claim 1 in that SUNDARAM et al. do not disclose, “…an interface to memory devices configured as graphics processor memory…” nor do SUNDARAM disclose its thermal management controller, e.g. memory access pipeline, to “…receive a series of memory access requests to the memory devices; enqueue the series of memory access requests to an access request buffer; and reorder, within the access request buffer, memory access requests within the series of memory access requests to balance a thermal impact of memory accesses to the memory devices.”
Song also discloses an interface to memory devices (column 3, lines 29-31 notes computer-readable medium (CRM) 112 includes volatile memory, non-volatile memory 114, and memory access manager 116, and lines 44-49 further notes non-volatile memory 114 includes solid-state drive 118 (SSD 118) and Flash memory integrated circuit (IC) chip 120 (Flash chip 120), where lines 40-41 and column 4, lines 6-9 notes access manager 116 manages access of CRM 112, lines 55-58 further notes input/output ports 122 allows computing device 102 to interact with other devices and/or users and lines 64-65 further notes data interface(s) 126 provides connectivity to one or more networks and other devices connected therewith) configured as graphics processor memory (e.g. column 3, lines 58-63 notes graphics engine 124 processes and renders graphics for computing device 102, where graphics engine 124 accesses computer readable medium (CRM) 112 to render graphics, thus may be considered “graphics processor memory”); a memory access pipeline (Figure 2, access manager 116 including translation maps 202, heat maps 204, filters 206, sensor interface 208, and access sequencer 210, implemented by processor 102 of Figure 1) configured to access the memory devices (e.g. CRM including volatile memory and non-volatile memory 114 as noted above), each of the memory devices having a thermal status (e.g. temperature sensors), the memory access pipeline including circuitry (perform process 300 of Figure 3) configured to: monitor the thermal status for the memory devices (step 304, column 5, lines 61 thru column 6, lines 4 notes determining respective temperatures of a first location and a second location of a memory device, where column 5, lines 8-11 notes access manager 116 includes heat maps 204, which maintains temperature information for physical locations of a memory device, and lines 21-26 further notes sensor interface 208 enables access manager 116 to receive information from temperature sensors associated with computer-readable medium (CRM) 11 or memory devices thereof); receive a series of memory access requests to the memory devices (step 302, column 5, lines 54-60 notes receiving a request to access a memory device, e.g. column 6, lines 32-34 notes example of multiple requests to access memory device may include one or more requests to read data from the memory device); enqueue the series of memory access requests to an access request buffer (column 5, lines 27-29 notes configured to monitor a queue of memory access requests or memory access commands (e.g. read, write, or erase), thus denoting memory access requests are queued, e.g. buffered); and reorder, within the access request buffer, memory access requests within the series of memory access requests to balance a thermal impact of memory accesses to the memory devices (step 306, column 6, lines 5-19 notes which of two locations to access is selected based on the respective temperatures, step 308, column 6, lines 20-40 notes an order in which to access two locations is determined based on the respective temperatures, e.g. the one or more requests to read data from the memory device, step 310, column 6, lines 41-51 notes accessing the location(s) of the memory device based on the determined order, e.g. such as for requests to read data from the memory device, performance of the access is delayed or re-ordered in the queue effective to access the location based on the determined order, where by doing so, access of the memory device(s) is managed such that a temperature of the memory device is minimized, where column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue). NOTE: As noted above, CRM 112 include a plurality of memory devices, e.g. SSD 118 and Flash chip, where temperature sensors may be located at each of these memory devices. Therefore, although the steps noted above describes a single memory device, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the steps to be performed across the plurality of memory devices as described, yielding predictable results, without changing the scope of the invention.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify SUNDARAM et al.’s thermal management controller to reorder the memory access requests to balance a thermal impact of the memory accesses to the memory devices as described in Song such that access of the memory device(s) is managed such that a temperature of the memory device is minimized, thus enhancing the performance of the system (see column 6, lines 41-51 of Song).
As to claim 2, SUNDARAM et al. modified with Song disclose to balance the thermal impact of the memory accesses to the memory devices, the circuitry is configured to reorder the memory access requests based on the thermal status for the memory devices (SUNDARAM, e.g. as noted in claim 1, thermal management controller may receive a high temperature alert generated by at least one of a plurality of communicably coupled memory resources, and further restrict, throttle, limit, or otherwise control data traffic to and/or from the at least one communicably coupled memory resource that generated the high temperature alert; modified with Song, e.g. as noted in claim 1, step 308, column 6, lines 20-31 notes determining an order in which to access the locations are based on the respective temperatures of the memory devices, where column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue).
As to claim 3, SUNDARAM et al. modified with Song disclose the circuitry configured to reorder a memory access request to a first memory device after one or more memory access requests to a second memory device in response to a determination that the second memory device has a second temperature that is lower than a first temperature of the first memory device (SUNDARAM, e.g. as noted in claim 1, thermal management controller may receive a high temperature alert generated by at least one of a plurality of communicably coupled memory resources, and further restrict, throttle, limit, or otherwise control data traffic to and/or from the at least one communicably coupled memory resource that generated the high temperature alert; modified with Song, e.g. as noted in claim 1, step 306, column 6, lines 5-19 notes determining which of two locations to access is selected based on the respective temperatures, e.g. a cooler of the two locations can be selected such that a data write operation increases the temperature of the cooler location, instead of the hotter location, step 308, column 6, lines 20-31 notes determining an order in which to access the locations are based on the respective temperatures of the memory devices, where column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue).
As to claim 4, SUNDARAM et al. modified with Song disclose the circuitry including one or more memory controllers coupled with the memory devices (SUNDARAM, e.g. as noted in claim 1, thermal management controller 150 coupled to each of memory resources 112A-112n; modified with Song, access manager 116 coupled to CRM 112, further to each of non-volatile memory 114), the one or more memory controllers to reorder the memory access requests within the series of memory access requests to balance the thermal impact of the memory accesses to the memory devices (SUNDARAM, as noted in claim 1, [0039], [0040], [0041] notes thermal management controller 150 for controlling, restricting, or otherwise adjusting the flow of data to and/or from each one of some or all of the plurality of memory resources 110 upon receipt of thermal event; modified with Song, e.g. as noted in claim 1, column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue, where column 6, lines 20-40 notes determining an order in which to access the memory devices based on their respective temperatures minimizes the heat’s effect on electrical properties of the memory cells, thereby improving reliability of the memory devices).
As to claim 6, SUNDARAM et al. modified with Song disclose the circuitry configured to monitor the thermal status for the memory devices via thermal sensors within the memory devices (SUNDARAM, e.g. as noted in claim 1, each of memory resources 112A-112n comprises thermal sensors 122A-122n; modified with Song, column 5, lines 21-26 notes each of memory devices may include temperature sensors).
As to claim 7, SUNDARAM et al. modified with Song disclose the thermal status for the memory devices includes a thermal status for multiple memory regions of the memory devices (modified with Song, as noted in claim 1, step 304, column 5, lines 61 thru column 6, lines 4 notes determining respective temperatures of a first location and a second location of the memory device, where column 5, lines 21-26 notes temperature sensors providing information on a per-device, per-block, or per-page resolution).
Claims 21-23 are similar in scope to claims 1-3, respectively, and are therefore rejected under similar rationale.
Claim(s) 5, 8-10, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUNDARAM et al. (US 2017/0060202) in view of Song (US 9,959,936) as applied to claims 1, 7, and 21 above, and further in view of Arora et al. (US 2016/0086654).
As to claim 5, SUNDARAM et al. modified with Song disclose the circuitry configured to monitor the thermal status for the memory devices (modified with Song, column 5, lines 8-20 notes access manager 116 includes heat maps 204, which may be provided based on translation maps 202, where heat maps 204 maintain temperature information for physical locations of a memory device, where filters 206 may be applied to heat maps 204 to estimate or predict the dissipation of heat between physical locations of a memory device), but do not disclose, but Arora et al. disclose the circuitry configured to monitor the thermal status for the memory devices via a thermal model that is based on usage metrics ([0028]-[0032] notes memory controller 251 utilizes an integrated thermal model to determine the expected thermal level for the physical locations in the structure of processing node 201 and may be used to manage data placement and compute dispatch to minimize a cost function consisting of at least the following dimensions: intra-stack thermal penalty, performance penalty, power penalty, and resilience and reliability, the thermal model may further correlate expected thermal levels with each of a number of locations within the structure of node 201 based on memory activity patterns (read throughput, write throughput, row buffer hit rate and other factors), logic die instructions per cycle (IPC), operating voltage supply levels, processor core frequencies, thermal dissipation capability of cooling components and surfaces, packaging, computation pattern (e.g. integer or floating-point intensive), latency, and other factors).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify SUNDARAM et al. modified with Song’s system and method of monitoring thermal status of memory devices with Arora et al.’s method of monitoring the thermal status for the memory devices via a thermal model to minimize cost functions such as thermal penalty, performance penalty, power penalty, and resilience and reliability, thus further enhancing the performance of the system (see [0028] of Arora et al.)
As to claim 8, SUNDARAM et al. modified with Song disclose the multiple memory regions (modified with Song, as noted in claim 7, memory devices having multiple locations), but do not disclose, but Arora et al. disclose the multiple memory regions including multiple memory dies or memory channels (Figure 2B, [0020] notes multiple memory stacks 210-213, each memory stack 210-213 comprising stacked dies A, B, C, D, and E, where dies 210-213E are logic dies located at the bottoms of memory stacks 210-213, respectively, and the A, B, C, and D dies in each of the stacks 210-213 are memory dies).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify SUNDARAM et al. modified with Song’s multiple memory regions to further include multiple memory dies as described by Arora et al. as an alternative form of memory regions, where Arora et al. describes such memory dies are stacked so that they are within close proximity of a processing logic, thus enabling thermal monitoring within such memory dies (see Background of Arora et al.).
As to claim 9, SUNDARAM et al. modified with Song and Arora et al. disclose the circuitry configured to reorder the memory access requests within the series of memory access requests to balance the thermal impact of the memory accesses to the multiple memory regions of the memory devices (modified with Song, as noted in claim 1, step 308, column 6, lines 20-40 notes an order in which to access two locations is determined based on the respective temperatures, e.g. the one or more requests to read data from the memory device, step 310, column 6, lines 41-51 notes accessing the location(s) of the memory device based on the determined order, e.g. such as for requests to read data from the memory device, performance of the access is delayed or re-ordered in the queue effective to access the location based on the determined order, where by doing so, access of the memory device(s) is managed such that a temperature of the memory device is minimized, where column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue; further modified with Arora, Figure 3, step 301, [0041] notes memory controller 251 determines an expected thermal level associated with each of a number of locations in the node 201, further to step 305, [0042] notes memory controller 251 determines the type of the received operation, e.g. a processing task or a memory write operation, where if the operation is a memory write operation, proceeding to step 311, [0043], [0044] notes the memory controller 251 calculates the thermal penalty associated with the memory write operation, step 313, [0045], [0046] notes the memory controller 251 determines for the data being placed a probability of concurrent access with other data stored in the memory, step 315, [0047]-[0052] notes the memory controller 251 selects a target location out of multiple available physical locations, then assigns the memory write operation to the target location, and step 317, [0055] notes the memory controller 251 causes the data to be written to the assigned target location as provided by the received operation; and if the operation is a processing task, proceeding to step 321, [0056] notes the memory controller 251 determines the thermal penalty associated with the task, step 323, [0057]-[0060] notes the memory controller 251 identifies one or more available target locations that are a minimum distance away from one or more heat sources in the node 201 where the processing tasks can be executed, step 325, [0061] notes the memory controller 251 assigns the processing task to one of the identified target location of block 323, and step 327, [0060] notes the processing task is dispatched to and executed at the assigned location).
As to claim 10, SUNDARAM et al. modified with Song and Arora et al. disclose the circuitry configured to reorder a memory access request to a first region of a memory device after one or more memory access requests to a second region of the memory device in response to a determination that the second region has a second temperature that is lower than a first temperature of the first region (modified with Song, e.g. as noted in claim 1, step 306, column 6, lines 5-19 notes determining which of two locations to access is selected based on the respective temperatures, e.g. a cooler of the two locations can be selected such that a data write operation increases the temperature of the cooler location, instead of the hotter location; further modified with Arora, [0048] notes for a memory write operation for which the data is associated with a relatively high thermal penalty, the memory controller 251 may store the data at a physical location having a greater thermal dissipation capability, thus, data associated with a high thermal penalty may be stored at locations closer to cooling components or closer to exposed surfaces of the memory stacks 210-213, as compared to data with a lower thermal penalty, and since a higher access frequency for data results in a correspondingly higher thermal penalty for that data, data that is accessed frequently can be stored at a location that is closer to cooling components and exterior surfaces than data that is less frequently accessed, and [0058] further notes for a processing task, memory controller 251 may select a target location that is a minimum distance away from the location of a concurrently accessed data to avoid the generation of access heat at one location).
Claim 24 is similar in scope to claims 5 and 6 combined, and is therefore rejected under similar rationale.
Claim 25 is similar in scope to claims 7 and 8 combined, and is therefore rejected under similar rationale.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUNDARAM et al. (US 2017/0060202) in view of Arora et al. (US 2016/0086654) and Song (US 9,959,936).
As to claim 16, SUNDARAM et al. discloses a graphics processing system (Figure 2, system 200 with one or more circuits 212, where [0046] notes circuit 212 may be implemented as a graphics processing unit (GPU), thus system 200 may be considered a graphics processing system) comprising: comprising: a first memory device (e.g. one of memory resources 110A-110n); a second memory device (e.g. a different one of memory resources 110A-110n); a graphics core cluster ([0046] notes circuit 212 may be a multi-core processor) including processing resources to execute instructions to perform graphics and compute operations ([0047] notes one or more circuits 212, e.g. multi-core GPU, to execute machine-readable instruction sets, where, by definition, a multi-core GPU performs graphics and compute operations); and a memory access pipeline (e.g. thermal management controller 150 of Figure 1, where [0014] notes thermal management controller 150 may include be a hardwired circuit within a processor, e.g. circuit 212 implemented as a GPU, [0042], [0043] further notes thermal management controller 150 may include one or more dedicated control circuits communicatively coupled to each memory resource 110 and may include one or more configurable circuits capable of reading and executing one or more sets or machine-readable instructions, which may be stored in a storage device or memory integrated with the thermal management controller 150) configured to access the first memory device and the second memory device (e.g. memory resources 110A-110n) on behalf of the graphics core cluster (e.g. circuit 212 as a multi-core processor)([0044] notes one or more communications buses may communicably couple the thermal management controller 150 to each of the memory resources 110, e.g. depicted in Figure 1 as three (3) buses communicably couple the thermal management controller 150 to each of the plurality of memory resources 110, where command (CMD) bus 152 permits the thermal management controller 150 to bidirectionally communicate with each of the plurality of memory resources 110, where such commands may include, but are not limited to, commands that limit, alter, adjust, restrict or halt the flow of data to/from memory resources 110 experiencing a high temperature thermal condition), the first memory device and the second memory device each having a thermal status (Figure 1, [0020] notes each of memory resources 110A-110n includes at least one respective comparator 120A-120n that are communicatively coupled to at least one respective thermal sensor 122A-122n which provides a real-time signal that includes information indicative of the temperature of the memory resource 110 to the respective comparator 120, [0021] notes each memory resource 110A-110n further includes data indicative of a respective first, e.g. “HIGH SET,” temperature threshold 112A-112n, and a respective second, e.g. “LOW SET,” temperature threshold 114A-114n, [0022] notes each memory resource 110A-110n further includes a respective first output, e.g. “ALERT” pin 124A-124n, and [0024] notes each memory resource 110A-110n further includes a respective register, e.g. “STATUS REGISTER,” 126A-126n, which provides a data storage area in the memory resource where data indicative or representative of a thermal state of the memory resource 110 may be stored or written), and the memory access pipeline including circuitry (e.g. thermal management controller 150 including one or more dedicated circuits and/or configurable circuits noted above) configured to: monitor the thermal status for the memory devices ([0044] notes an alert bus 154 permits alert signals generated by each of the memory resources 110 to reach the thermal management controller 150, the alert signal can be an unaddressed signal indicative of an occurrence of a high temperature thermal event in one or more of the memory resources 110 and/or thermal management controller 150 may use data accessed via the status bus 156 and/or thermal management controller 150 may access data stored in the register 126 in each of the memory resources 110, where the thermal management controller 150 may, via the status bus 156, bidirectionally communicate with the register 126 in each of the memory resources 110 to identify the memory resource 110 in which the high temperature event has occurred); and…balance a thermal impact of memory accesses to the memory devices ([0039], [0040], [0041] notes thermal management controller 150 for controlling, restricting, or otherwise adjusting the flow of data to and/or from each one of some or all of the plurality of memory resources 110 upon receipt of thermal event).
SUNDARAM et al. differ from the invention defined in claim 16 in that SUNDARAM et al. disclose a first memory device and a second memory device, but do not disclose “…a first memory device including a first base die and first memory dies stacked on the first base die; and a second memory device including a second base die and second memory dies stacked on the second base die…” SUNDARAM et al. further differ from the invention defined in claim 16 in that SUNDARAM et al. do not disclose its thermal management controller, e.g. memory access pipeline to “…receive a series of memory access requests to the first memory device and the second memory device; enqueue the series of memory access requests to an access request buffer; and reorder, within the access request buffer, memory access requests within the series of memory access requests to balance thermal impact of memory accesses to the first memory device and the second memory device.”
Arora et al. disclose a first memory device (Figure 2B, one of memory stacks 210-213) including a first base die (respective logic dies 210-213E) and first memory dies (respective memory dies 210-213A, 210-213B, 210-213C, and 210-213D) stacked on the first base die ([0020] notes multiple memory stacks 210-213, each memory stack 210-213 comprising stacked dies A, B, C, D, and E, where dies 210-213E are logic dies located at the bottoms of memory stacks 210-213, respectively, and the A, B, C, and D dies in each of the stacks 210-213 are memory dies); a second memory device (a different one of memory stacks 210-213) including a second base die (respective logic dies 210-213E) and second memory dies (respective memory dies 210-213A, 210-213B, 210-213C, and 210-213D) stacked on the second base die ([0020] notes multiple memory stacks 210-213, each memory stack 210-213 comprising stacked dies A, B, C, D, and E, where dies 210-213E are logic dies located at the bottoms of memory stacks 210-213, respectively, and the A, B, C, and D dies in each of the stacks 210-213 are memory dies). Arora et al. further disclose a memory access pipeline (memory controller 251, implemented in host processor 250) configured to access the first memory device (e.g. one of memory stacks 210-213) and the second memory device (e.g. a different one of memory stacks 210-213), the first memory device and the second memory device each having a thermal status ([0039] notes each of memory stacks have thermal sensors 220-223 attached to measure actual temperatures of memory stacks 210-213), and the memory access pipeline including circuitry (memory controller 251, implemented in host processor 250, [0024] notes memory controller further includes control logic for performing thermal management of the memory via data placement and compute dispatch scheme)(placement process 300) configured to: monitor the thermal status for the first memory device and the second memory device (step 301, [0041] notes memory controller 251 determines an expected thermal level associated with each of a number of locations in the node 201); receive a series of memory access requests to the first memory device and the second memory device (step 303, [0042] notes memory controller 251 receives an operation to be placed in the processing node 201); enqueue the series of memory access requests to an access request buffer ([0042] notes the received operations may be one of several queued operations that are pending placement in the node 201); and reorder…memory access requests within the series of memory access requests to balance thermal impact of memory accesses to the first memory device and the second memory device (step 305, [0042] notes memory controller 251 determines the type of the received operation, e.g. a processing task or a memory write operation, where if the operation is a memory write operation, proceeding to step 311, [0043], [0044] notes the memory controller 251 calculates the thermal penalty associated with the memory write operation, step 313, [0045], [0046] notes the memory controller 251 determines for the data being placed a probability of concurrent access with other data stored in the memory, step 315, [0047]-[0052] notes the memory controller 251 selects a target location out of multiple available physical locations, then assigns the memory write operation to the target location, and step 317, [0055] notes the memory controller 251 causes the data to be written to the assigned target location as provided by the received operation; and if the operation is a processing task, proceeding to step 321, [0056] notes the memory controller 251 determines the thermal penalty associated with the task, step 323, [0057]-[0060] notes the memory controller 251 identifies one or more available target locations that are a minimum distance away from one or more heat sources in the node 201 where the processing tasks can be executed, step 325, [0061] notes the memory controller 251 assigns the processing task to one of the identified target location of block 323, and step 327, [0060] notes the processing task is dispatched to and executed at the assigned location).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify SUNDARAM et al. modified with Song’s multiple memory regions to further include multiple memory dies as described by Arora et al. as an alternative form of memory regions, where Arora et al. describes such memory dies are stacked so that they are within close proximity of a processing logic, thus enabling thermal monitoring within such memory dies (see Background of Arora et al.).
SUNDARAM et al. modified with Arora et al. do not explicitly disclose “…reorder, within the access request buffer, memory access requests within the series of memory access requests to balance a thermal impact of memory accesses to the first memory device and the second memory device.”
Song also discloses a memory access pipeline (Figure 2, access manager 116 including translation maps 202, heat maps 204, filters 206, sensor interface 208, and access sequencer 210, implemented by processor 102 of Figure 1) configured to access memory devices (column 3, lines 29-31 notes computer-readable medium (CRM) 112 includes volatile memory, no-volatile memory 114, and memory access manager 116, and lines 44-49 further notes non-volatile memory 114 includes solid-state drive 118 (SSD 118) and Flash memory integrated circuit (IC) chip 120 (Flash chip 120)), each of the memory devices having a thermal status (e.g. temperature sensors), the memory access pipeline including circuitry (perform process 300 of Figure 3) configured to: monitor the thermal status for the memory devices (step 304, column 5, lines 61 thru column 6, lines 4 notes determining respective temperatures of a first location and a second location of a memory device, where column 5, lines 8-11 notes access manager 116 includes heat maps 204, which maintains temperature information for physical locations of a memory device, and lines 21-26 further notes sensor interface 208 enables access manager 116 to receive information from temperature sensors associated with computer-readable medium (CRM) 11 or memory devices thereof); receive a series of memory access requests to the memory devices (step 302, column 5, lines 54-60 notes receiving a request to access a memory device, e.g. column 6, lines 32-34 notes example of multiple requests to access memory device may include one or more requests to read data from the memory device); enqueue the series of memory access requests to an access request buffer (column 5, lines 27-29 notes configured to monitor a queue of memory access requests or memory access commands (e.g. read, write, or erase), thus denoting memory access requests are queued, e.g. buffered); and reorder, within the access request buffer, memory access requests within the series of memory access requests to balance a thermal impact of memory accesses to the first memory device and the second memory device (step 306, column 6, lines 5-19 notes which of two locations to access is selected based on the respective temperatures, step 308, column 6, lines 20-40 notes an order in which to access two locations is determined based on the respective temperatures, e.g. the one or more requests to read data from the memory device, step 310, column 6, lines 41-51 notes accessing the location(s) of the memory device based on the determined order, e.g. such as for requests to read data from the memory device, performance of the access is delayed or re-ordered in the queue effective to access the location based on the determined order, where by doing so, access of the memory device(s) is managed such that a temperature of the memory device is minimized, where column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue). NOTE: As noted above, CRM 112 include a plurality of memory devices, e.g. SSD 118 and Flash chip, where temperature sensors may be located at each of these memory devices. Therefore, although the steps noted above describes a single memory device, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the steps to be performed across the plurality of memory devices as described, yielding predictable results, without changing the scope of the invention.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify SUNDARAM et al. modified with Arora et al.’s thermal management controller to reorder the memory access requests to balance a thermal impact of the memory accesses to the memory devices as described in Song such that access of the memory device(s) is managed such that a temperature of the memory device is minimized, thus enhancing the performance of the system (see column 6, lines 41-51 of Song).
As to claim 17, SUNDARAM et al. modified with Arora et al. and Song disclose to balance the thermal impact of the memory accesses to the first memory device and the second memory device, the circuitry is configured to reorder the memory access requests based on the thermal status for the first memory device and the second memory device (SUNDARAM, e.g. as noted in claim 16, thermal management controller may receive a high temperature alert generated by at least one of a plurality of communicably coupled memory resources, and further restrict, throttle, limit, or otherwise control data traffic to and/or from the at least one communicably coupled memory resource that generated the high temperature alert; further modified with Song, e.g. as noted in claim 16, step 308, column 6, lines 20-31 notes determining an order in which to access the locations are based on the respective temperatures of the memory devices), including to reorder a memory access request to the first memory device after a memory access request to the second memory device in response to a determination that a temperature of the second memory device is lower than the temperature of the first memory device (SUNDARAM, e.g. as noted in claim 16, thermal management controller may receive a high temperature alert generated by at least one of a plurality of communicably coupled memory resources, and further restrict, throttle, limit, or otherwise control data traffic to and/or from the at least one communicably coupled memory resource that generated the high temperature alert; further modified with Song, e.g. as noted in claim 16, step 306, column 6, lines 5-19 notes determining which of two locations to access is selected based on the respective temperatures, e.g. a cooler of the two locations can be selected such that a data write operation increases the temperature of the cooler location, instead of the hotter location; modified with Arora, [0048] notes for a memory write operation for which the data is associated with a relatively high thermal penalty, the memory controller 251 may store the data at a physical location having a greater thermal dissipation capability, thus, data associated with a high thermal penalty may be stored at locations closer to cooling components or closer to exposed surfaces of the memory stacks 210-213, as compared to data with a lower thermal penalty, and since a higher access frequency for data results in a correspondingly higher thermal penalty for that data, data that is accessed frequently can be stored at a location that is closer to cooling components and exterior surfaces than data that is less frequently accessed, and [0058] further notes for a processing task, memory controller 251 may select a target location that is a minimum distance away from the location of a concurrently accessed data to avoid the generation of access heat at one location).
As to claim 18, SUNDARAM et al. modified with Arora et al. and Song disclose the first base die including first control logic to control access to the first memory dies and the second base die including second control logic to control access to the second memory dies (modified with Arora, [0024] notes memory controller 251, implemented in the host processor, includes control logic for performing thermal management of the memory via a data placement and compute dispatch scheme, where as an embodiment, memory controller functions may be implemented in the logic dies E instead of host processor, thus would be respective memory controllers in each logic die, e.g. at least a first control logic and a second control logic).
As to claim 19, SUNDARAM et al. modified with Arora et al. and Song disclose the first control logic is to balance memory accesses between the first memory dies based on the thermal status of the first memory dies and the second control logic is to balance memory accesses between the second memory dies based on the thermal status of the second memory dies (modified with Arora, e.g. as noted in claim 18, a first memory controller including control logic, e.g. first control logic, and a second memory controller including control logic, e.g. a second control logic, where [0023] notes control logic for a node 201 implements such a scheme may model or dynamically monitor the thermal levels of multiple locations in the memory stacks 210-213, then assign pending operations to locations in the memory stacks based on the expected thermal level at those locations and the expected thermal penalties that will be incurred by the operations).
As to claim 20, SUNDARAM et al. modified with Arora et al. and Song disclose the first control logic (modified with Arora, e.g. as noted in claims 18 and 19, a first control logic) is to balance memory accesses between a first plurality of memory channels of the first memory dies based on the thermal status of the first plurality of memory channels (modified with Arora, e.g. as noted in claim 19, control logic dynamically monitor the thermal levels of multiple locations in the memory stacks 210-213, then assign pending operations to locations in the memory stacks based on the expected thermal level at those locations and the expected thermal penalties that will be incurred by the operations, where the multiple locations may be considered “a first plurality of memory channels”) and the second control logic (modified with Arora, e.g. as noted in claims 18 and 19, a second control logic) is to balance memory accesses between a second plurality of memory channels of the second memory dies based on the thermal status of the second plurality of memory channels (modified with Arora, e.g. as noted in claim 19, control logic dynamically monitor the thermal levels of multiple locations in the memory stacks 210-213, then assign pending operations to locations in the memory stacks based on the expected thermal level at those locations and the expected thermal penalties that will be incurred by the operations, where the multiple locations may be considered “a second plurality of memory channels”).
Response to Arguments
Applicant’s arguments filed July 7, 2026 have been fully considered but they are not persuasive. Applicant amends independent claims 1 and 16 and adds new claim 21 to similarly recite, “…reorder, within the access request buffer, memory access requests within the series of memory access requests to balance a thermal impact of memory accesses to the first memory device and the second memory device…” Applicant argues on pages 8-13 of the Amendment filed that the prior art of record fails to teach or suggest the limitations of the claims as now amended.
Applicant argues on page 9 of the Amendment filed regarding claim 1 that, “…Sundaram does not teach or suggest these limitations. The Office Action relies on Sundaram's thermal management controller 150, memory resources 110, and related alert/status functionality. At most, Sundaram describes controlling, restricting, adjusting, or halting data flow to or from a memory resource in response to a thermal event. The Office Action appears to recognize this deficiency, stating that Sundaram does not disclose receiving a series of memory access requests, enqueueing the series to an access request buffer, and reordering memory accesses or memory access requests within the series. Thus, Sundaram does not teach the claimed request-buffer reordering performed within the access request buffer of a graphics processor memory access pipeline. (see first paragraph of page 9).
In reply, as noted in the rejection of claim 1 above, SUNDARAM is modified with Song for teaching at least “…receive a series of memory access requests to the memory devices; enqueue the series of memory access requests to an access request buffer; and reorder, within the access request buffer, memory access requests within the series of memory access requests to balance a thermal impact of memory accesses to the memory devices…” as claimed. Please see additional responses to arguments below regarding Song.
Applicant further argues on pages 9-10 of the Amendment filed regarding claim 1 that, “…Song does not cure this deficiency…Song’s cited ordering is directed to accessing locations of a memory device…That is materially different from amended claim 1…The Office Action itself confirms the distinction…Applicant respectfully submits that this reasoning does not supply the missing claim limitations. The fact that Song can order accesses to locations of a single memory device does not teach or suggest, after enqueueing a series of memory access requests to an access request buffer in a graphics processor memory access pipeline, reordering the already- enqueued memory access requests within that access request buffer to balance thermal impact across multiple graphics processor memory devices. Nor does the Office Action identify an articulated reason with rational underpinning for modifying Song’s single-memory-device location-ordering technique into the claimed multi-memory-device request-buffer reordering arrangement…” (see second paragraph of page 9 continued to page 10).
In reply, as noted in the rejection above, SUNDARAM discloses a thermal management controller for monitoring thermal events, e.g. high temperatures, of a plurality of memory devices. The thermal management controller may further restrict, throttle, limit, or otherwise control data traffic to and/or from at least one communicably coupled memory resource, e.g. that generated a high temperature alert ([0039], [0040], [0041]). However, as further noted in the rejection above, SUNDARAM does not explicitly teach its thermal management controller, e.g. memory access pipeline, to “…receive a series of memory access requests to the memory devices; enqueue the series of memory access requests to an access request buffer; and reorder, within the access request buffer, memory access requests within the series of memory access requests to balance a thermal impact of memory accesses to the memory devices.” Song describes its computer readable medium (CRM) 102 to include volatile memory (not illustrated) and non-volatile memory 114, which further comprises solid-state drive (SSD) 118 and Flash memory integrated-circuit (IC) chip (Flash chip) 120 (Figure 1, column 3, lines 29-54), where each may be considered “a memory device.” As further evidence of teaching of the described memories above may be “memory devices,” Song describes temperature sensors associated with CRM 112 or “memory devices thereof” (column 5, lines 21-26). Further still, Song discloses, in step 302 of method 300 of Figure 3 (column 5, lines 54-60), “receiving a request to access a memory device,” denoting the received request is to access a specific memory device, thus one of many memory devices, e.g. such as those described above. Therefore, the Examiner’s conclusion that Song teaches a plurality of memory devices and further balances thermal impact of memory accesses across the plurality memory devices as claimed is proper. However, because Song further describes its process performed at a finer granularity, e.g. on locations of the memory devices, the Examiner acknowledges this, noting the obviousness to perform at the level of the memory devices. Additionally, SUNDARAM is modified with Song, where SUNDARAM explicitly discloses controlling access, via the thermal management controller, to each of the plurality of memory devices, where the modification of SUNDARAM with Song may render the thermal management controller of SUNDARAM to implement the methods as performed by the access manager of Song, thus further rendering the method performed across the plurality of memory devices as claimed. Regarding the amendment of claim 1, Song further discloses its access manager 116 via access sequencer 210 monitors a queue of memory access requests or memory access commands (column 5, lines 27-29), denoting the memory access requests are “enqueued.” Further still, Song discloses, in step 308 of method 300 of Figure 3 (column 6, lines 20-40), determining an order in which to access a memory device based on respective temperatures, e.g. received from the temperature sensors associated with each of the memory devices. Step 310 of method 300 of Figure 3 (column 6, lines 41-51) notes accessing the memory device in the determined order, e.g. such as for requests to read data from the memory device, performance of the access is delayed or re-ordered in a queue effective to access the memory device in the determined order, where access manager 116 via access sequencer 210 further manages the sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue, denoting the memory access requests may be reordered “within the access request buffer.” Therefore, it is believed SUNDARAM modified with Song still teaches the limitations of claim 1 as now amended.
Applicant further argues on page 10 of the Amendment filed regarding claim 1 that, “…The distinction is reinforced by amended claim 3. Claim 3 recites that the circuitry is configured to reorder a memory access request to a first memory device after one or more memory access requests to a second memory device in response to a determination that the second memory device has a second temperature that is lower than a first temperature of the first memory device. Song’s cited selection of a cooler location within a memory device does not teach reordering a memory access request to one memory device after one or more memory access requests to another memory device based on the relative temperatures of the two memory devices…” (second paragraph of page 10).
In reply, as noted in the Examiner’s response above, SUNDARAM explicitly discloses its thermal management controller monitors thermal events, e.g. high temperatures, of a plurality of memory devices, and further restricts, throttles, limits, or otherwise controls data traffic to and/or from the at least one communicably coupled memory resource, e.g. to a memory device that generated a high temperature alert. Song discloses reordering memory access requests based on temperatures of the memory devices, but further describes reordering based on locations of a memory device. SUNDARAM is modified with Song, where SUNDARAM explicitly discloses controlling access, via the thermal management controller, to each of the plurality of memory devices, where the modification of SUNDARAM with song may render the thermal management controller of SUNDARAM to implement the methods as performed by the access manager of Song, thus further rendering the method performed across the plurality of memory devices as claimed. Therefore, it is believed SUNDARAM modified with Song still teaches the limitations of claim 3 as now amended.
Applicant further argues on pages 10-11 of the Amendment filed regarding independent claim 1 that, “…Arora does not cure the deficiencies of Sundaram and Song discussed above. The Office Action relies on Arora for thermal modeling, stacked memory dies, memory regions, and placement of operations based on expected thermal levels. Even assuming, without conceding, that Arora teaches monitoring thermal status via a thermal model and memory regions including multiple memory dies, Arora does not teach or suggest the amended claim 1 limitations requiring a graphics processor memory access pipeline to enqueue a series of memory access requests to an access request buffer and reorder, within the access request buffer, memory access requests within the series to balance thermal impact to memory devices…” (last paragraph of page 10 continued to page 11).
In reply, the Examiner believes SUNDARAM modified with Song still teaches the limitations of claim 1 as now amended. Please see the Examiner’s response above.
Applicant further argues on page 11 of the Amendment filed regarding dependent claim 10 that, “…Nor does Arora teach the amended limitation of claim 10. Claim 10 recites that the circuitry is configured to reorder a memory access request to a first region of a memory device after one or more memory access requests to a second region of the memory device in response to a determination that the second region has a second temperature that is lower than a first temperature of the first region. The Office Action relies on Arora's placement of data or processing tasks at target locations based on thermal penalty and expected thermal level. Such placement does not teach reordering memory access requests within an access request buffer as claimed, nor does it cure Song's failure to teach the claimed graphics processor memory access pipeline request-buffer reordering…” (first paragraph of page 11).
In reply, as noted in the rejection above, in step 304 of method 300 of Figure 3 (column 5, lines 61 thru column 6, lines 19), Song discloses determining respective temperatures of locations of a memory device, where the locations may correlate to the claimed “regions.” Song further discloses, in step 308 of method 300 of Figure 3 (column 6, lines 20-40), determining an order to access the locations of the memory device based on the determined temperatures, and in step 310 of method 300 of Figure 3 (column 6, lines 41-51), the determined order may include re-ordering memory requests, e.g. as performed by access manager 116 via access sequencer 210 (column 5, lines 29-32). Therefore, it is believed SUNDARAM modified with Song and Arora still teaches the limitations of claim 10 as now amended.
Applicant further argues on pages 11-12 of the Amendment filed regarding independent claim 16 that Sundaram, Arora, nor Song teaches the limitations of the claims as now amended for similar reasons as noted for claim 1 above (see fourth paragraph of page 11 continued to second paragraph of page 12).
In reply, claim 16 is similar in scope to claim 1. Therefore, the Examiner believes SUNDARAM modified with Arora and Song still teaches the limitations of claim 16 for similar reasons as noted for claim 1. Please see the Examiner’s responses regarding independent claim 1.
Applicant further argues on page 12 of the Amendment filed regarding dependent claim 17 that Sundaram, Arora, nor Song teaches the limitations of the claims as now amended for similar reasons as noted for claim 3 above (see third paragraph of page 12).
In reply, claim 17 is similar in scope to claim 3. Therefore, the Examiner believes SUNDARAM modified with Arora and Song still teaches the limitations of claim 17 for similar reasons as noted for claim 3. Please see the Examiner’s responses regarding independent claim 3.
Applicant adds new claims 21-25 which are similar in scope to claims 1-3 and 5-8. Applicant argues claim 21 is patentable for similar reasons as noted for independent claim 1 (see first paragraph of page 13).
In reply, claim 21 is similar in scope to claim 1. Therefore, the Examiner believes SUNDARAM modified with Song still teaches the limitations of claim 21 for similar reasons as noted for claim 1. Please see the Examiner’s responses regarding independent claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m.
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617
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