CTNF 18/791,963 CTNF 83016 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on August 1, 2024, October 13, 2024, January 9, 2025, April 28, 2025, June 23, 2025, August 19, 2025, October 16, 2025, January 6, 2026, and February 26, 2026 were filed on/after the filing date of the application on August 1, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Drawings 06-37 AIA The drawings were received on August 1, 2024 . These drawings are accepted . Election/Restrictions 08-08 AIA Restriction to one of the following inventions is required under 35 U.S.C. 121: I. Claim s 1-10 and 16-20 , drawn to monitoring thermal status of a plurality of memory devices and reordering memory accesses to the plurality of memory devices , classified in 345/536 . II. Claim s 11-15 , drawn to monitoring thermal status of a single memory device, migrating data to different regions of the memory device, and updating a virtual address mapping , classified in 345/566 . 08-13 AIA The inventions are independent or distinct, each from the other because: Inventions I and II are related as combination and sub-combination. Inventions in this relationship are distinct if it can be shown that (1) the combination as claimed does not require the particulars of the sub-combination as claimed for patentability, and (2) that the sub-combination has utility by itself or in other combinations (MPEP § 806.05(c)). In the instant case, the combination as claimed does not require the particulars of the sub-combination as claimed. Sub-combination I has separate utility such as monitoring thermal status of a plurality of memory devices and reordering memory accesses to the plurality of memory devices. Sub-combination II has a separate utility such as monitoring thermal status of a single memory device, migrating data to different regions of the memory device, and updating a virtual address mapping. The examiner has required restriction between combination and sub-combination inventions. Where applicant elects a sub-combination, and claims thereto are subsequently found allowable, any claim(s) depending from or otherwise requiring all the limitations of the allowable sub-combination will be examined for patentability in accordance with 37 CFR 1.104. See MPEP § 821.04(a). Applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or non-statutory double patenting rejections over the claims of the instant application. Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: Each sub-combination has separate, distinct utilities, classified in different classifications as outlined above; and each sub-combination requires different fields of search (e.g. searching different class/subclasses with different search strategies/formulations). 18-22 AIA Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention . The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. 08-23 AIA During a telephone conversation with Howard Hamilton on March 30, 2026 , a provisional election was made without traverse to prosecute the invention of Group I , claim s 1-10 and 16-20 . Affirmation of this election must be made by applicant in replying to this Office action. Claim s 11-15 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention. Claim Objections 07-29-01 AIA Claim s 1 and 16 are objected to because of the following informalities: Claims 1 and 16 similarly recite, “…enqueue the series of memory accesses requests” but should recite, “…enqueue the series of memory access requests” Appropriate correction is required. Claims 1-10 and 16-20 are objected to because Claims 1 and 16 similarly recite, “receive a series of memory access requests …enqueue the series of memory accesses requests …reorder the memory accesses in the series of memory accesses to balance a thermal impact of the memory accesses to the memory devices…” where the claims interchange between “memory access requests” and “memory accesses,” where the claims provides antecedent basis for “a series of memory access requests” but do not provide appropriate antecedent basis for “memory accesses.” For prior art purposes, the Examiner considers the claims recite, “reorder the memory access requests in the series of memory access requests to balance a thermal impact of the accesses to the memory devices…” Dependent claims 2-10 are objected for depending upon rejected independent claim 1, where dependent claims 2, 4, and 9 also refer to reordering “memory accesses” not “memory access requests.” Dependent claims 17-20 are objected for depending upon rejected independent claim 16, with dependent claim 17 also refer to reordering “memory accesses” not “memory access requests.” Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-4, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUNDARAM et al. (US 2017/0060202) in view of Song (US 9,959,936) . As to claim 1, SUNDARAM et al. disclose a graphics processor ( Figure 2, circuit 212, where [0046] notes one or more circuits 212 may be implemented as a graphics processing unit (GPU) ) comprising: a graphics core cluster ( [0046] notes circuit 212 may be a multi-core processor ) including processing resources to execute instructions to perform graphics and compute operations ( [0047] notes one or more circuits 212, e.g. multi-core GPU, to execute machine-readable instruction sets, where, by definition, a multi-core GPU performs graphics and compute operations ); and a memory access pipeline ( e.g. thermal management controller 150 of Figure 1, where [0014] notes thermal management controller 150 may include be a hardwired circuit within a processor, e.g. circuit 212 implemented as a GPU, [0042], [0043] further notes thermal management controller 150 may include one or more dedicated control circuits communicatively coupled to each memory resource 110 and may include one or more configurable circuits capable of reading and executing one or more sets or machine-readable instructions, which may be stored in a storage device or memory integrated with the thermal management controller 150 ) configured to access memory devices ( e.g. memory resources 110A-110n ) on behalf of the graphics core cluster ( e.g. circuit 212 as a multi-core processor )( [0044] notes one or more communications buses may communicably couple the thermal management controller 150 to each of the memory resources 110, e.g. depicted in Figure 1 as three (3) buses communicably couple the thermal management controller 150 to each of the plurality of memory resources 110, where command (CMD) bus 152 permits the thermal management controller 150 to bidirectionally communicate with each of the plurality of memory resources 110, where such commands may include, but are not limited to, commands that limit, alter, adjust, restrict or halt the flow of data to/from memory resources 110 experiencing a high temperature thermal condition ), each of the memory devices having a thermal status ( Figure 1, [0020] notes each of memory resources 110A-110n includes at least one respective comparator 120A-120n that are communicatively coupled to at least one respective thermal sensor 122A-122n which provides a real-time signal that includes information indicative of the temperature of the memory resource 110 to the respective comparator 120, [0021] notes each memory resource 110A-110n further includes data indicative of a respective first, e.g. “HIGH SET,” temperature threshold 112A-112n, and a respective second, e.g. “LOW SET,” temperature threshold 114A-114n, [0022] notes each memory resource 110A-110n further includes a respective first output, e.g. “ALERT” pin 124A-124n, and [0024] notes each memory resource 110A-110n further includes a respective register, e.g. “STATUS REGISTER,” 126A-126n, which provides a data storage area in the memory resource where data indicative or representative of a thermal state of the memory resource 110 may be stored or written ), the memory access pipeline including circuitry ( e.g. thermal management controller 150 including one or more dedicated circuits and/or configurable circuits noted above ) configured to: monitor the thermal status for the memory devices ( [0044] notes an alert bus 154 permits alert signals generated by each of the memory resources 110 to reach the thermal management controller 150, the alert signal can be an unaddressed signal indicative of an occurrence of a high temperature thermal event in one or more of the memory resources 110 and/or thermal management controller 150 may use data accessed via the status bus 156 and/or thermal management controller 150 may access data stored in the register 126 in each of the memory resources 110, where the thermal management controller 150 may, via the status bus 156, bidirectionally communicate with the register 126 in each of the memory resources 110 to identify the memory resource 110 in which the high temperature event has occurred ); and balance a thermal impact of the memory accesses to the memory devices ( [0039], [0040], [0041] notes thermal management controller 150 for controlling, restricting, or otherwise adjusting the flow of data to and/or from each one of some or all of the plurality of memory resources 110 upon receipt of thermal event ). SUNDARAM et al. differ from the invention defined in claim 1 in that SUNDARAM et al. do not disclose its thermal management controller, e.g. memory access pipeline, to “…receive a series of memory access requests to the memory devices; enqueue the series of memory accesses requests to an access request buffer; and reorder the memory accesses in the series of memory accesses to balance a thermal impact of the memory accesses to the memory devices.” Song also discloses a memory access pipeline ( Figure 2, access manager 116 including translation maps 202, heat maps 204, filters 206, sensor interface 208, and access sequencer 210, implemented by processor 102 of Figure 1 ) configured to access memory devices ( column 3, lines 29-31 notes computer-readable medium (CRM) 112 includes volatile memory, no-volatile memory 114, and memory access manager 116, and lines 44-49 further notes non-volatile memory 114 includes solid-state drive 118 (SSD 118) and Flash memory integrated circuit (IC) chip 120 (Flash chip 120) ), each of the memory devices having a thermal status ( e.g. temperature sensors ), the memory access pipeline including circuitry ( perform process 300 of Figure 3 ) configured to: monitor the thermal status for the memory devices ( step 304, column 5, lines 61 thru column 6, lines 4 notes determining respective temperatures of a first location and a second location of a memory device, where column 5, lines 8-11 notes access manager 116 includes heat maps 204, which maintains temperature information for physical locations of a memory device, and lines 21-26 further notes sensor interface 208 enables access manager 116 to receive information from temperature sensors associated with computer-readable medium (CRM) 11 or memory devices thereof ); receive a series of memory access requests to the memory devices ( step 302, column 5, lines 54-60 notes receiving a request to access a memory device, e.g. column 6, lines 32-34 notes example of multiple requests to access memory device may include one or more requests to read data from the memory device ); enqueue the series of memory accesses requests to an access request buffer ( column 5, lines 27-29 notes configured to monitor a queue of memory access requests or memory access commands (e.g. read, write, or erase), thus denoting memory access requests are queued, e.g. buffered ); and reorder the memory accesses [requests] in the series of memory accesses [requests] to balance a thermal impact of the memory accesses to the memory devices ( step 306, column 6, lines 5-19 notes which of two locations to access is selected based on the respective temperatures, step 308, column 6, lines 20-40 notes an order in which to access two locations is determined based on the respective temperatures, e.g. the one or more requests to read data from the memory device, step 310, column 6, lines 41-51 notes accessing the location(s) of the memory device based on the determined order, e.g. such as for requests to read data from the memory device, performance of the access is delayed or re-ordered in the queue effective to access the location based on the determined order, where by doing so, access of the memory device(s) is managed such that a temperature of the memory device is minimized, where column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue ). NOTE: As noted above, CRM 112 include a plurality of memory devices, e.g. SSD 118 and Flash chip, where temperature sensors may be located at each of these memory devices. Therefore, although the steps noted above describes a single memory device, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the steps to be performed on the plurality of memory devices as described, yielding predictable results, without changing the scope of the invention. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify SUNDARAM et al.’s thermal management controller to reorder the memory access requests to balance a thermal impact of the memory accesses to the memory devices as described in Song such that access of the memory device(s) is managed such that a temperature of the memory device is minimized, thus enhancing the performance of the system ( see column 6, lines 41-51 of Song ). As to claim 2, SUNDARAM et al. modified with Song disclose to balance the thermal impact of the memory accesses to the memory devices, the circuitry is configured to reorder the memory accesses based on the thermal status for the memory devices ( modified with Song, e.g. as noted in claim 1, step 308, column 6, lines 20-31 notes determining an order in which to access the locations are based on the respective temperatures of the memory devices ). As to claim 3, SUNDARAM et al. modified with Song disclose the circuitry configured to order a memory access request to a first memory device having a first temperature below one or more accesses to a second memory device having a second temperature that is lower than the first temperature ( modified with Song, e.g. as noted in claim 1, step 306, column 6, lines 5-19 notes determining which of two locations to access is selected based on the respective temperatures, e.g. a cooler of the two locations can be selected such that a data write operation increases the temperature of the cooler location, instead of the hotter location ). As to claim 4, SUNDARAM et al. modified with Song disclose the circuitry including one or more memory controllers coupled with the memory devices ( SUNDARAM, e.g. as noted in claim 1, thermal management controller 150 coupled to each of memory resources 112A-112n; modified with Song, access manager 116 coupled to CRM 112, further to each of non-volatile memory 114 ), the one or more memory controllers to reorder the memory accesses in the series of memory accesses to balance the thermal impact of the memory accesses to the memory devices ( modified with Song, e.g. as noted in claim 1, column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue ). As to claim 6, SUNDARAM et al. modified with Song disclose the circuitry configured to monitor the thermal status for the memory devices via thermal sensors within the memory devices ( SUNDARAM, e.g. as noted in claim 1, each of memory resources 112A-112n comprises thermal sensors 122A-122n; modified with Song, column 5, lines 21-26 notes each of memory devices may include temperature sensors ). As to claim 7, SUNDARAM et al. modified with Song disclose the thermal status for the memory devices includes a thermal status for multiple memory regions of the memory devices ( modified with Song, as noted in claim 1, step 304, column 5, lines 61 thru column 6, lines 4 notes determining respective temperatures of a first location and a second location of the memory device, where column 5, lines 21-26 notes temperature sensors providing information on a per-device, per-block, or per-page resolution ) . 07-22-aia AIA Claim (s) 5 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUNDARAM et al. (US 2017/0060202) in view of Song (US 9,959,936) as applied to claim s 1 and 7 above, and further in view of Arora et al. (US 2016/0086654) . As to claim 5, SUNDARAM et al. modified with Song disclose the circuitry configured to monitor the thermal status for the memory devices ( modified with Song, column 5, lines 8-20 notes access manager 116 includes heat maps 204, which may be provided based on translation maps 202, where heat maps 204 maintain temperature information for physical locations of a memory device, where filters 206 may be applied to heat maps 204 to estimate or predict the dissipation of heat between physical locations of a memory device ), but do not disclose, but Arora et al. disclose the circuitry configured to monitor the thermal status for the memory devices via a thermal model that is based on usage metrics ( [0028]-[0032] notes memory controller 251 utilizes an integrated thermal model to determine the expected thermal level for the physical locations in the structure of processing node 201 and may be used to manage data placement and compute dispatch to minimize a cost function consisting of at least the following dimensions: intra-stack thermal penalty, performance penalty, power penalty, and resilience and reliability, the thermal model may further correlate expected thermal levels with each of a number of locations within the structure of node 201 based on memory activity patterns (read throughput, write throughput, row buffer hit rate and other factors), logic die instructions per cycle (IPC), operating voltage supply levels, processor core frequencies, thermal dissipation capability of cooling components and surfaces, packaging, computation pattern (e.g. integer or floating-point intensive), latency, and other factors ). It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify SUNDARAM et al. modified with Song’s system and method of monitoring thermal status of memory devices with Arora et al.’s method of monitoring the thermal status for the memory devices via a thermal model to minimize cost functions such as thermal penalty, performance penalty, power penalty, and resilience and reliability, thus further enhancing the performance of the system ( see [0028] of Arora et al. ) As to claim 8, SUNDARAM et al. modified with Song disclose the multiple memory regions ( modified with Song, as noted in claim 7, memory devices having multiple locations ), but do not disclose, but Arora et al. disclose the multiple memory regions including multiple memory dies or memory channels ( Figure 2B, [0020] notes multiple memory stacks 210-213, each memory stack 210-213 comprising stacked dies A, B, C, D, and E, where dies 210-213E are logic dies located at the bottoms of memory stacks 210-213, respectively, and the A, B, C, and D dies in each of the stacks 210-213 are memory dies ). It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify SUNDARAM et al. modified with Song’s multiple memory regions to further include multiple memory dies as described by Arora et al. as an alternative form of memory regions, where Arora et al. describes such memory dies are stacked so that they are within close proximity of a processing logic, thus enabling thermal monitoring within such memory dies ( see Background of Arora et al. ). As to claim 9, SUNDARAM et al. modified with Song and Arora et al. disclose the circuitry configured to reorder the memory accesses in the series of memory accesses to balance the thermal impact of the memory accesses to the multiple memory regions of the memory devices ( modified with Song, as noted in claim 1, step 308, column 6, lines 20-40 notes an order in which to access two locations is determined based on the respective temperatures, e.g. the one or more requests to read data from the memory device, step 310, column 6, lines 41-51 notes accessing the location(s) of the memory device based on the determined order, e.g. such as for requests to read data from the memory device, performance of the access is delayed or re-ordered in the queue effective to access the location based on the determined order, where by doing so, access of the memory device(s) is managed such that a temperature of the memory device is minimized, where column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue; further modified with Arora, Figure 3, step 301, [0041] notes memory controller 251 determines an expected thermal level associated with each of a number of locations in the node 201, further to step 305, [0042] notes memory controller 251 determines the type of the received operation, e.g. a processing task or a memory write operation, where if the operation is a memory write operation, proceeding to step 311, [0043], [0044] notes the memory controller 251 calculates the thermal penalty associated with the memory write operation, step 313, [0045], [0046] notes the memory controller 251 determines for the data being placed a probability of concurrent access with other data stored in the memory, step 315, [0047]-[0052] notes the memory controller 251 selects a target location out of multiple available physical locations, then assigns the memory write operation to the target location, and step 317, [0055] notes the memory controller 251 causes the data to be written to the assigned target location as provided by the received operation; and if the operation is a processing task, proceeding to step 321, [0056] notes the memory controller 251 determines the thermal penalty associated with the task, step 323, [0057]-[0060] notes the memory controller 251 identifies one or more available target locations that are a minimum distance away from one or more heat sources in the node 201 where the processing tasks can be executed, step 325, [0061] notes the memory controller 251 assigns the processing task to one of the identified target location of block 323, and step 327, [0060] notes the processing task is dispatched to and executed at the assigned location ). As to claim 10, SUNDARAM et al. modified with Song and Arora et al. disclose the circuitry configured to order a memory access request to a first region of a memory device having a first temperature below one or more accesses to a second region of the memory device having a second temperature that is lower than the first temperature ( modified with Song, e.g. as noted in claim 1, step 306, column 6, lines 5-19 notes determining which of two locations to access is selected based on the respective temperatures, e.g. a cooler of the two locations can be selected such that a data write operation increases the temperature of the cooler location, instead of the hotter location; further modified with Arora, [0048] notes for a memory write operation for which the data is associated with a relatively high thermal penalty, the memory controller 251 may store the data at a physical location having a greater thermal dissipation capability, thus, data associated with a high thermal penalty may be stored at locations closer to cooling components or closer to exposed surfaces of the memory stacks 210-213, as compared to data with a lower thermal penalty, and since a higher access frequency for data results in a correspondingly higher thermal penalty for that data, data that is accessed frequently can be stored at a location that is closer to cooling components and exterior surfaces than data that is less frequently accessed, and [0058] further notes for a processing task, memory controller 251 may select a target location that is a minimum distance away from the location of a concurrently accessed data to avoid the generation of access heat at one location ) . 07-21-aia AIA Claim (s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUNDARAM et al. (US 2017/0060202) in view of Arora et al. (US 2016/0086654) and Song (US 9,959,936) . As to claim 16, SUNDARAM et al. discloses a graphics processing system ( Figure 2, system 200 with one or more circuits 212, where [0046] notes circuit 212 may be implemented as a graphics processing unit (GPU), thus system 200 may be considered a graphics processing system ) comprising: comprising: a first memory device ( e.g. one of memory resources 110A-110n ); a second memory device ( e.g. a different one of memory resources 110A-110n ); a graphics core cluster ( [0046] notes circuit 212 may be a multi-core processor ) including processing resources to execute instructions to perform graphics and compute operations ( [0047] notes one or more circuits 212, e.g. multi-core GPU, to execute machine-readable instruction sets, where, by definition, a multi-core GPU performs graphics and compute operations ); and a memory access pipeline ( e.g. thermal management controller 150 of Figure 1, where [0014] notes thermal management controller 150 may include be a hardwired circuit within a processor, e.g. circuit 212 implemented as a GPU, [0042], [0043] further notes thermal management controller 150 may include one or more dedicated control circuits communicatively coupled to each memory resource 110 and may include one or more configurable circuits capable of reading and executing one or more sets or machine-readable instructions, which may be stored in a storage device or memory integrated with the thermal management controller 150 ) configured to access the first memory device and the second memory device ( e.g. memory resources 110A-110n ) on behalf of the graphics core cluster ( e.g. circuit 212 as a multi-core processor )( [0044] notes one or more communications buses may communicably couple the thermal management controller 150 to each of the memory resources 110, e.g. depicted in Figure 1 as three (3) buses communicably couple the thermal management controller 150 to each of the plurality of memory resources 110, where command (CMD) bus 152 permits the thermal management controller 150 to bidirectionally communicate with each of the plurality of memory resources 110, where such commands may include, but are not limited to, commands that limit, alter, adjust, restrict or halt the flow of data to/from memory resources 110 experiencing a high temperature thermal condition ), the first memory device and the second memory device each having a thermal status ( Figure 1, [0020] notes each of memory resources 110A-110n includes at least one respective comparator 120A-120n that are communicatively coupled to at least one respective thermal sensor 122A-122n which provides a real-time signal that includes information indicative of the temperature of the memory resource 110 to the respective comparator 120, [0021] notes each memory resource 110A-110n further includes data indicative of a respective first, e.g. “HIGH SET,” temperature threshold 112A-112n, and a respective second, e.g. “LOW SET,” temperature threshold 114A-114n, [0022] notes each memory resource 110A-110n further includes a respective first output, e.g. “ALERT” pin 124A-124n, and [0024] notes each memory resource 110A-110n further includes a respective register, e.g. “STATUS REGISTER,” 126A-126n, which provides a data storage area in the memory resource where data indicative or representative of a thermal state of the memory resource 110 may be stored or written ), and the memory access pipeline including circuitry ( e.g. thermal management controller 150 including one or more dedicated circuits and/or configurable circuits noted above ) configured to: monitor the thermal status for the memory devices ( [0044] notes an alert bus 154 permits alert signals generated by each of the memory resources 110 to reach the thermal management controller 150, the alert signal can be an unaddressed signal indicative of an occurrence of a high temperature thermal event in one or more of the memory resources 110 and/or thermal management controller 150 may use data accessed via the status bus 156 and/or thermal management controller 150 may access data stored in the register 126 in each of the memory resources 110, where the thermal management controller 150 may, via the status bus 156, bidirectionally communicate with the register 126 in each of the memory resources 110 to identify the memory resource 110 in which the high temperature event has occurred ); and balance a thermal impact of the memory accesses to the memory devices ( [0039], [0040], [0041] notes thermal management controller 150 for controlling, restricting, or otherwise adjusting the flow of data to and/or from each one of some or all of the plurality of memory resources 110 upon receipt of thermal event ). SUNDARAM et al. differ from the invention defined in claim 16 in that SUNDARAM et al. disclose a first memory device and a second memory device, but do not disclose “…a first memory device including a first base die and first memory dies stacked on the first base die; and a second memory device including a second base die and second memory dies stacked on the second base die…” SUNDARAM et al. further differ from the invention defined in claim 16 in that SUNDARAM et al. do not disclose its thermal management controller, e.g. memory access pipeline to “…receive a series of memory access requests to the first memory device and the second memory device; enqueue the series of memory accesses requests to an access request buffer; and reorder the memory accesses in the series of memory accesses to balance thermal impact of the memory accesses to the first memory device and the second memory device.” Arora et al. disclose a first memory device ( Figure 2B, one of memory stacks 210-213 ) including a first base die ( respective logic dies 210-213E ) and first memory dies ( respective memory dies 210-213A, 210-213B, 210-213C, and 210-213D ) stacked on the first base die ( [0020] notes multiple memory stacks 210-213, each memory stack 210-213 comprising stacked dies A, B, C, D, and E, where dies 210-213E are logic dies located at the bottoms of memory stacks 210-213, respectively, and the A, B, C, and D dies in each of the stacks 210-213 are memory dies ); a second memory device ( a different one of memory stacks 210-213 ) including a second base die ( respective logic dies 210-213E ) and second memory dies ( respective memory dies 210-213A, 210-213B, 210-213C, and 210-213D ) stacked on the second base die ( [0020] notes multiple memory stacks 210-213, each memory stack 210-213 comprising stacked dies A, B, C, D, and E, where dies 210-213E are logic dies located at the bottoms of memory stacks 210-213, respectively, and the A, B, C, and D dies in each of the stacks 210-213 are memory dies ). Arora et al. further disclose a memory access pipeline ( memory controller 251, implemented in host processor 250 ) configured to access the first memory device ( e.g. one of memory stacks 210-213 ) and the second memory device ( e.g. a different one of memory stacks 210-213 ), the first memory device and the second memory device each having a thermal status ( [0039] notes each of memory stacks have thermal sensors 220-223 attached to measure actual temperatures of memory stacks 210-213 ), and the memory access pipeline including circuitry ( memory controller 251, implemented in host processor 250, [0024] notes memory controller further includes control logic for performing thermal management of the memory via data placement and compute dispatch scheme )( placement process 300 ) configured to: monitor the thermal status for the first memory device and the second memory device ( step 301, [0041] notes memory controller 251 determines an expected thermal level associated with each of a number of locations in the node 201 ); receive a series of memory access requests to the first memory device and the second memory device ( step 303, [0042] notes memory controller 251 receives an operation to be placed in the processing node 201 ); enqueue the series of memory accesses requests to an access request buffer ( [0042] notes the received operations may be one of several queued operations that are pending placement in the node 201 ); and reorder the memory accesses in the series of memory accesses to balance thermal impact of the memory accesses to the first memory device and the second memory device ( step 305, [0042] notes memory controller 251 determines the type of the received operation, e.g. a processing task or a memory write operation, where if the operation is a memory write operation, proceeding to step 311, [0043], [0044] notes the memory controller 251 calculates the thermal penalty associated with the memory write operation, step 313, [0045], [0046] notes the memory controller 251 determines for the data being placed a probability of concurrent access with other data stored in the memory, step 315, [0047]-[0052] notes the memory controller 251 selects a target location out of multiple available physical locations, then assigns the memory write operation to the target location, and step 317, [0055] notes the memory controller 251 causes the data to be written to the assigned target location as provided by the received operation; and if the operation is a processing task, proceeding to step 321, [0056] notes the memory controller 251 determines the thermal penalty associated with the task, step 323, [0057]-[0060] notes the memory controller 251 identifies one or more available target locations that are a minimum distance away from one or more heat sources in the node 201 where the processing tasks can be executed, step 325, [0061] notes the memory controller 251 assigns the processing task to one of the identified target location of block 323, and step 327, [0060] notes the processing task is dispatched to and executed at the assigned location ). It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify SUNDARAM et al. modified with Song’s multiple memory regions to further include multiple memory dies as described by Arora et al. as an alternative form of memory regions, where Arora et al. describes such memory dies are stacked so that they are within close proximity of a processing logic, thus enabling thermal monitoring within such memory dies ( see Background of Arora et al. ). SUNDARAM et al. modified with Arora et al. do not explicitly disclose “…reorder the memory access [requests] in the series of memory access [requests] to balance a thermal impact of the accesses to the memory devices…” Song also discloses a memory access pipeline ( Figure 2, access manager 116 including translation maps 202, heat maps 204, filters 206, sensor interface 208, and access sequencer 210, implemented by processor 102 of Figure 1 ) configured to access memory devices ( column 3, lines 29-31 notes computer-readable medium (CRM) 112 includes volatile memory, no-volatile memory 114, and memory access manager 116, and lines 44-49 further notes non-volatile memory 114 includes solid-state drive 118 (SSD 118) and Flash memory integrated circuit (IC) chip 120 (Flash chip 120) ), each of the memory devices having a thermal status ( e.g. temperature sensors ), the memory access pipeline including circuitry ( perform process 300 of Figure 3 ) configured to: monitor the thermal status for the memory devices ( step 304, column 5, lines 61 thru column 6, lines 4 notes determining respective temperatures of a first location and a second location of a memory device, where column 5, lines 8-11 notes access manager 116 includes heat maps 204, which maintains temperature information for physical locations of a memory device, and lines 21-26 further notes sensor interface 208 enables access manager 116 to receive information from temperature sensors associated with computer-readable medium (CRM) 11 or memory devices thereof ); receive a series of memory access requests to the memory devices ( step 302, column 5, lines 54-60 notes receiving a request to access a memory device, e.g. column 6, lines 32-34 notes example of multiple requests to access memory device may include one or more requests to read data from the memory device ); enqueue the series of memory accesses requests to an access request buffer ( column 5, lines 27-29 notes configured to monitor a queue of memory access requests or memory access commands (e.g. read, write, or erase), thus denoting memory access requests are queued, e.g. buffered ); and reorder the memory access [requests] in the series of memory access [requests] to balance a thermal impact of the accesses to the memory devices ( step 306, column 6, lines 5-19 notes which of two locations to access is selected based on the respective temperatures, step 308, column 6, lines 20-40 notes an order in which to access two locations is determined based on the respective temperatures, e.g. the one or more requests to read data from the memory device, step 310, column 6, lines 41-51 notes accessing the location(s) of the memory device based on the determined order, e.g. such as for requests to read data from the memory device, performance of the access is delayed or re-ordered in the queue effective to access the location based on the determined order, where by doing so, access of the memory device(s) is managed such that a temperature of the memory device is minimized, where column 5, lines 29-32 notes access sequencer 210 enables access manager 116 to manage a sequence or order in which the memory access requests or commands are performed, such as by altering their respective positions in the queue ). NOTE: As noted above, CRM 112 include a plurality of memory devices, e.g. SSD 118 and Flash chip, where temperature sensors may be located at each of these memory devices. Therefore, although the steps noted above describes a single memory device, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the steps to be performed on the plurality of memory devices as described, yielding predictable results, without changing the scope of the invention. It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify SUNDARAM et al. modified with Arora et al.’s thermal management controller to reorder the memory access requests to balance a thermal impact of the memory accesses to the memory devices as described in Song such that access of the memory device(s) is managed such that a temperature of the memory device is minimized, thus enhancing the performance of the system ( see column 6, lines 41-51 of Song ). As to claim 17, SUNDARAM et al. modified with Arora et al. and Song disclose to balance the thermal impact of the memory accesses to the first memory device and the second memory device, the circuitry is configured to reorder the memory accesses based on the thermal status for the first memory device and the second memory device ( further modified with Song, e.g. as noted in claim 16, step 308, column 6, lines 20-31 notes determining an order in which to access the locations are based on the respective temperatures of the memory devices ), including to order a memory access request to the first memory device below an access to the second memory device in response to a determination that a temperature of the second memory device is lower than the temperature of the second memory device ( further modified with Song, e.g. as noted in claim 16, step 306, column 6, lines 5-19 notes determining which of two locations to access is selected based on the respective temperatures, e.g. a cooler of the two locations can be selected such that a data write operation increases the temperature of the cooler location, instead of the hotter location; modified with Arora, [0048] notes for a memory write operation for which the data is associated with a relatively high thermal penalty, the memory controller 251 may store the data at a physical location having a greater thermal dissipation capability, thus, data associated with a high thermal penalty may be stored at locations closer to cooling components or closer to exposed surfaces of the memory stacks 210-213, as compared to data with a lower thermal penalty, and since a higher access frequency for data results in a correspondingly higher thermal penalty for that data, data that is accessed frequently can be stored at a location that is closer to cooling components and exterior surfaces than data that is less frequently accessed, and [0058] further notes for a processing task, memory controller 251 may select a target location that is a minimum distance away from the location of a concurrently accessed data to avoid the generation of access heat at one location ). As to claim 18, SUNDARAM et al. modified with Arora et al. and Song disclose the first base die including first control logic to control access to the first memory dies and the second base die including second control logic to control access to the second memory dies ( modified with Arora, [0024] notes memory controller 251, implemented in the host processor, includes control logic for performing thermal management of the memory via a data placement and compute dispatch scheme, where as an embodiment, memory controller functions may be implemented in the logic dies E instead of host processor, thus would be respective memory controllers in each logic die, e.g. at least a first control logic and a second control logic ). As to claim 19, SUNDARAM et al. modified with Arora et al. and Song disclose the first control logic is to balance memory accesses between the first memory dies based on the thermal status of the first memory dies and the second control logic is to balance accesses between the second memory dies based on the thermal status of the second memory dies ( modified with Arora, e.g. as noted in claim 18, a first memory controller including control logic, e.g. first control logic, and a second memory controller including control logic, e.g. a second control logic, where [0023] notes control logic for a node 201 implements such a scheme may model or dynamically monitor the thermal levels of multiple locations in the memory stacks 210-213, then assign pending operations to locations in the memory stacks based on the expected thermal level at those locations and the expected thermal penalties that will be incurred by the operations ). As to claim 20, SUNDARAM et al. modified with Arora et al. and Song disclose the first control logic ( modified with Arora, e.g. as noted in claims 18 and 19, a first control logic ) is to balance accesses between a first plurality of memory channels of the first memory dies based on the thermal status of the first plurality of memory channels ( modified with Arora, e.g. as noted in claim 19, control logic dynamically monitor the thermal levels of multiple locations in the memory stacks 210-213, then assign pending operations to locations in the memory stacks based on the expected thermal level at those locations and the expected thermal penalties that will be incurred by the operations, where the multiple locations may be considered “a first plurality of memory channels” ) and the second control logic ( modified with Arora, e.g. as noted in claims 18 and 19, a second control logic ) is to balance accesses between a second plurality of memory channels of the second memory dies based on the thermal status of the second plurality of memory channels ( modified with Arora, e.g. as noted in claim 19, control logic dynamically monitor the thermal levels of multiple locations in the memory stacks 210-213, then assign pending operations to locations in the memory stacks based on the expected thermal level at those locations and the expected thermal penalties that will be incurred by the operations, where the multiple locations may be considered “a second plurality of memory channels” ) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. ROTITHOR (US 2009/0248976) disclose a multi-core processing system and method of memory throttling to improve power/performance, the method includes scheduling memory access requests by prioritizing cache bound memory requests over DRAM bound memory requests in response to certain thermal conditions. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, King Y. Poon can be reached at (571)272-7440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617 Application/Control Number: 18/791,963 Page 2 Art Unit: 2617 Application/Control Number: 18/791,963 Page 3 Art Unit: 2617 Application/Control Number: 18/791,963 Page 4 Art Unit: 2617 Application/Control Number: 18/791,963 Page 5 Art Unit: 2617 Application/Control Number: 18/791,963 Page 6 Art Unit: 2617 Application/Control Number: 18/791,963 Page 7 Art Unit: 2617 Application/Control Number: 18/791,963 Page 8 Art Unit: 2617 Application/Control Number: 18/791,963 Page 9 Art Unit: 2617 Application/Control Number: 18/791,963 Page 10 Art Unit: 2617 Application/Control Number: 18/791,963 Page 11 Art Unit: 2617 Application/Control Number: 18/791,963 Page 12 Art Unit: 2617 Application/Control Number: 18/791,963 Page 13 Art Unit: 2617 Application/Control Number: 18/791,963 Page 14 Art Unit: 2617 Application/Control Number: 18/791,963 Page 15 Art Unit: 2617 Application/Control Number: 18/791,963 Page 17 Art Unit: 2617 Application/Control Number: 18/791,963 Page 18 Art Unit: 2617 Application/Control Number: 18/791,963 Page 19 Art Unit: 2617 Application/Control Number: 18/791,963 Page 20 Art Unit: 2617 Application/Control Number: 18/791,963 Page 21 Art Unit: 2617 Application/Control Number: 18/791,963 Page 22 Art Unit: 2617 Application/Control Number: 18/791,963 Page 23 Art Unit: 2617 Application/Control Number: 18/791,963 Page 24 Art Unit: 2617 Application/Control Number: 18/791,963 Page 25 Art Unit: 2617 Application/Control Number: 18/791,963 Page 26 Art Unit: 2617
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