DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 20 is rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 20 recites the limitation "the memory system" in line 2. There is insufficient antecedent basis for this limitation in the claim because there is no first instance of ‘a memory system.’
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 10, 13-14, 16-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Winter et al. (US Pub. No. 2015/0117448), hereinafter referred to as Winter.
Referring to claim 1, Winter discloses a memory device (fig. 1-3, [0012-0015]), comprising: an input/output data interface configured to couple to a data bus and communicate data via the data bus (one or more buses operable to transmit communications, [0012]); and a data processor (fig. 1, processor 102) coupled to the input/output data interface, wherein the data processor has a device Internet Protocol (IP) address (IHS IP address, [0021]), wherein the data processor is configured to: generate first payload data having a Transmission Control Protocol/Internet Protocol (TCP/IP) packet format (TCP/IP data, [0021]), the first payload data including at least one of the device IP address of the data processor and a target IP address of a host device (the destination IHS IP address 604a (e.g., "100.1.1.1") in the data packet, [0022]); convert the first payload data to output data having a Peripheral Component Interconnect Express (PCIe) packet format (TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]); and provide the output data to the input/output data interface for communicating the output data via the data bus (exchanging writes between the two endpoints (e.g., the source IHS and the destination IHS), [0024]).
As to claim 2, Winter discloses the data processor is configured to: obtain input data having the PCIe packet format (local communications are conducted between IHSs connected via a PCIe system and without the need to traverse a layer-2 network, PCIe is the only protocol required, [0019]), the input data including the device IP address, wherein the input data is provided via the input/output data interface (an IP address with a PCIe associated IP subnet)…PCIe addressable write buffers may then be allocated and reserved on both sides of the connection…proceed with TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]); and convert the input data to second payload data having a TCP/IP package format (data packet 600 also includes application data 608 that is being communicated from the source IHS to the destination IHS. The data packet 600 provides…TCP/IP data, [0021]; NOTE: Winter teaches the applications of the IHS operating according to TCP/IP, which implies the data converted from the PCIe tunnelling to TCP/IP for application operations).
As to claim 3, Winter discloses the data bus is configured to communicate data between the input/output data interface and the host device according to a PCIe interface standard (local communications are conducted between IHSs connected via a PCIe system and without the need to traverse a layer-2 network, PCIe is the only protocol required, [0019]).
Referring to claim 10, Winter discloses a method of creating a virtual communication link between computing elements (server IHS to server IHS local communication…local communication involve tunneling, [0019]), comprising: at a memory device (fig. 1-3, [0012-0015]) including an input/output data interface configured to couple to a data bus and communicate data via the data bus (one or more buses operable to transmit communications, [0012]), and a data processor (fig. 1, processor 102) coupled to the input/output data interface, wherein the data processor has a device Internet Protocol (IP) address (IHS IP address, [0021]), by the data processor: generating first payload data having a Transmission Control Protocol/Internet Protocol (TCP/IP) packet format (TCP/IP data, [0021]), the first payload data including at least one of the device IP address of the data processor and a target IP address of a host device (the destination IHS IP address 604a (e.g., "100.1.1.1") in the data packet, [0022]); converting the first payload data to output data having a Peripheral Component Interconnect Express (PCIe) packet format (TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]); and providing the output data to the input/output data interface for communicating the output data via the data bus (exchanging writes between the two endpoints (e.g., the source IHS and the destination IHS), [0024]).
As to claim 13, Winter discloses the data processor is coupled to a virtual link (server IHS to server IHS local communication…local communication involve tunneling, [0019]), the method further comprising: bidirectionally transferring TCP/IP packets by the virtual link according to a TCP/IP addressing protocol (an IP address with a PCIe associated IP subnet)…PCIe addressable write buffers may then be allocated and reserved on both sides of the connection…proceed with TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]).
As to claim 14, Winter discloses the data processor is communicatively coupled to a cluster of processors of external devices distinct from the memory device (component interconnect system 206 may be coupled to a network 208 to, for example, provide for the communication of the IHSs 202 with IHSs that are connected to the network 208, [0014]), and each of the cluster of processors has a respective IP address (IHS IP address, [0021]), the method further comprising: at the data processor, exchanging TCP/IP packets with each processor of the cluster of processors (IP address subnet for the IHSs 202/server IHSs 304 that are coupled to the ports 406a-d such that local data packets exchanged between the IHSs 202/server IHSs 304 may be distinguished from data packets destined for IHSs connected to the network 208, [0018]).
As to claim 16, Winter discloses at the data bus, communicating data according to a PCIe interface standard without using an ethernet cable (a plurality of server IHSs 304 are communicatively coupled together in a server rack or chassis via PCIe connections to a rack switch 306…without the need for a layer-2/data link layer protocol such as Ethernet., [0015]).
As to claim 17, Winter discloses at the data processor: obtaining input data having the PCIe packet format (local communications are conducted between IHSs connected via a PCIe system and without the need to traverse a layer-2 network, PCIe is the only protocol required, [0019]), the input data including the device IP address, wherein the input data is provided via the input/output data interface (an IP address with a PCIe associated IP subnet)…PCIe addressable write buffers may then be allocated and reserved on both sides of the connection…proceed with TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]); and converting the input data to second payload data having a TCP/IP package format (data packet 600 also includes application data 608 that is being communicated from the source IHS to the destination IHS. The data packet 600 provides…TCP/IP data, [0021]; NOTE: Winter teaches the applications of the IHS operating according to TCP/IP, which implies the data converted from the PCIe tunnelling to TCP/IP for application operations).
As to claim 18, Winter discloses communicating data between the input/output data interface and the host device by the data bus according to a PCIe interface standard (local communications are conducted between IHSs connected via a PCIe system and without the need to traverse a layer-2 network, PCIe is the only protocol required, [0019]).
Referring to claim 20, Winter discloses a non-transitory computer-readable storage medium, having instructions stored thereon, which when executed by a memory device (fig. 1-3, [0012-0015]) cause the memory system to: at a data processor (fig. 1, processor 102) of the memory device, wherein the memory device includes an input/output data interface configured to couple to a data bus and communicate data via the data bus (one or more buses operable to transmit communications, [0012]), and the data processor is coupled to the input/output data interface and has a device Internet Protocol (IP) address (IHS IP address, [0021]): generate first payload data having a Transmission Control Protocol/Internet Protocol (TCP/IP) packet format (TCP/IP data, [0021]), the first payload data including at least one of the device IP address of the data processor and a target IP address of a host device (the destination IHS IP address 604a (e.g., "100.1.1.1") in the data packet, [0022]); convert the first payload data to output data having a Peripheral Component Interconnect Express (PCIe) packet format (TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]); and provide the output data to the input/output data interface for communicating the output data via the data bus (exchanging writes between the two endpoints (e.g., the source IHS and the destination IHS), [0024]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 9, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Winter in view of Ramaswamy et al. (US Pub. No. 2018/0189225), hereinafter referred to as Ramaswamy.
As to claims 4 and 19, while Winter discloses the input/output data interface, the data processor, and the step to send the output data to the host device via the input/output data interface, Winter does not appear to explicitly disclose a memory controller distinct from the data processor and configured to send the output data.
However, Ramaswamy discloses a memory controller distinct from the data processor and configured to send the output data (fig. 3, memory controller 320, [0035]).
Winter and Ramaswamy are analogous art because they are from the same field of endeavor, IHS architecture and operation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Winter and Ramaswamy before him or her, to modify the IHS of Winter to include the memory controller of Ramaswamy because, though Winter is silent regarding a memory controller, memory controllers a common component of IHS architecture and memory operations, which Ramaswamy demonstrates. Accordingly, the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; in combination, each element merely performs the same function as it does separately; and ne of ordinary skill in the art would have recognized that the results of the combination is a predictable memory access architecture.
The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A).
Therefore, it would have been obvious to combine Winter and Ramaswamy to obtain the invention as specified in the instant claim.
As to claim 9, Winter discloses a non-volatile memory coupled to the data processor (Programs and data are stored on a mass storage device 108, which is coupled to processor 102. Examples of mass storage devices may include hard discs, optical disks, magneto-optical discs, solid-state storage devices, [0013]) and including a plurality of memory blocks, wherein a subset of the plurality of memory blocks is reserved for the data processor (storage device 108…includes instruction that, when executed by the at least one processor, cause the at least one processor to provide a routing engine 404 that is configured to perform the functions of the routing engines and/component interconnect systems discussed herein, [0016]).
Winter does not appear to explicitly disclose the memory controller.
However, Ramaswamy discloses a memory controller distinct from the data processor and configured to send the output data (fig. 3, memory controller 320, [0035]).
The rationale to support a conclusion that the claim would have been obvious remains as indicated above.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Winter in view of Ramaswamy, as applied to claim 4, 9, and 19 above, further in view of Nemiroff et al. (US Pub. No. 2011/0320777), hereinafter referred to as Nemiroff.
As to claim 5, Winter discloses a memory buffer coupled to the data processor, wherein: the memory buffer includes a first buffer portion allocated to the data processor, the first buffer portion configured to store the output data (addressable write buffers may then be allocated and reserved on both sides of the connection for the session duration, [0024]).
Winter does not appear to explicitly disclose the memory controller and a second buffer portion allocated to the memory controller and the memory controller is configured to move the output data stored in the first buffer portion to the second buffer portion before sending the output data to the input/output data interface.
However, Ramaswamy disclose the memory controller and sending the output data to the input/output data interface (fig. 3, memory controller 320, [0035]).
Furthermore, Nemiroff discloses a pipeline buffer architecture which provides a second buffer portion and moving the output data stored in the first buffer portion to the second buffer portion before sending the output data (fig. 2, HW buffers 210, Output buffers 200, [0026-0030]).
Winter, Ramaswamy, and Nemiroff are analogous art because they are from the same field of endeavor, data transmission operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Winter, Ramaswamy, and Nemiroff before him or her, to modify the IHS of Winter to include the buffer architecture of Nemiroff because the buffers would support pipeline data transfer operations.
The suggestion/motivation for doing so would have been improve performance (Nemiroff: [0016]).
Therefore, it would have been obvious to combine Winter, Ramaswamy, and Nemiroff to obtain the invention as specified in the instant claim.
Claims 6-8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Winter in view of Ramaswamy, as applied to claim 4, 9, and 19 above, further in view of Kim et al. (US Pub. No. 2021/0209047), hereinafter referred to as Kim.
As to claim 6, Winter discloses to receive input data having the PCIe packet format from the input/output data interface, store the input data in a memory buffer (an IP address with a PCIe associated IP subnet)…PCIe addressable write buffers may then be allocated and reserved on both sides of the connection…proceed with TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]).
Winter does not appear to explicitly disclose the memory controller and send an incoming notification to the data processor.
However, as indicated in the rejections above, Ramaswamy discloses the memory controller (fig. 3, memory controller 320, [0035]).
Furthermore, Kim teaches a data buffering coordination architecture including sending an incoming notification to the data processor (a hardware interrupt mechanism to notify the MCN processor 150 of any received packet in the RX buffer 186 of the local buffer 180, [0057]).
Winter, Ramaswamy, and Kim are analogous art because they are from the same field of endeavor, data transmission operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Winter, Ramaswamy, and Kim before him or her, to modify the IHS of Winter in view of Ramaswamy to include interrupt mechanism of Kim because the interrupts would coordinate processing of incoming data.
The suggestion/motivation for doing so would have been to optimize the processing of data transfers (Kim: [0103]).
Therefore, it would have been obvious to combine Winter, Ramaswamy, and Kim to obtain the invention as specified in the instant claim.
As to claim 7, Winter discloses the data processor is configured to obtain the input data from the memory buffer (PCIe addressable write buffers may then be allocated and reserved on both sides of the connection…proceed with TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]) and convert the input data to second payload data having the TCP/IP packet format (data packet 600 also includes application data 608 that is being communicated from the source IHS to the destination IHS. The data packet 600 provides…TCP/IP data, [0021]; NOTE: Winter teaches the applications of the IHS operating according to TCP/IP, which implies the data converted from the PCIe tunnelling to TCP/IP for application operations), the second payload data including at least the device IP address (an IP address with a PCIe associated IP subnet), [0024]).
As to claim 8, while Winter discloses the memory buffer, Winter is silent regarding the specific architecture of the memory buffer and therefore does not appear to explicitly disclose an outgoing buffer portion configured to store the output data and a receiving buffer portion configured to store the input data. However, Kim discloses an outgoing buffer portion configured to store the output data and a receiving buffer portion configured to store the input data (fig. 1C, local buffer 180, TX 184, RX 186). The suggestion/motivation to combine remains as indicated above.
As to claim 15, Winter does not appear to explicitly disclose at the data processor, operating according to a notification mechanism including at least one of interrupt, polling, or doorbell. However, Kim discloses at the data processor, operating according to a notification mechanism including at least one of interrupt (a hardware interrupt mechanism to notify the MCN processor 150 of any received packet in the RX buffer 186 of the local buffer 180, [0057]). The suggestion/motivation to combine remains as indicated above.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Winter in view of Jaliminche et al. (US Pub. No. 2024/0281354), hereinafter referred to as Jaliminche.
As to claim 11, Winter discloses the data processor (fig. 1, processor 102) and converting data between TCP/IP packets and PCIe packets (TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]).
While Winter anticipates the IHS operating a variety of software components, of which operating systems are common, Winter is silent regarding an operating system and a storage-side kernel.
However, Jaliminche discloses an operating system and a storage-side kernel (operating system…. kernel is executed in the computational storage device, [0038-0039]).
Winter and Jaliminche are analogous art because they are from the same field of endeavor, data processing and storing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Winter and Jaliminche before him or her, to modify the IHS of Winter to include the OS/kernel architecture of Winter and Jaliminche in order to provide improved compute performance.
The suggestion/motivation for doing so would have been to optimize compute performance (Jaliminche: [0036]).
Therefore, it would have been obvious to combine Winter and Jaliminche to obtain the invention as specified in the instant claim.
As to claim 12, Winter discloses a relay application and relaying TCP/IP packets according to a PCIe interface standard on the host side (data packet 600 also includes application data 608 that is being communicated from the source IHS to the destination IHS. The data packet 600 provides…TCP/IP data, [0021]; PCIe addressable write buffers may then be allocated and reserved on both sides of the connection…proceed with TCP/IP packets encapsulated within the PCIe TLP/DLP packets, [0024]).
Winter does not appear to explicitly disclose executing the operating system by the host device on a host side, wherein the host device further includes a host-side kernel.
However, Jaliminche discloses executing the operating system by the host device on a host side, wherein the host device further includes a host-side kernel (the kernel when executed in the host…operating system, [0038-0039]).
The suggestion/motivation to combine remains as indicated above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2011/0202701 of Maitra et al. is pertinent to transferring TCP/IP packets over a PCIe connection.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184