Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to claims filed on August 1, 2024. Claims 1-15 are pending and presented for examination.
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Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the European Patent Office on August 7, 2023. It is noted, however, that applicant has not filed a certified copy of the European application No. EP23190039.0 as required by 37 CFR 1.55. The U.S. Patent office attempted retrieval of foreign priority document on January 7, 2025 but was unable to retrieve the foreign priority document.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al “Wang”, US-PGPub. No. 20230155732 in view of Lei et al “Lei”, US-PGPub. No. 20230064912.
As per claims 1 and 13-15, Wang teaches an optical line terminal, methods and an optical network unit, ONU, configured to transmit data to an optical line terminal, OLT, during upstream timeslots within a passive optical network (Fig. 1, Paragraph(s) [0003], [0054-0056]; Wang illustrates various optical network elements are shown on Fig. 1);
wherein the ONU comprises a scrambler circuitry configured to scramble at least one data stream according to a periodic scrambling pattern (Fig. 2, Paragraph(s) [0064], [0094]; generating a preload pattern of a scrambler based on a target bit and scrambling the raw data based on the preload pattern to obtain the target data (see Paragraph(s) [0078]). It is further noted that Wang teaches that during upstream data transmission, each ONU sends upstream data to the OLT in a specific timeslot according to a sending rule of time division multiplexing (TDM) (see Paragraph(s) [0004]), and a descrambler circuitry configured to descramble the at least one scrambled data stream according to the periodic scrambling pattern (Fig. 10, Paragraph(s) [0005]; providing a data scrambling method, a data descrambling method and a related device. In further details, Wang teaches generating a preload pattern of a descrambler based on a target bit (see Paragraph [0088]) and descrambling the target data based on the preload pattern to obtain the raw data (see Paragraph [0091])); and
wherein the ONU further comprises at least one data channel for exchanging the at least one scrambled data stream between the scrambler circuitry and the descrambler circuitry (Fig. 14, Paragraph(s) [0097-0098]; the laser 1402 is configured to convert an electrical signal output by the MAC chip 1401 into an optical signal. The wavelength division multiplexing apparatus 1403 is configured to perform multiplexing on a to-be-sent optical signal, and the wavelength division multiplexing apparatus 1403 is further configured to perform demultiplexing on a received optical signal. In addition, Wang teaches after scrambled data reaches a data receiving end, descrambling needs to be performed on the scrambled data to restore raw data (Paragraph(s) [0084])); and wherein the scrambler circuitry is further configured to perform, during a period between the upstream timeslots (Paragraph(s) [0056]).
Wang fails to explicitly teach but Lei teaches scrambling a reference sequence according to the periodic scrambling pattern, thereby obtaining a scrambled reference sequence and sending the scrambled reference sequence to the descrambler circuitry over the at least one data channel (Paragraph(s) [0035]; the repetition component 198 of the UE 110 may include a generation component 224 configured to generate scrambling IDs and/or scrambling sequences. The UE 110 may include a scrambling/descrambling component 226 configured to scramble a bit sequence using a scrambling sequence (e.g., using an XOR operator). In further details, Lei teaches generating a first scrambling identification (ID), generating a first scrambling sequence based on the first scrambling ID, scrambling a first set of information based on the first scrambling sequence to generate a first plurality of information bits, generating a plurality of repeated copies of the first plurality of information bits scrambled using the first scrambling sequence, and transmitting a first transmission burst including each of the plurality of repeated copies of the first plurality of information bits on different ones of a first plurality of resources in a communication channel (Paragraph(s) [0006]). In addition, Lei teaches when acting as a receiver device, the scrambling/descrambling component 226 is configured to descramble a transmission that includes duplicated or repeated copies of information scrambled with the same scrambling sequence by applying a same descrambling sequence to the information (Paragraph(s) [0046]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the applicants' invention to combine the teachings of Wang and Lei in order to provide security and efficiency to data being exchanged among various communication systems.
As per claim 2, Wang teaches wherein the reference sequence is a sequence of bits that have the same logical value (Paragraph(s) [0075], [0079]).
As per claim 3, Wang teaches wherein the descrambler circuitry is further configured to perform, determining the periodic scrambling pattern for descrambling the at least one scrambled data stream based on the scrambled reference sequence and the reference sequence (Paragraph(s) [0019], [0090]).
As per claim 4, Wang teaches wherein the descrambler circuitry is further configured to perform, capturing at least a portion of the scrambled reference sequence within at least one capture buffer (Fig. 15, Paragraph(s) [0029], [0099]).
As per claim 5, Wang teaches wherein determining the periodic scrambling pattern is based on the captured portion of the scrambled reference sequence and the reference sequence (Paragraph(s) [0019], [0075]).
As per claim 6, Wang teaches wherein the periodic scrambling pattern has a pattern length, and the at least one capture buffer has a buffer size; and wherein the buffer size is an integer multiple of the pattern length (Paragraph(s) [0080]).
As per claim 7, Wang teaches wherein the scrambler circuitry further comprises a controller configured to perform, during the period between upstream timeslots, sending a control signal to the descrambler circuitry indicative of that the scrambler circuitry is sending the scrambled reference sequence to the descrambler circuitry over the at least one data channel (Paragraph(s) [0004], [0056], [0092]).
As per claim 8, Wang teaches wherein the scrambler circuitry is further configured to perform adjusting the periodic scrambling pattern between the end of an upstream timeslot and the control signal that follows the upstream timeslot (Paragraph(s) [0079-0080]).
As per claim 9, Wang teaches wherein the adjusting is based on data expected to be transmitted from the ONU to the OLT within a next upstream timeslot (Paragraph(s) [0080], [0092]).
As per claim 10, Wang teaches wherein the descrambler circuitry is further configured to perform detecting bit errors by comparing the determined periodic scrambling pattern with one or more previously determined periodic scrambling patterns (Paragraph(s) [0005], [0062]).
As per claim 11, Wang teaches wherein the descrambler circuitry is further configured to perform detecting bit errors by descrambling the scrambled reference sequence according to the periodic scrambling pattern determined by the descrambler circuitry (Paragraph(s) [0052], [0058], [0062]).
As per claim 12, Wang teaches wherein the scrambler circuitry is included in a first circuitry of the ONU configured to process the at least one data stream; and wherein the descrambling circuitry is included in a second circuitry of the ONU configured to interface with an optical fibre of the passive optical network to transmit the data to the optical line terminal (Paragraph(s) [0056], ]0098], [0101]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to form PTO-892 (Notice of Reference Cited) for a list of relevant prior art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED A WASEL whose telephone number is (571) 272-2669. The examiner can normally be reached Mon-Fri (8:00 am – 4:30 pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Glenton Burgess can be reached on (571)272-3949. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMED A. WASEL/Primary Examiner, Art Unit 2454