DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burky et al (pub # US 20200081719 A1).
Regarding claim 1, Burky discloses a system (system in figure 1), comprising: a memory that stores computer executable components (storage circuitry 150 in figure 1, paragraph 29); and a processor (functional units 130 and 140, paragraph 28) that executes the computer executable components stored in the memory, wherein the computer executable components comprise: a prediction component (prediction circuitry, paragraph 31) configured to: parse program code (decode, paragraph 28) to identify a conditional operation in the program code (conditional branch, paragraph 30); generate a prediction of an outcome of the conditional operation (paragraph 31); and speculatively execute an operation in the program code in accordance with the prediction (paragraph 31); and a rewind component configured to: rewind, in response to a determination that the prediction was incorrect, the speculatively executed operation (rewind or flush, to return execution back to the branch instruction, paragraph 31).
Burky does not disclose explicitly the distinct components. However, examiner notes that given the teachings and functionalities of prediction, snapshot, and rewind taught by Burky, and the exemplary system in figure 1, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to separate or combine different circuitry for the benefit of customizing scalability and cost of production.
Regarding claim 3, the above reference discloses the system of claim 1, wherein the conditional operation comprises executing a first operation or executing a second operation (conditional branch instruction determines which instructions are executed after the branch, paragraph 31, predicted instruction E is executed, but instruction H being executed upon correction of prediction).
Regarding claim 4, the above reference discloses the system of claim 3, wherein the first operation is speculatively executed by the prediction component (instruction E is speculatively executed, paragraph 31).
Regarding claim 5, the above reference discloses the system of claim 4, wherein the rewind component is further configured to: monitor execution of the first operation to determine a first state resulting from the speculative execution of the first operation (determine whether the prediction is correct, paragraph 31); generate a rewind operation configured to enact a second state (rewind if prediction is incorrect, paragraph 31), wherein the second state is a conditional state prior to speculative execution of the first operation (operation D, paragraph 31); and apply the rewind operation to the speculatively executed operation (execution restart from operation D, paragraph 31).
Regarding claim 6, the above reference discloses the system of claim 5, wherein the rewind operation comprises one of a conjugate transpose of the first state, a compliment of the first state, utilizing a sequence of gates having an operation that is the compliment to the first state, utilizing a sequence of operations having a combined operation that is the compliment of the first state, or a sequence of gates and operations that combine to be the compliment of the first state (re-execution of instruction D causes a different branch of to be taken, and leads to instruction H, paragraph 31).
Regarding claim 7, the above reference discloses the system of claim 1, wherein the conditional operation in the program code is a first conditional operation (conditional branch, paragraph 31) and the program code is a first program code (historical outcomes of the same branch, paragraph 21), the prediction component is further configured to: identify second program code having a second conditional operation similar to the first conditional operation in the first program code, wherein the second program code is executed prior to the first program code; and identify a second prior outcome of the second conditional operation (current branch instruction predicted based historical outcomes and confidence indicator, paragraph 21).
Regarding claim 8, the above reference discloses the system of claim 7, wherein the prediction component is further configured to: generate the predicted outcome of the first conditional operation based on the second prior outcome of the second conditional operation (based on historical outcomes, paragraph 21).
Allowable Subject Matter
Claims 12-20 are allowed.
Claims 2, 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: prior art of record discloses program prediction and out-of-order execution, including predicting the outcome of conditional branch instructions, and rewinding mispredictions. However, prior art of record does not teach or suggest, inter alia, circuit to predict and rewind conditional branch instructions in a quantum computer. Since conventional and quantum computers are significantly different in design, it would have not been obvious to an ordinary person of skill in the art to simply incorporate conventional prediction circuitry into a quantum computer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SCOTT C SUN/Primary Examiner, Art Unit 2181
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