DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 3, 4, 9 and 12 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by An1.
Regarding claim 3, An teaches a stereoscopic image display device (note that the body of the claim does not specifically recite any elements that refer back to “stereoscopic image display” and define a complete apparatus themselves; see An, paragraph 0010 teaching “a multi-view autostereoscopic image display according to the present invention includes a display panel for displaying multi-view image data”) comprising:
a display panel comprising a plurality of data lines, a plurality of gate lines, and a plurality of pixels (see An, paragraph 0044 and figure 2 teaching “display panel 100 includes a pixel array PIX in which data lines 105 and gate lines (or scan lines) 106 cross each other and pixels are disposed in a matrix form”);
a data driver configured to apply a data voltage of image data to the plurality of data lines (see An, paragraphs 0045-0046 teaching “display panel driver includes a data driving circuit 102 for supplying data voltages of 2D and 3D images to the data lines 105 of the display panel”);
a gate driver configured to apply a gate signal to the plurality of gate lines (see An, paragraph 0045 teaching “gate driving circuit 103 for sequentially supplying scan pulses (or gate pulses) to the scan lines 106 of the display panel 100”);
a timing controller configured to transmit the image data to the data driver, and to control operation timings of the data driver and the gate driver (see An, paragraph 0044 teaching “timing controller 101 supplies digital video data to the data driving circuit 102” and as in paragraph 0050, “timing controller 101 supplies digital video data RGB of a 2D/3D input image input from the host system 110 to the data driving circuit 102” and “timing controller 101 generates timing control signals for controlling operation timings of the display panel driver 102 and 103 and the 3D optical element driver 210 by using the timing signals and controlling the operation timings of these drivers to be synchronized with each other”);
an optical module attached to a front surface of the display panel (see An, paragraph 0047 and figures 3-7 teaching “3D optical element 200 can be implemented as a lens LENTI or barrier BAR, as shown in FIGS. 3 to 7. For example, 3D optical element 200 can be bonded to the front or back of the display panel 100, or it can be embedded in the display panel 100 to separate the optical axes of left-eye image data and right-eye image data of 3D image data. The switchable barrier BAR or switchable lens LENS can include a birefringence medium such as liquid crystal, and it can be electrically driven by the 3D optical element driver 210 to separate the optical axes of light of left-eye and right-eye images” where the lens or barrier are optical modules which are attached (“bonded”) to “the front…of the display panel”); and
an image processor configured to correct the image data based on a correction parameter pre-stored in an internal memory of the timing controller and user's position information sensed by a position sensing module, and transmit the corrected image data to the timing controller (note that “the image data” has antecedent basis as “image data” is what each element functions in relation to but for example “the image data” does not refer to any specific image data that has been processed above; see An, paragraphs 0052-0054 teaching an image processor in the form of host system 110 and 3D data formatter 120 where “host system 110 can be implemented as any of the following: a TV (television) system, a set-top box, a navigation system, a DVD player, a Blue-ray player, a personal computer (PC), a home theater system, a broadcast receiver, and a phone system, or other devices as known. The host system 110 uses a scaler to convert digital video data of a 2D/3D input image into a format appropriate for the resolution of the display panel PNL 100 and transmit a timing signal, along with the data, to the timing controller 101” and “3D data formatter 120 can be installed between the host system 110 and the timing controller 101. The 3D data formatter 120 realigns left-eye image data and right-eye image data of a 3D image input from the host system 110 in the 3D mode in accordance with the multi-view image data format shown in FIGS. 10A and 10B, and supplies it to the timing controller 101. When 2D image data is input in the 3D mode, the 3D data formatter 120 can execute a preset 2D-3D image conversion algorithm to generate left-eye image data and right-eye image data from the 2D image data, realign the data in accordance with the multi-view image data format” where these function to process the display image data and as in paragraphs 0061-0064 teaching “positions, size, and shape of the viewing zones can be pre-stored in a memory of a look-up table LUT in the timing controller 101” and “host system 110 or the timing controller 101 can determine which viewing zone the right eye RE and left eye LE of the viewer are located and determine the movement direction and movement distance of the viewer by comparing a position of the viewer sensed by the viewing distance sensing unit 114 with viewing zone position information of the look-up table. Also, the host system 110 or the timing controller 101 can serve as a viewing distance extension controller which controls the driving circuits of the display panel and converts at least some of multi-view image data into different view image data according to a change in the viewer's position” and “the multi-view autostereoscopic image display of the present invention senses the position of a viewing zone where the viewer is located, and selectively converts multi-view image data according to the sensed position of the viewer, thus allowing the viewer to view a normal stereoscopic image at any position” such that here the host system 110 functioning as an image processor is configured to correct the image data based on a correction parameter “pre-stored in a memory of a look-up table LUT in the timing controller 101” where it determines the location of the viewer using a viewer sensing unit and uses this information in connection with the LUT “and converts at least some of multi-view image data into different view image data according to a change in the viewer’s position” where this conversion is a correction of the image data to avoid crosstalk errors and as the host system can perform the correction and the timing controller is downstream of such image processor then this means the timing controller is transmitted the corrected image data).
Regarding claim 4, An teaches all that is required as applied to claim 3 above and further teaches wherein the optical module includes a plurality of lenticular lenses having a predetermined width (see An, paragraphs 0005-0007 and figure 1 describing the principles of the optical module which can be a “lenticular lens“ where a lens in the reference refers to lenticular lenses and thes are arranged where “an optimal viewing distance OVD from which a viewer can properly view a stereoscopic image is calculated based on the back length between a pixel array PIX of a display panel and a lens LENS, the focal length of the lens LENS, a pixel pitch Ppix, a lens pitch Plens, and the distance between the left and right eyes of the viewer” and as seen in figures 3, 5, 6 and 7, the lenses “lenti” have some spatial dimension that has been set across the lens where the lens pitch Plens is a width of a lenticular lens), wherein the plurality of lenticular lenses are arranged side by side in a same direction as a direction of the plurality of data lines (see An, paragraphs 0005-0007 and figure 1 as explained above describing the basic principles of the autostereoscopic display where the lenses can be seen arranged side by side in a same direction as a direction of pixels and as in paragraphs 0044-0046 “display panel 100 includes a pixel array PIX in which data lines 105 and gate lines (or scan lines) 106 cross each other and pixels are disposed in a matrix form” and as in figures 3, 5, 6 and 7 it can be seen that the pixels which correspond to the data lines which are driving them are arranged side by side in the same direction as the lenses are arranged side by side such that the data lines are also considered arranged in that direction side by side as well).
Regarding claim 9, An teaches all that is required as applied to claim 3 above and further teaches wherein the image processor includes: a first image processor configured to scale 2D image data to a first resolution responsive to receiving the 2D image data (see An, paragraphs 0053-0054 teaching “host system 110 uses a scaler to convert digital video data of a 2D/3D input image into a format appropriate for the resolution of the display panel PNL 100 and transmit a timing signal, along with the data, to the timing controller 101” and “host system 110 supplies a 2D image to the timing controller 101 in the 2D mode” such that here when operating in 2D mode the host system functions as an image processor acting as a first image processor configured to scale 2D image data to a first resolution “format appropriate for the resolution of the display panel”); and
a second image processor configured to scale left-eye image data and right-eye image data to a second resolution responsive to receiving the left-eye image data and the right-eye image data (see An, paragraphs 0052-0054 teaching “host system 110 uses a scaler to convert digital video data of a 2D/3D input image into a format appropriate for the resolution of the display panel PNL 100 and transmit a timing signal, along with the data, to the timing controller 101” where “host system 110 … supplies a 3D or 2D image data to the 3D data formatter 120 in the 3D mode” and “3D data formatter 120 can be installed between the host system 110 and the timing controller 101. The 3D data formatter 120 realigns left-eye image data and right-eye image data of a 3D image input from the host system 110 in the 3D mode in accordance with the multi-view image data format shown in FIGS. 10A and 10B, and supplies it to the timing controller 101” and “When 2D image data is input in the 3D mode, the 3D data formatter 120 can execute a preset 2D-3D image conversion algorithm to generate left-eye image data and right-eye image data from the 2D image data, realign the data in accordance with the multi-view image data format shown in FIGS. 10A and 10B, and transmit it to the timing controller 101” such that the second image processor is the host system and 3D formatter which scales the left and right eye image data in 3D mode to a second resolution responsive to receiving the left and right eye image data as it always scaling the “input image into a format appropriate for the resolution of the display panel”).
Regarding claim 12, An teaches all that is required as applied to claim 3 above and further teaches wherein the timing controller is on a control printed circuit board (CPCB), and the image processor is on a PCB separate from the CPCB (see An, paragraphs 0043-0054 and figure 2 teaching timing controller on a control circuit corresponding to “timing controller 101” where this timing controller is located with the display as it is controlling the pixels through the connected driver circuits as disclosed and where “host system 110” is separate and functions as the image processor as explained above and “host system 110 can be implemented as any of the following: a TV (television) system, a set-top box, a navigation system, a DVD player, a Blue-ray player, a personal computer (PC), a home theater system, a broadcast receiver, and a phone system, or other devices as known. The host system 110 uses a scaler to convert digital video data of a 2D/3D input image into a format appropriate for the resolution of the display panel PNL 100 and transmit a timing signal, along with the data, to the timing controller 101” such that as it must transmit this information it is a separate circuit from the timing controller of the display; note that ‘’ a set-top box…a DVD player, a Blue-ray player, a personal computer (PC)” are all examples of host systems acting as image processors where such rely on microelectronics on printed circuit boards as such available devices would of course use printed circuit boards as they are the industry standard for such data intensive processing tasks and alternatives would not be operable as explained below; further see paragraph 0063 teaching “host system 110 or the timing controller 101 can serve as a viewing distance extension controller which controls the driving circuits of the display panel and converts at least some of multi-view image data into different view image data according to a change in the viewer's position” such that this shows the timing controller 101 is separate from the host system and that the timing controller is one that “controls the driving circuits of the display panel” meaning that the timing controller which signals the driving circuits is also of the display panel and separate from the host system and its processing). An teaches all of the above, but is silent as to the control circuit and image processor circuits being on printed circuit boards (where a CPCP is functionally simply a PCB associated with control functions). However, in the context of the invention, such functions being carried out would inherently be carried out with respect to installation of such processing elements on a printed circuit board. In relying upon a theory of inherency, the Examiner recognizes that the examiner must provide a basis in fact and/or technical reasoning to reasonably support the determination that the allegedly inherent characteristic necessarily flows from the teachings of the applied prior art. Here An teaches the host system to process “digital video data of a 2D/3D input image”, including “multi-view image data” such as 4-view image data and transmit this data at video frame rates such as 60 Hz, and furthermore (see An, paragraphs 0051-0061). It is a fact and fundamental technical necessity recognized by one having ordinary skill in the art that such high-bandwidth, high-frequency digital signaling done by such circuits performing the processing disclosed by An require precise impedance control, grounding planes, and electromagnetic shielding provided by printed circuit boards. The Examiner is unable to find any alternative wiring technique that is known that could reasonably provide such circuits without use of a printed circuit board as for example Thus it necessarily and inevitably flows from the explicit data transmission and high-speed processing requirements performed by the image processor and timing controller and their functional relationships that the timing controller is mounted on a control printed circuit board (CPCB) and the image processor is mounted on a PCB separate from the CPCP of the external host system processor, as both inherently must be on a printed circuit board to physically function as disclosed to achieve autostereoscopic viewing.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Takahashi2.
Regarding claim 5, An teaches all that is required as applied to claim 3 above but fails to explicitly teach wherein the optical module further includes an adhesive member on bottom surfaces of the plurality of lenticular lenses. An does teach that the optical member is bonded on bottom surfaces of the plurality of lenticular lenses (see An, paragraphs 0041 and 0047 and figures 3-7 teaching “3D optical element in the multi-view autostereoscopic image display can be bonded onto a display panel of the multi-view autostereoscopic image display” and “3D optical element 200 can be bonded to the front or back of the display panel 100”), but is silent as to how such bonding is achieved and does not mention any specific “adhesive member” that is on the bottom surfaces of the plurality of lenticular lenses.
In the same field of endeavor relating to attaching optical modules such as lenticular lenses to a display for autostereoscopic viewing, Takahashi teaches aligning an optical module for attaching to a display for autostereoscopic viewing wherein the optical module further includes an adhesive member on bottom surfaces of the plurality of lenticular lenses (see Takahashi, paragraph 0005 and figure 1 teaching “a top view of a lenticular-type 3D display with a lens sheet in front of display panel” and “lenticular-type 3D display 1 includes a backlight system 11, a display panel 13 on the backlight system 11, a lens sheet 15 attached on the display panel 13 by an adhesive 17 (such as glue)” where here the optical modules is the lens sheet attached on the bottom surface of the plurality of lenses of the sheet to the display panel 13 using an adhesive member such as “adhesive 17 (such as glue)” such that the optical module is bonded to the panel, which is further taught in paragraph 0055 and figure 8 where “a lens sheet 45 loaded on a 3D component stage 50 b is stacked on a display panel 43 (ex: LCD panel) loaded on a display x-y stage 50 a (with a backlight 51 thereon), and an UV glue 47 is dispersed between the lens sheet 45 and the display panel 43”). Thus the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date to modify with the teachings of Takahashi because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would yield nothing more than predictable results to one of ordinary skill in the art. Here An already teaches to bond the optical module to the display panel and Takahashi teaches that such bonding could be achieved through use of an adhesive member on bottom surfaces of the lenses of the lens sheet such that in combination, each element merely performs the same function as it does separately. Thus modifying An with the teachings of Takahashi would predictably result in a bond achieved using an adhesive member and autostereoscopic viewing would function as in both prior art teachings.
Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Cui et al3 (“Cui”).
Regarding claim 6, An teaches all that is required as applied to claim 4 above but fails to teach wherein a dummy area that lacks any lenticular lenses is on both sides of the optical module, a plurality of first alignment marks are in a non-display area of the display panel, and a plurality of second alignment marks corresponding to the plurality of first alignment marks are in the dummy area of the optical module. Thus An stands as a base device upon which the claimed invention can be seen as an improvement through such use of alignment marks that could improve the alignment of the optical module with the display panel.
In the same field of endeavor relating to autostereoscopic displays which have an optical module attached to a display panel, Cui teaches that is it know to provide an optical module and display panel and to attach the optical module comprising lenticular lenses to the display panel to enable stereoscopic viewing that such system comprises a dummy area that lacks any lenticular lenses is on both sides of the optical module (see Cui, column 4, lines 12-51 teaching “aligning and assembling a stereoscopic display” and “using an alignment imaging device to search alignment marks at non-display regions of a display panel and a cylindrical lens sheet” where “in the present embodiment, the non-display region of the display panel includes six alignment marks, the non-display region of the cylindrical lens sheet also includes six alignment marks” such that here the “non-display region of the cylindrical lens sheet” is a dummy area that lacks any lenticular lenses as seen in figure 4 showing a lack of lenticular lenses on the optical module in the non-display area where the alignment marks are positioned), a plurality of first alignment marks are in a non-display area of the display panel (see Cui, column 4, lines 12-51 and figure 4 teaching “the non-display region of the display panel includes six alignment marks”), and a plurality of second alignment marks corresponding to the plurality of first alignment marks are in the dummy area of the optical module (see Cui, column 4, lines 12-51 teaching “aligning and assembling a stereoscopic display” and “using an alignment imaging device to search alignment marks at non-display regions of a display panel and a cylindrical lens sheet” where “in the present embodiment, the non-display region of the display panel includes six alignment marks, the non-display region of the cylindrical lens sheet also includes six alignment marks” such that here the “non-display region of the cylindrical lens sheet” is a dummy area that lacks any lenticular lenses as seen in figure 4 showing a lack of lenticular lenses on the optical module in the non-display area where the alignment marks are positioned ).
Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify An to incorporate the non-display regions with corresponding alignment marks as taught by Cui. The predicable result of the modification would be that the optical module of An would have alignment marks placed thereon where information from such alignment marks can be used to provide correction information relating to the alignment of the optical module and display panel. This would result in an improved system as it allows to “effectively solve the assembling and aligning problem of the cylindrical lens sheet with high ductility and the display panel, improving the assembling drift corresponding to a direction of a 3D display for left and right eyes, which can obviously improve the assembly precision, reduce crosstalk and improve the 3D display effect,” as suggested by Cui (see column 3, lines 28-50).
Regarding claim 8, An as modified teaches all that is required as applied to claim 6 above and further teaches wherein a specification mark that indicates a specification of the optical module is in the dummy area of the optical module (see An as modified by Cui where Cui’s alignment marks are in the dummy area of the optical module as explained above and such alignment marks may also be considered to function as specification marks as they specify the position of the optical module in relation to the display panel alignment marks and also function to specify a center coordinate of the display panel and lens sheet as in column 4, lines 12-51 teaching “aligning and assembling a stereoscopic display” and “using an alignment imaging device to search alignment marks at non-display regions of a display panel and a cylindrical lens sheet” where “in the present embodiment, the non-display region of the display panel includes six alignment marks, the non-display region of the cylindrical lens sheet also includes six alignment marks” and as in column 5, lines 3-23, the marks as positioned also specify the center coordinate of the sheet and display where “determining center points of the two groups of the alignment marks, and averaging coordinates of the center points of the two groups of the alignment marks in order to obtain first mark points. Respectively connecting the two groups of the alignment marks at diagonal directions, and respectively obtaining the center points of the alignment marks which are connecting at diagonal directions. Then, averaging the two center points in order to obtain the first mark point. The step of the averaging the center points is specifically realized by connecting two center points to form a connection line. Then, taking a center point of the connection line as the first mark point. Using the display panel as an example, with reference to FIG. 5, center points of the two groups of alignment marks at diagonal directions of the display panel are respectively a center point 1 and a center point 3. Averaging the center point 1 and the center point 3 to obtain a center point 2 as the first mark point of the present embodiment. The method for determining a first mark point of the cylindrical lens sheet is similar as above, no more repeating”).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over An as modified as applied to claim 6 above, and further in view of Saito et al4 (“Saito”).
Regarding claim 7, An as modified teaches all that is required as applied to claim 6 above and further teaches wherein the correction parameter is an error indicating a degree of alignment between a first alignment mark from the plurality of first alignment marks and a second alignment mark from the plurality of second alignment marks, measured by a measuring device when the optical module is attached to the front surface of the display panel (see An as modified by Cui above where Cui teaches to determine an error indicating a degree of alignment between first and second alignment marks measured by a measuring device when the optical module is attached to the front surface of the display panel as column 5, lines 3-67 through column 6, lines 1-12 teaching “S23: searching the alignment marks at central positions of short edges of each of the display panel and cylindrical lens sheet, and using a center point between the alignment marks at central positions of the short edges of each of the display panel and cylindrical lens sheet as a second mark point.” And “determining two included angles between diagonals and long sides of the display panel and the cylindrical lens sheet, and averaging the two included angles in order to obtain an angle offset” and “Averaging the two included angles (the included angle between the diagonal and the long side of the display panel and the included angle between the diagonal and the long side of cylindrical lens sheet) means taking an average value of the two included angles. Adopting the average value as the angle offset of the display panel and the cylindrical lens sheet. For example, adopting (α1+α2)/2 as the angle offset of the display panel and the cylindrical lens sheet”). An as modified teaches the bolded limitations above, however, the error is a correction parameter in Cui which is used to correct the alignment at production, whereas the claims require a correction parameter used when displaying the image by the image processor to correct such offset. Thus An as modified stands as a base device upon which the claimed invention can be seen as an improvement which would use misalignment error data between an optical module and display panel to correct image data for display and would not require additional fitting or aligning stages or processes to be performed during manufacture and production.
In the same field of endeavor relating to correcting errors caused by misalignment of an optical module and display panel, Saito teaches that it is known to provide an image processor that corrects for production errors relating to the attachment of an optical module and display panel and determines correction parameters relating to such alignment wherein the correction parameter is an error indicating a degree of alignment between a first alignment mark from the plurality of first alignment marks and a second alignment mark from the plurality of second alignment marks (see Saito, paragraphs 0076-0078 teaching “Parallax images displayed on an autostereoscopic display apparatus are generally easily influenced by an angle error of the boundaries BL of the cylindrical lenses 12 with respect to the pixel pitch of the two-dimensional display 11, and a production error caused when the cylindrical lenses 12 are attached to the two-dimensional display 11. In addition, the parallax images are also influenced by a production error caused in the individual process of producing the cylindrical lenses 12. In a second embodiment of the present invention, an autostereoscopic display apparatus that corrects a variation of the lens pitch L of the cylindrical lenses 12 caused by a production error and corrects an error of a fixing angle of the lenticular sheet 14 fixed to the two-dimensional display 11 will be explained” and “a production error storage unit 33 that stores a production error ΔL of the lens pitch L of the cylindrical lenses 12 and a production error Δθ of the inclined angle θ of the boundaries BL of the cylindrical lenses 12, and the parallax image changer 22 that changes parallax images based on the production errors stored in the production error storage unit 33” and “a “production error” is a margin of error from a design value or a target value caused when the autostereoscopic display apparatus is manufactured. The “production error” includes an error caused when the plural cylindrical lenses 12 are attached to the two-dimensional display 11 and an error caused in the individual process of producing the cylindrical lenses 12. The production error caused when attaching the cylindrical lenses 12 to the two-dimensional display 11 or in the individual process of producing the cylindrical lenses 12 is stored in the production error storage unit 33 before shipping the autostereoscopic display apparatus”), measured by a measuring device when the optical module is attached to the front surface of the display panel (see Saito, paragraphs 0076-0078 teaching “error of the cylindrical lenses 12 themselves may be detected by, for example, preparing data showing a one-to-one error with regard to each of the cylindrical lenses 12. The error caused during the attaching process may be detected as follows. First, each of the two-dimensional display 11 and the cylindrical lenses 12 is provided with a positioning mark. Then, the amount of gap between the respective positioning marks is measured by, for example, a CCD camera to detect the error. Note that the detection of each of the production error ΔL of the lens pitch L and the production error Δθ of the inclined angle θ is not limited to the method described above, and the detection may be carried out by other methods” where the error relates to “production error ΔL of the lens pitch L is divided into three stages of less than −0.5 μm, from −0.5 μm to +0.5 μm, and more than +0.5 μm. The production error Δθ of the inclined angle θ is divided into three stages of less than −0.05, from −0.05 to +0.05, and more than +0.05. Nine parallax images S1 to S9 corresponding to the combinations of the three stages of the production error ΔL and the three stages of the production error Δθ are stored in the parallax image storage unit 34” and an image processor such as “parallax image changer 22 that changes parallax images based on the production errors stored” is disclosed as an image processor that utilizes the error data and as in paragraphs 0085-0089 the image processor parallax changer accesses the pre-stored error data to correct the images when displayed). Thus Saito teaches a known technique applicable to the base device of An as modified.
Therefore it would have been obvious for one of ordinary skill in the art to apply the teachings of Saito to the base system of An as modified as doing so would be no more than application of a known technique to a base device ready for improvement where the modification would yield predictable results and result in an improved system. The predictable result of applying Saito’s technique would be that the image processor of An that corrects the image already based on a viewing position would also access the alignment error data to correct the image data based on the alignment errors stored as offset positioning data and to correct the image based on these correction parameters as in Saito when it is displayed to the user. This would result in an improved system as it would allow to solve for the problem of misalignment of optical modules and display panel production without necessitating further effort to have perfectly precise attachment and “corrects a variation of the lens pitch L of the cylindrical lenses 12 caused by a production error and corrects an error of a fixing angle of the lenticular sheet 14 fixed to the two-dimensional display 11” as suggested by Saito (see Saito, paragraph 0076).
Claim(s) 10, 11 and 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Kuruhashi et al5 (“Kuruhashi”).
Regarding claim 10, An teaches all that is required as applied to claim 9 above and further teaches wherein the first image processor includes: an input buffer configured to receive the 2D image data; a scaler configured to scale the 2D image data to the first resolution (see An, paragraphs 0053-0054 teaching “host system 110 uses a scaler to convert digital video data of a 2D/3D input image into a format appropriate for the resolution of the display panel PNL 100 and transmit a timing signal, along with the data, to the timing controller 101” and “host system 110 supplies a 2D image to the timing controller 101 in the 2D mode” such that here when operating in 2D mode the host system functions as an image processor acting as a first image processor configured to scale 2D image data to a first resolution “format appropriate for the resolution of the display panel” ); and an output buffer configured to store the scaled 2D image data. An teaches the limitations bolded above but is silent with regard to use of an input buffer to receive the 2D image data and an output buffer configured to stored the scaled 2D image data. Thus An stands as a base device upon which the claimed invention can be seen an improvement as the processing architecture to execute the operations is not specifically disclosed and can be seen as ready for improvement relating to its internal memory routing and staging architecture.
In the same field of endeavor relating to processing and displaying left/right images on an autostereoscopic display and use of input and output buffers in displaying such data, Kuruhashi teaches an input buffer configured to receive 2D image data (see Kuruhashi, column 7, lines 15-67 through column 8, lines 1-27 teaching “images … are displayed as a stereoscopic image … on the display device 4” and “left and right image … are respectively entered … into a signal processing circuit 27, and all the drive circuits and the processing circuits relating to the generation of the left and right image signals are synchronized under the control of a timing generator 25” and “signal processing circuit 27 is connected to color process circuits 26 a, 26 b; process memories 31 a, 31 b; a compression/expansion circuit 32 and a VRAM 28, and executes various signal processings including a color conversion process by supplying the color process circuits 26 a, 26 b with the left and right image signals converted into digital signals by the A/ D conversion circuits 23 a, 23 b; conversion of the left and right digital image signals subjected to such color conversion process into a predetermined pixel size and transfer of thus converted left and right digital image signals to the VRAM 28 alternately in the vertical direction by every line; and storage of the image data in the process memories 31 a, 31 b. Since the number of pixels of the images stored in the process memories 31 a, 31 b does not necessarily coincide with that of the pixels of the image displayed on the LCD 30, as will be explained later, the image process circuit 27 is further provided with a function of pixel thinning-out and interpolation for coping with the difference in the number of pixels, in addition to the foregoing functions” where “liquid crystal display (LCD) 30 constitutes the display device 4 of the compound eye camera 1, and is controlled by an LCD control unit 29. The VRAM 28, constituting a display memory, has a capacity sufficient for the image to be displayed on the LCD 30, and, under the control by the LCD control unit 29, the contents stored in the VRAM 28 is displayed on the LCD 30” such that here “process memories 31 a, 31 b” are used for image processing and image conversion and correction including a scaling to a predetermined pixel size and format where these process memories function as an input buffer configured to receive the 2D left/right images as further explained in column 9, lines 1-45, teaching “Receiving the left and right parallax images subjected to color conversion, the signal processing circuit 27 stores image data of such parallax images in the process memories 31 a, 31 b, and converts the left and right parallax images so as to match the pixel size of the LCD 30” such that here the process memories act as an input buffer to perform the scaling and conversion and other processing operations); a scaler configured to scale the 2D image data to the first resolution (see Kuruhashi, column 7, lines 15-67 through column 8, lines 1-27, where as above “left and right image … are respectively entered … into a signal processing circuit 27, and all the drive circuits and the processing circuits relating to the generation of the left and right image signals are synchronized under the control of a timing generator 25” and “signal processing circuit 27 is connected to color process circuits 26 a, 26 b; process memories 31 a, 31 b; a compression/expansion circuit 32 and a VRAM 28, and executes various signal processings including a color conversion process by supplying the color process circuits 26 a, 26 b with the left and right image signals converted into digital signals by the A/ D conversion circuits 23 a, 23 b; conversion of the left and right digital image signals subjected to such color conversion process into a predetermined pixel size and transfer of thus converted left and right digital image signals to the VRAM 28 alternately in the vertical direction by every line; and storage of the image data in the process memories 31 a, 31 b. Since the number of pixels of the images stored in the process memories 31 a, 31 b does not necessarily coincide with that of the pixels of the image displayed on the LCD 30, as will be explained later, the image process circuit 27 is further provided with a function of pixel thinning-out and interpolation for coping with the difference in the number of pixels, in addition to the foregoing functions” this conversion to a predetermined pixel size is a scaling operation as further explained in column 9, lines 1-45 teaching “Receiving the left and right parallax images subjected to color conversion, the signal processing circuit 27 stores image data of such parallax images in the process memories 31 a, 31 b, and converts the left and right parallax images so as to match the pixel size of the LCD 30” such that here the process memories act as an input buffer to perform the scaling and conversion and other processing operations); and an output buffer configured to store the scaled 2D image data (see Kuruhashi, column 7, lines 15-67 through column 8, lines 1-27, teaching “conversion of the left and right digital image signals subjected to such color conversion process into a predetermined pixel size and transfer of thus converted left and right digital image signals to the VRAM 28” where VRAM 28 is an output buffer which stores the scaled image data as further taught in column 9, lines 1-45, teaching “Receiving the left and right parallax images subjected to color conversion, the signal processing circuit 27 stores image data of such parallax images in the process memories 31 a, 31 b, and converts the left and right parallax images so as to match the pixel size of the LCD 30 and writes an interlaced image, synthesized by alternating both images by every line in the vertical direction, into the VRAM 28. Through these operations, the left and right parallax images obtained form the CCD's 20 a, 20 b are stored in the process memories 31 a, 31 b and in the VRAM 28” such that here the VRAM functions as an output buffer configured to store the scaled 2D image data before display on the display 4 ). Thus Kuruhashi teaches that utilizing a pipeline of an input buffer, a scaling circuit, and an output buffer was a known technique in the art of autostereoscopic image display processing.
Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention, to modify An by applying the known techniques of Kuruhashi as doing so would be no more than application of a known technique to a base device ready for improvement, which would yield predictable results and result in an improved system. The predictable result of the application of Kuruhashi to An would be that An’s generically taught scaler would be implemented using Kuruhashi’s input and output buffer architecture (which allows for processing to be performed on the image data before display) such that the input and output buffers would allow for the temporary data storage required to stage incoming 2D left/right image data so that image processing can be applied, and where the output buffer would predictable store the scaled data so that it can be displayed once it is ready and can be synchronized for display. This would result in an improved system as the scaling pipeline would be able to be implemented in high speed real time display of captured or transmitted images or reviewed at a later time with such buffers enabling the image processing and image data routing to allow for such varied viewing as suggested by Kuruhashi (see Kuruhashi, column 7, lines 14-24 teaching “the images picked up by the image pickup optical systems 2, 3 are displayed as a stereoscopic image or a panoramic image on the display device 4, so that the photographer can observe the picked-up images on the spot or even in the course of image pickup operation”).
Regarding claim 11, An teaches all that is required as applied to claim 9 above and further teaches wherein the second image processor includes: an input buffer configured to receive the left-eye and right-eye image data; a first scaler configured to scale the left-eye image data to the second resolution; a second scaler configured to scale the right-eye image data to the second resolution (see An, paragraphs 0052-0054 teaching “host system 110 uses a scaler to convert digital video data of a 2D/3D input image into a format appropriate for the resolution of the display panel PNL 100 and transmit a timing signal, along with the data, to the timing controller 101” where “host system 110 … supplies a 3D or 2D image data to the 3D data formatter 120 in the 3D mode” and “3D data formatter 120 can be installed between the host system 110 and the timing controller 101. The 3D data formatter 120 realigns left-eye image data and right-eye image data of a 3D image input from the host system 110 in the 3D mode in accordance with the multi-view image data format shown in FIGS. 10A and 10B, and supplies it to the timing controller 101” and “When 2D image data is input in the 3D mode, the 3D data formatter 120 can execute a preset 2D-3D image conversion algorithm to generate left-eye image data and right-eye image data from the 2D image data, realign the data in accordance with the multi-view image data format shown in FIGS. 10A and 10B, and transmit it to the timing controller 101” such that the second image processor is the host system and 3D formatter which scales the left and right eye image data in 3D mode to a second resolution responsive to receiving the left and right eye image data as it always scaling the “input image into a format appropriate for the resolution of the display panel” such that here it functions as a first scaler and a second scaler when it operates on the respective left and right eye image data which is scaled to the display resolution); a correction module configured to correct the scaled left-eye image data and the scaled right-eye image data based on the pre-stored correction parameter and the sensed user's position information (see An, paragraphs 0052-0054 teaching an image processor in the form of host system 110 and 3D data formatter 120 where “host system 110 can be implemented as any of the following: a TV (television) system, a set-top box, a navigation system, a DVD player, a Blue-ray player, a personal computer (PC), a home theater system, a broadcast receiver, and a phone system, or other devices as known. The host system 110 uses a scaler to convert digital video data of a 2D/3D input image into a format appropriate for the resolution of the display panel PNL 100 and transmit a timing signal, along with the data, to the timing controller 101” and “3D data formatter 120 can be installed between the host system 110 and the timing controller 101. The 3D data formatter 120 realigns left-eye image data and right-eye image data of a 3D image input from the host system 110 in the 3D mode in accordance with the multi-view image data format shown in FIGS. 10A and 10B, and supplies it to the timing controller 101. When 2D image data is input in the 3D mode, the 3D data formatter 120 can execute a preset 2D-3D image conversion algorithm to generate left-eye image data and right-eye image data from the 2D image data, realign the data in accordance with the multi-view image data format” where these function to process the display image data and as in paragraphs 0061-0064 teaching “positions, size, and shape of the viewing zones can be pre-stored in a memory of a look-up table LUT in the timing controller 101” and “host system 110 or the timing controller 101 can determine which viewing zone the right eye RE and left eye LE of the viewer are located and determine the movement direction and movement distance of the viewer by comparing a position of the viewer sensed by the viewing distance sensing unit 114 with viewing zone position information of the look-up table. Also, the host system 110 or the timing controller 101 can serve as a viewing distance extension controller which controls the driving circuits of the display panel and converts at least some of multi-view image data into different view image data according to a change in the viewer's position” and “the multi-view autostereoscopic image display of the present invention senses the position of a viewing zone where the viewer is located, and selectively converts multi-view image data according to the sensed position of the viewer, thus allowing the viewer to view a normal stereoscopic image at any position” such that here the host system 110 functioning as an image processor is configured to correct the image data based on a correction parameter “pre-stored in a memory of a look-up table LUT in the timing controller 101” where it determines the location of the viewer using a viewer sensing unit and uses this information in connection with the LUT “and converts at least some of multi-view image data into different view image data according to a change in the viewer’s position” where this conversion is a correction of the image data to avoid crosstalk errors and as the host system can perform the correction and the timing controller is downstream of such image processor then this means the timing controller is transmitted the corrected image data); and an output buffer configured to store the corrected left-eye image data and the corrected right-eye image data. An teaches the limitations bolded above but is silent with regard to use of an input buffer to receive the image data and an output buffer configured to stored the scaled image data. Thus An stands as a base device upon which the claimed invention can be seen an improvement as the processing architecture to execute the operations is not specifically disclosed and can be seen as ready for improvement relating to its internal memory routing and staging architecture.
In the same field of endeavor relating to processing and displaying left/right images on an autostereoscopic display and use of input and output buffers in displaying such data, Kuruhashi teaches an input buffer configured to receive the left-eye and right-eye image data (see Kuruhashi, column 7, lines 15-67 through column 8, lines 1-27 teaching “images … are displayed as a stereoscopic image … on the display device 4” and “left and right image … are respectively entered … into a signal processing circuit 27, and all the drive circuits and the processing circuits relating to the generation of the left and right image signals are synchronized under the control of a timing generator 25” and “signal processing circuit 27 is connected to color process circuits 26 a, 26 b; process memories 31 a, 31 b; a compression/expansion circuit 32 and a VRAM 28, and executes various signal processings including a color conversion process by supplying the color process circuits 26 a, 26 b with the left and right image signals converted into digital signals by the A/ D conversion circuits 23 a, 23 b; conversion of the left and right digital image signals subjected to such color conversion process into a predetermined pixel size and transfer of thus converted left and right digital image signals to the VRAM 28 alternately in the vertical direction by every line; and storage of the image data in the process memories 31 a, 31 b. Since the number of pixels of the images stored in the process memories 31 a, 31 b does not necessarily coincide with that of the pixels of the image displayed on the LCD 30, as will be explained later, the image process circuit 27 is further provided with a function of pixel thinning-out and interpolation for coping with the difference in the number of pixels, in addition to the foregoing functions” where “liquid crystal display (LCD) 30 constitutes the display device 4 of the compound eye camera 1, and is controlled by an LCD control unit 29. The VRAM 28, constituting a display memory, has a capacity sufficient for the image to be displayed on the LCD 30, and, under the control by the LCD control unit 29, the contents stored in the VRAM 28 is displayed on the LCD 30” such that here “process memories 31 a, 31 b” are used for image processing and image conversion and correction including a scaling to a predetermined pixel size and format where these process memories function as an input buffer configured to receive the 2D left/right images as further explained in column 9, lines 1-45, teaching “Receiving the left and right parallax images subjected to color conversion, the signal processing circuit 27 stores image data of such parallax images in the process memories 31 a, 31 b, and converts the left and right parallax images so as to match the pixel size of the LCD 30” such that here the process memories act as an input buffer to perform the scaling and conversion and other processing operations); a first scaler configured to scale the left-eye image data to the second resolution; a second scaler configured to scale the right-eye image data to the second resolution (see Kuruhashi, column 7, lines 15-67 through column 8, lines 1-27, where as above “left and right image … are respectively entered … into a signal processing circuit 27, and all the drive circuits and the processing circuits relating to the generation of the left and right image signals are synchronized under the control of a timing generator 25” and “signal processing circuit 27 is connected to color process circuits 26 a, 26 b; process memories 31 a, 31 b; a compression/expansion circuit 32 and a VRAM 28, and executes various signal processings including a color conversion process by supplying the color process circuits 26 a, 26 b with the left and right image signals converted into digital signals by the A/ D conversion circuits 23 a, 23 b; conversion of the left and right digital image signals subjected to such color conversion process into a predetermined pixel size and transfer of thus converted left and right digital image signals to the VRAM 28 alternately in the vertical direction by every line; and storage of the image data in the process memories 31 a, 31 b. Since the number of pixels of the images stored in the process memories 31 a, 31 b does not necessarily coincide with that of the pixels of the image displayed on the LCD 30, as will be explained later, the image process circuit 27 is further provided with a function of pixel thinning-out and interpolation for coping with the difference in the number of pixels, in addition to the foregoing functions” this conversion to a predetermined pixel size is a scaling operation as further explained in column 9, lines 1-45 teaching “Receiving the left and right parallax images subjected to color conversion, the signal processing circuit 27 stores image data of such parallax images in the process memories 31 a, 31 b, and converts the left and right parallax images so as to match the pixel size of the LCD 30” and “At first the left-side image a and the right-side image b are converted, according to the display size of the LCD 30, to compressed images, c, d, for example by compression to ½ in the vertical and horizontal directions to 320×240 pixels (lines L′0-L′239 and R′0-R′239). Such image conversion can be achieved by a simple thinning-out or interpolation. Then these compressed images, c, d are alternately synthesized by every line in the order of [L′0, R′1, L′2, . . . , R′237, L′238, R′239] to generate a synthesized image e, which is then written into the VRAM 28” such that here the conversion is to a second display resolution matching the display and having the proper pixels for each left and right image); an output buffer configured to store the corrected left-eye image data and the corrected right-eye image data (see Kuruhashi, column 7, lines 15-67 through column 8, lines 1-27, teaching “conversion of the left and right digital image signals subjected to such color conversion process into a predetermined pixel size and transfer of thus converted left and right digital image signals to the VRAM 28” where VRAM 28 is an output buffer which stores the scaled image data as further taught in column 9, lines 1-45, teaching “Receiving the left and right parallax images subjected to color conversion, the signal processing circuit 27 stores image data of such parallax images in the process memories 31 a, 31 b, and converts the left and right parallax images so as to match the pixel size of the LCD 30 and writes an interlaced image, synthesized by alternating both images by every line in the vertical direction, into the VRAM 28. Through these operations, the left and right parallax images obtained form the CCD's 20 a, 20 b are stored in the process memories 31 a, 31 b and in the VRAM 28” such that here the VRAM functions as an output buffer configured to store the scaled left/right image data before display on the display 4 ). Thus Kuruhashi teaches that utilizing a pipeline of an input buffer, scaling/correction/image processing of data from the input buffer, and an output buffer that stores processed data was a known technique in the art of autostereoscopic image display processing.
Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention, to modify An by applying the known techniques of Kuruhashi as doing so would be no more than application of a known technique to a base device ready for improvement, which would yield predictable results and result in an improved system. The predictable result of the application of Kuruhashi to An would be that An’s generically taught scaler would be implemented using Kuruhashi’s input and output buffer architecture (which allows for processing to be performed on the image data before display) such that the input and output buffers would allow for the temporary data storage required to stage incoming 2D left/right image data so that image processing can be applied, and where the output buffer would predictable store the scaled data so that it can be displayed once it is ready and can be synchronized for display. This would result in an improved system as the scaling pipeline would be able to be implemented in high speed real time display of captured or transmitted images or reviewed at a later time with such buffers enabling the image processing and image data routing to allow for such varied viewing as suggested by Kuruhashi (see Kuruhashi, column 7, lines 14-24 teaching “the images picked up by the image pickup optical systems 2, 3 are displayed as a stereoscopic image or a panoramic image on the display device 4, so that the photographer can observe the picked-up images on the spot or even in the course of image pickup operation”).
Regarding claim 1, the instant claim limitations defining the “image processor” correspond to the limitations of claims 3, 9 and 11 wherein the “second image processor” as defined by claim 11 and addressed in the rejection of claim 11 corresponds to the “image processor” of claim 1. In the interest of brevity and as it is clear that claim 11 is narrower while containing all of the limitations of claim 1, such that the prior art combination and rejection applied in claim 11 necessarily also anticipated each limitation of claim 1. Thus the limitations of claim 1 correspond to the limitations of claim 11; thus they are rejected on the same grounds as claim 11.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over An as modified by Kuruhashi as applied to claim 1 above, and further in view of Won et al6 ("Won").
Regarding claim 2, An as modified teaches all that is required as applied to claim 1 above but fails to teach wherein the correction parameter includes at least one of a specification error of an optical module, an attachment position error of the optical module, or a tilting angle error of the optical module. Rather in An as modified the correction can be with regard to a user viewing position and color and scale and format correction, but the correction parameter is not at least one of a specification error of an optical module, an attachment position error of the optical module, or a tilting angle error of the optical module. Thus An as modified stands as a base device upon which the claimed invention can be seen as an improvement through configuring an image processor to correct image data in an autostereoscopic display based on correction parameters that includes at least one of a specification error of an optical module, an attachment position error of the optical module, or a tilting angle error of the optical module as this would improve the ability of the display to provide a superior image that is not degraded by alignment errors caused from attachment of the optical module.
In the same field of endeavor relating to autostereoscopic image processing and viewing devices, Won teaches that it is known to determine correction parameters relating to the attachment position error or tilting angle error of an optical module that is attached to a display panel and to utilizes such correction parameters in an image processor to correct for such errors (see Won, paragraphs 0003-0010 teaching “three-dimensional image display device displays an image while dividing the image into a left eye image and a right eye image so as to allow a user to feel a three-dimensional effect according to a binocular disparity” and “an optical member including a parallax barrier, a lenticular sheet, and the like is formed in a display device, and optical axes of left and right parallax images are separated from each other, thereby implementing a three-dimensional image. The three-dimensional image display device may be manufactured using a bonding device which bonds the display panel and the optical member to each other” and “Embodiments provide a display device capable of displaying a three-dimensional image with increased reliability, and a method of operating the display device. For example, according to embodiments, the display device includes a display module and an optical member coupled to the display module, and offset data for compensating for an alignment error between the display module and the optical member may be provided” and “a display device includes an optical member including a plurality of three-dimensional lenses, and a display module coupled to the optical member, the display module including a display panel including a plurality of sub-pixels and a storage device configured to store offset data representing a relative arrangement position between the three-dimensional lenses and the sub-pixels. The display device further includes a main controller configured to receive the offset data from the display module by accessing the display module in a power-on mode, and correct image data to be provided to the display module, based on the offset data” such that here attachment position error is determined and stored and used for image correction, and as further explained in paragraphs 0051-0062, the error may be an attachment position error or tilting angle error of an optical module attached to a display panel where “driver integrated circuit 120 may transfer, to the main controller 300, the information of the arrangement position coordinates of the sub-pixels arranged in the display panel 110, the slope angle of the three-dimensional lenses 220 of the optical member 200, and the information of the relative arrangement position between the three-dimensional lenses 220 and the sub-pixels” and “may determine viewing viewpoints of the sub-pixels according to the relative arrangement position between the three-dimensional lenses 220 and the sub-pixels” and “may correct image data input from outside of the main controller 300 according to the position coordinates and the viewing viewpoints of the sub-pixels, thereby generating corrected image data” where “driver integrated circuit 120 may read offset data OFS representing a relative arrangement position between the three-dimensional lenses 220 and the sub-pixels from the storage device 130, and provide the read offset data OFS to the main controller 300, under the control of the main controller 300” and as in paragraphs 0067-0070 “When the optical member 200 is aligned and coupled to the display module 100, an error may occur in the alignment of the optical member 200 and the display module 100 due to various causes. This may mean that a portion of a three-dimensional lens, which each of the unit pixels UP overlaps, is different from an intended portion” and “Due to the alignment error, the angle a between the direction in which the three-dimensional lenses 220 extend and the second direction Y may be different from an intended angle. Also, due to the alignment error, the three-dimensional lenses 220 may be shifted by a specific distance d in the first direction X and/or the second direction Y from an intended position” and “the angle a between the direction in which the three-dimensional lenses 220 extend and the second direction Y and the distance d by which the three-dimensional lenses 220 are shifted may be measured in a test process after a manufacturing process of the display device 1000, and a measured result may be provided as the offset data OFS. The offset data OFS may utilize a relatively small number of data bits, and therefore, a relatively small storage space may be utilized to store the offset data OFS”). Thus Won teaches known techniques applicable to the base system of An as modified.
Therefore it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify An as modified by applying the known technique of Won above as doing so would be no more than application of a known technique to a base system ready for improvement which would yield predictable results and result in an improved system. Here the predictable result of the combination would be that instead of correcting for only the viewing position and other parameters in An as modified, the error correction relating to the optical attachment to the panel would be used as well in the same manner as Won. Won already teaches compatibility with user determined position correction and such correction would simply also involve shifting related to the know alignment errors such that the predictable result would be a combination of shifts based on the viewing position and optical module misalignment errors. This would result in an improved system as it would allow for the device to correct for inevitable manufacturing/production errors or allow for less precise placement as such errors could be dealt with using image processing techniques as suggested by Won (see Won, paragraphs 0006-0009 and 0068-0070 teaching compensating for the alignment error to cure unwanted offsets from attachment issues).
Conclusion
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/SCOTT E SONNERS/Examiner, Art Unit 2613
/XIAO M WU/Supervisory Patent Examiner, Art Unit 2613
1 US PGPUB No. 20140091991
2 US PGPUB No. 20140022634
3 9648306
4 US PGPUB No. 20130194398
5 US Patent No. 6278480
6 US PGPUB No. 20240339060