Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claims 1, 3-4, 6-14, 16-20 objected to because of the following informalities:
Regarding to claims 1, 3-4, 6-14, 16-20: The phrase "PHY" should be -- physical layer--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Das (US 20220012140)
Regarding claim 1:
Das disclose A method, comprising:
monitoring bandwidth utilization on a plurality of ports on a network switch (see fig. 1. [0025-0026] switch/bridge 120 through serial link 119 … multiple devices are capable of being coupled to switch 120 [0051] a flit mode … a higher speed mode may utilize and particularly benefit from Forward Error Correction … it may be desirable to utilize flits for packet transfer when operating in lower speed modes [0074] Mission mode channel error characterization and diagnostics allows such monitoring to be deployed in data centers … Mission mode monitoring enables the data center owner to monitor the electrical channels across several thousand platforms as well as calibrate the parameters using real world workloads and signal.);
determining that the bandwidth utilization on the plurality of ports meets a criterion (([0051] a flit mode when high-speed PAM4 encoding is utilized … a higher speed mode may utilize and particularly benefit from Forward Error Correction. [0080] a threshold number or rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. [0074] Mission mode channel error characterization and diagnostics allows such monitoring to be deployed in data centers … across several thousand platforms. [0103] these errors to determine 1345 a threshold level of errors has been met or exceededl);
disabling at least one serializer/de-serializer component on the network switch in response to determining that the bandwidth utilization on the plurality of ports meets the criterion ([0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link. [0045] the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized. [0025-0026] multiple devices are capable of being coupled to switch 120); and
reconfiguring a PHY on the network switch in response to disabling the at least one serializer/de-serializer component ([0045] the transmitter serializes …The receiver … de-serialized [0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link … Links suffering from a lower error rate may be allowed to function (e.g., and rely upon more standard error detection/correction techniques (e.g., FEC, replay, etc.). [0051] a higher speed mode may utilize and particularly benefit from Forward Error Correction … where a first packet header format is utilized for a mode utilizing flits for the packet transfer … it may be desirable to utilize flits for packet transfer when operating in lower speed modes (e.g., 8b/10b, 128b/130b NRZ). [0103] errors detected on the link (e.g., by PHY-level error detection logic). [0025-0026] switch/bridge 120 through serial link 119 … multiple devices are capable of being coupled to switch 120)
Regarding claim 2:
Das disclose The method of claim 1, further comprising: monitoring the bandwidth utilization using an artificial intelligence algorithm (([0051] a flit mode when high-speed PAM4 encoding is utilized … a higher speed mode may utilize and particularly benefit from Forward Error Correction … [0082] log received error-affected flits in their respective replay buffers for later analysis by post-processing software programs).
Regarding claim 3:
Das disclose The method of claim 1, further comprising: reconfiguring the PHY to reduce an amount of power consumed by the network switch (0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link [0146] During power management, while other power planes are powered down or off … this enabling turning off all of the unnecessary processor components that were previously left powered on during deep sleep states. [0149] dynamic control of the cores or independent core portions can provide for reduced power consumption by powering off components when they are not being used. . [0025-0026] switch/bridge 120 through serial link 119 … multiple devices are capable of being coupled to switch 120. [0103] errors detected on the link (e.g., by PHY-level error detection logic)).
Regarding claim 4:
Das disclose The method of claim 1, further comprising: reconfiguring the PHY to reduce an amount of bandwidth used by the network switch ([0025-0026] switch/bridge 120 through serial link 119 … multiple devices are capable of being coupled to switch 120 … Switch 120, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. [0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined … disable certain functionality of the link … Links suffering from a lower error rate may be allowed to function. [0051] a higher speed mode may utilize and particularly benefit from Forward Error Correction … where a first packet header format is utilized for a mode utilizing flits for the packet transfer … it may be desirable to utilize flits for packet transfer when operating in lower speed modes (e.g., 8b/10b, 128b/130b NRZ). [0103] errors detected on the link (e.g., by PHY-level error detection logic). Note: disable certain functionality of the link is reduce an amount of bandwidth)
Regarding claim 5:
Das disclose The method of claim 1, further comprising: disabling the at least one serializer/de-serializer component while one or more ports coupled to the at least one serializer/de-serializer component is disabled are in use ([0045] the transmitter serializes …The receiver … de-serialized. [0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link … Links suffering from a lower error rate may be allowed to function (e.g., and rely upon more standard error detection/correction techniques (e.g., FEC, replay, etc.). [0051] a higher speed mode may utilize and particularly benefit from Forward Error Correction … where a first packet header format is utilized for a mode utilizing flits for the packet transfer … it may be desirable to utilize flits for packet transfer when operating in lower speed modes. Note: rate of bit errors is logging and triggered is port is disabled are in use).
Regarding claim 6:
Das disclose The method of claim 5, further comprising: reconfiguring the PHY such that a serializer/de-serializer component that is not disabled becomes coupled to the one or more ports coupled to the at least one serializer/de-serializer component that is disabled ([0045] the transmitter serializes …The receiver … de-serialized. [0103] errors detected on the link (e.g., by PHY-level error detection logic [0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link … Links suffering from a lower error rate may be allowed to function (e.g., and rely upon more standard error detection/correction techniques (e.g., FEC, replay, etc.). [0051] a higher speed mode may utilize and particularly benefit from Forward Error Correction … where a first packet header format is utilized for a mode utilizing flits for the packet transfer … it may be desirable to utilize flits for packet transfer when operating in lower speed modes)
Regarding claim 7:
Das disclose The method of claim 1, further comprising: reconfiguring the PHY while the network switch is in an operational mode ([0103] errors detected on the link (e.g., by PHY-level error detection logic. [0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link … Links suffering from a lower error rate may be allowed to function (e.g., and rely upon more standard error detection/correction techniques (e.g., FEC, replay, etc.). [0025-0026] switch/bridge 120 through serial link 119 … multiple devices are capable of being coupled to switch 120 … Switch 120, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Note: rate of bit errors is logging and triggered or links suffering from a lower error rate may be allowed to function is the network switch is in an operational mode)
Regarding claim 8:
Das disclose The method of claim 1, further comprising: disabling the at least one serializer/de-serializer component and reconfiguring the PHY automatically in an absence of an instruction from a user ([0103] errors detected on the link (e.g., by PHY-level error detection logic). [0045] the transmitter serializes …The receiver … de-serialized. 0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link … Links suffering from a lower error rate may be allowed to function [0096] triggering by software).
Regarding claim 9:
Das disclose The method of claim 8, further comprising: reporting that the at least one serializer/de-serializer component was disabled and that the PHY was reconfigured in response to disabling the at least one serializer/de-serializer component and reconfiguring the PHY automatically ([0045] the transmitter serializes …The receiver … de-serialized [0103] errors detected on the link (e.g., by PHY-level error detection logic. [0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link … Links suffering from a lower error rate may be allowed to function (e.g., and rely upon more standard error detection/correction techniques (e.g., FEC, replay, etc.). [0051] a higher speed mode may utilize and particularly benefit from Forward Error Correction … where a first packet header format is utilized for a mode utilizing flits for the packet transfer … it may be desirable to utilize flits for packet transfer when operating in lower speed modes (e.g., 8b/10b, 128b/130b NRZ). [0096] triggering by software. [0145] cache memory in which the processor context is stored during the sleep state [0146] for the sustain power plane may reside on the PCH as well. Note: Logging of disable link in cached/PCH is reporting that the at least one serializer/de-serializer component was disabled)
Regarding claim 11:
Das disclose The method of claim 1, further comprising: disabling the at least one serializer/de-serializer component and reconfiguring the PHY at a particular time selected from a group of times consisting of: a time of a particular day, a day of a particular week, and one more particular days of a given month ([0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined … a logging mode may limit or disable certain functionality of the link. [0074] lane margining or channel error characterization … within a live, operational “runtime” environment … recreate the live signaling (and error) conditions to enable proper diagnosis. [0077] through the logging mode, it is possible to monitor and characterize the links in real world scenarios and at scale as the link is in its live operational mode carrying traffic load from typical user application on a system deployed at the customer site during mission mode … standardized for runtime analysis. Note: run time or live is at a particular time selected from a group of times consisting of: a time of a particular day, a day of a particular week, and one more particular days of a given month)
Regarding claim 12:
Das disclose The method of claim 1, further comprising:
determining that the bandwidth utilization on the plurality of ports no longer meets the criterion ([0051] a higher speed mode may utilize and particularly benefit from Forward Error Correction [0080] a threshold number or rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered… disable certain functionality of the link [0074] Mission mode channel error characterization and diagnostics … across several thousand platforms)
re-enabling the at least one serializer/de-serializer component on the network switch in response to determining that the bandwidth utilization on the plurality of ports no longer meets the criterion (([0045] the transmitter serializes …The receiver … de-serialized. ([0051] a higher speed mode may utilize and particularly benefit from Forward Error Correction … it may be desirable to utilize flits for packet transfer when operating in lower speed modes (e.g., 8b/10b, 128b/130b NRZ. .[0080] rate of bit errors (e.g., correctable and/or uncorrectable errors) may be defined (e.g., in another configuration register), such that when this threshold is met or surpassed, a transition to a logging mode is triggered. In some implementations, a logging mode may limit or disable certain functionality of the link … Links suffering from a lower error rate may be allowed to function. [0145] cache memory in which the processor context is stored during the sleep state. The sustain power plane is also used to power on the processor's wakeup logic that monitors and processes the various wakeup source signal [0146] During power management, while other power planes are powered down or off when the processor enters certain deep sleep states, the sustain power plane remains powered on to support the above-referenced components. Note: Power on or wakeup plane/link is re-enabling the at least one serializer/de-serializer component); and
reconfiguring the PHY on the network switch in response to re-enabling the at least one serializer/de-serializer component ([0045] the transmitter serializes …The receiver … de-serialized [0145] cache memory in which the processor context is stored during the sleep state. The sustain power plane is also used to power on the processor's wakeup logic that monitors and processes the various wakeup source signals. [0146] During power management, while other power planes are powered down or off when the processor enters certain deep sleep states, the sustain power plane remains powered on to support the above-referenced components).
Regarding to claim 13:
Das disclose An apparatus, comprising: one or more network interfaces to communicate with a network (see fig. 1);
a processor coupled to the one or more network interfaces and configured to execute one or more processes (see fig. 1); and
a memory configured to store a process that is executable by the processor (see fig. 1), the process comprising:
[Rejection rationale for claim 1 is applicable].
Regarding to claim 14:
[Rejection rationale for claim 3 is applicable].
Regarding to claim 15:
[Rejection rationale for claim 5 is applicable].
Regarding to claim 16:
[Rejection rationale for claim 6 is applicable].
Regarding to claim 17:
[Rejection rationale for claim 7 is applicable].
Regarding to claim 18:
[Rejection rationale for claim 11 is applicable].
Regarding to claim 19:
[Rejection rationale for claim 12 is applicable].
Regarding to claim 20:
A tangible, non-transitory, computer-readable medium storing program instructions that cause a device to execute a process comprising (] [0215] Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media):
[Rejection rationale for claim 1 is applicable].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under pre- AIA 35 U.S.C. 103(a) are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Das (US 20220012140), in view of Bakke (US7363382)
Regarding claim 10:
Das teaches The method of claim 1,
Das does not explicitly disclose further comprising: disabling the at least one serializer/de-serializer component and reconfiguring the PHY in response to a user command
Bakke teaches further comprising: disabling the at least one serializer/de-serializer component and reconfiguring the PHY in response to a user command (Fig. 4, col 6 lines 10-25 “Block 430 checks whether the connectivity information indicates a manual failover was requested by a user … Block 435 then selects a second IP address (e.g., IPB 154) and goes to block 460 to drop the first network connection (if needed) and to block 470 to establish a second network connection between the host computer and the target using the second IP address. In some embodiments, block 435 selects a second portal and goes to block 460 to drop the first network connection (if needed) and to block 470 to establish a second network connection between the host computer and the target using the second portal
Das teaches a layered protocol stack of network protocols with a PHY layer comprising a transmitter and a receiver. The transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized (Das see fig. 2. [0045] the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized …). Bakke teaches establish a second network connection between the host computer and the target using the second IP address and drop the first network connection when failover was requested by a user. The combination of Das and Bakke teaches disabling the at least one serializer/de-serializer component and reconfiguring the PHY in response to a user command.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to take the teachings of Bakke and apply them on the teachings of Das to further implement disabling the at least one serializer/de-serializer component and reconfiguring the PHY in response to a user command. One would be motivated to do so because in order to improve better system and method to provide checks whether the connectivity information indicates a manual failover was requested by a user then selects a second IP address and goes to drop the first network connection (Fig. 4, col 6 lines 10-25).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEN DOAN whose telephone number is 571 272-4317. The examiner can normally be reached on Monday-Thursday and biweekly Friday 9am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, VIVEK SRIVASTAVA can be reached on (571)272-7304. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HIEN V DOAN/Examiner, Art Unit 2449
/VIVEK SRIVASTAVA/Supervisory Patent Examiner, Art Unit 2449
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