DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 18/792,246 filed on 8/1/2024.
Claims 1-18 have been examined.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/1/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
Claims 10, 11, 12, 13, and 15, are method claims that include one or more contingent clauses, such as “doing X, when Y” or “when Y, do X” and do not explicitly claim that the condition, Y, positively occurs in the claimed language. The broadest reasonable interpretation of these claims does not include those X steps occurring. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04 (II).
Looking at claim 10, for example, the claim states, “determining, by the memory controller, whether to maintain the allocation of a first memory region…when an error is detected…” But the claim never explicitly recites an error being detected while performing the write request. As a result, the broadest reasonable interpretation of this limitation is that an error is not detected and therefore the determining whether to maintain the allocation of a first memory region does not need to occur in the prior art for the claim to be met by the prior art.
Claims 11, 12, 16, 17, and 18 each contain limitations that further define the, “determining whether to maintain the allocation of the first memory region” limitation mentioned above with regards to claim 10. Since the broadest reasonable interpretation of the claims is that this limitation is contingent and as written does not need to occur, the further defining limitations from claims 11, 12, 16, 17, and 18 also do not need to occur in the prior art in order for the prior art to meet the limitations of each respective claim as they merely further define something that is not required to occur within the claim.
The examiner encourages the applicant to positively recite these conditions occurring in the claim limitations so that the resulting steps would be required to occur under the broadest reasonable interpretation of each claim. As an example for claim 10, “determining that an error is detected while performing the write request from the external device in the first memory region; determining, by the memory controller, whether to maintain the allocation of a first memory region from among the at least one of the allocated memory regions based on monitoring the size of written data, when the error is detected while performing the write request from the external device in the first memory region.”
The examiner would like to note, that in the interest of compact prosecution, prior art is being applied to claims 10, 11, 12, 13, and 15, 16, 17, and 18 as if the claims positively recited the limitations in question.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2022/0100419) and Chinnakkonda Vidyapoornachary et al. (US 2016/0224265).
With respect to claim 1, Jang teaches of a memory system comprising: a memory device including a plurality of memory regions (fig. 1-2, 5; paragraph 34, 80-82; where the memory includes multiple zones/super blocks (claimed regions) made up of memory blocks); and
a memory controller configured to control the memory device and to receive an allocation request provided from an external device, and to allocate some of the plurality of memory regions based on the allocation request (fig. 1; paragraph 8, 41-43, where the memory controller receives requests from the host and controls the memory device based on these requests. A write/program operation is received from the host and carried out to the PBA/zone),
wherein the memory controller is configured to perform a write request from the external device to at least one of the allocated memory regions ((fig. 1; paragraph 8, 41-43, 45-46; where the memory controller receives a write/program command from the host and carries it out in the PBA/zone), and
wherein when an error is detected in a first memory region among the allocated memory regions while performing of the write request, the memory controller is configured to determine whether to maintain the allocation of the first memory region (fig. 8, 12, 14; paragraph 87-88, 98-103; where an error is generated while the write data received from the host is moved and is detected by the error detector. The recovery operation controller may allocate a new memory block to the specific zone to store the existing data and the write data with the recovered data).
Jang fails to explicitly teach of (1) to monitor a size of written data in the at least one of the allocated memory regions based on the write request, and (2) wherein when an error is detected in a first memory region among the allocated memory regions while performing of the write request, the memory controller is configured to determine whether to maintain the allocation of the first memory region using the monitored size of written data.
However, Chinnakkonda Vidyapoornachary teaches of to monitor a size of written data in the at least one of the allocated memory regions based on the write request (fig. 4; paragraph 49-50; where it is determined whether the quantity of data stored is below the transfer threshold. Therefore, it is clear to one of ordinary skill in the art that the quantity amount of the data is monitored), and
the memory controller is configured to determine whether to maintain the allocation of the first memory region using the monitored size of written data (fig. 4; paragraph 49-50; where it is determined whether or not to perform a migration of the data based on whether the amount of data stored is under the transfer threshold).
The combination of Jang and Chinnakkonda Vidyapoornachary teaches of wherein when an error is detected in a first memory region among the allocated memory regions while performing of the write request, the memory controller is configured to determine whether to maintain the allocation of the first memory region using the monitored size of written data (Jang, fig. 8, 12, 14; paragraph 87-88, 98-103; Chinnakkonda Vidyapoornachary, fig. 4; paragraph 49-50; where in the combination, the controller determines whether or not to migrate the data of Jang to a second block in the zone based on whether or not the size of the data is below the transfer threshold of Chinnakkonda Vidyapoornachary).
Jang and Chinnakkonda Vidyapoornachary are analogous art because they are from the same field of endeavor, as they are directed to managing the storing of data.
It would have been obvious to one of ordinary skill in the art having the teachings Jang and Chinnakkonda Vidyapoornachary before the time of the effective filing of the claimed invention to incorporate the determining to move the data of Jang based on the transfer threshold of Chinnakkonda Vidyapoornachary. Their motivation would have been to more efficiently use the memory resources.
With respect to claim 10, the combination of Jang and Chinnakkonda Vidyapoornachary teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
With respect to claims 2 and 11, the combination of Jang and Chinnakkonda Vidyapoornachary teaches of wherein when the monitored size of the written data in the first memory region is greater than or equal to a first reference value, the memory controller is configured to recover the error in the first memory region and to continue to use the first memory region as the allocated memory region (Jang, fig. 8, 12, 14; paragraph 87-88, 98-103; Chinnakkonda Vidyapoornachary, fig. 4; paragraph 49-50; where in the combination when the amount of data is above the transfer threshold, the data is not a candidate for being moved. The data error is recovered in Jang).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claims 3 and 12, the combination of Jang and Chinnakkonda Vidyapoornachary teaches of wherein when the monitored size of the written data in the first memory region is less than a second threshold value, the memory controller is configured to allocate a second memory region from among the allocated memory regions, except for the first memory region, and to move the written data of the first memory region to the second memory region (Jang, fig. 8, 12, 14; paragraph 87-88, 98-103; Chinnakkonda Vidyapoornachary, fig. 4; paragraph 49-50; where in the combination, the controller determines to migrate the data of Jang to a second block in the zone when the size of the data is below the transfer threshold of Chinnakkonda Vidyapoornachary. Where a new memory block is allocated to the specific zone and the existing data and write data is moved to the new memory block).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
Claim(s) 4-6 and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang and Chinnakkonda Vidyapoornachary as applied to claims 1 and 10 above, and further in view of Porat et al. (US 7,753,340).
With respect to claim 4 and 13, Jang teaches of the memory controller is configured to allocate a temporary memory region, except for the first memory region, and to move the written data in the first memory region to the temporary memory region (fig. 12; paragraph 116-120; where the recovery operation controller retrieves the existing data and data A from the memory device. As the data is obtained by the recovery operation controller, the controller must have a temporary memory within that stores this obtained data).
The combination of Jang and Chinnakkonda Vidyapoornachary fails to explicitly teach of wherein when the error is detected after transmitting a response signal to the external device indicating performance of the write request in the first memory region.
However, Porat teaches of wherein when the error is detected after transmitting a response signal to the external device indicating performance of the write request in the first memory region (column 7, lines 10-19; where the error is detected after the execution of the data transfer was completed).
Jang, Chinnakkonda Vidyapoornachary, and Porat are analogous art because they are from the same field of endeavor, as they are directed to managing the storing of data.
It would have been obvious to one of ordinary skill in the art having the teachings Jang, Chinnakkonda Vidyapoornachary, and Porat before the time of the effective filing of the claimed invention to incorporate the detection of the error before, during, and after the completion of the command in the combination of Jang and Chinnakkonda Vidyapoornachary as taught in Gunda. Their motivation would have been to more efficiently use the memory.
With respect to claims 5 and 14, Jang teaches of wherein the memory controller is configured to sequentially write the written data in the temporary memory region to the second memory region based on a logical block address of the written data in the temporary memory region (fig. 12; paragraph 41, 116-120; where the existing data and the write data is sequentially stored into the new block).
The reasoning for obviousness is the same as indicated with respect to claims 4 and 13.
With respect to claims 6 and 15, Jang teaches of to allocate the second memory region based on the allocation request from the external device and to re-perform the write request in the second memory region (fig. 12; paragraph 116-120; where a new memory block is allocated to the zone and the data is written into the new block).
The combination of Jang and Chinnakkonda Vidyapoornachary fails to explicitly teach of wherein when the error is detected before transmitting a response signal to the external device indicating performance of the write request in the first memory region.
However, Porat teaches of wherein when the error is detected before transmitting a response signal to the external device indicating performance of the write request in the first memory region, the memory controller is configured to transmit a program error message to the external device, to manage the first memory region as a finished state based on a request from the external device receiving the program error message (fig. 4; column 7, lines 20-32, column 7, line 60-column 8, line 42; where the status is placed into the status buffer. The status processor instructs an error status output to the director and the command itself is not retried to avoid corrupting the data in the memory already written).
The reasoning for obviousness is the same as indicated with respect to claims 4 and 13.
Claim(s) 7-9 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang and Chinnakkonda Vidyapoornachary as applied to claims 1 and 10 above, and further in view of Gunda (US 2022/0066648).
With respect to claims 7 and 16, the combination of Jang and Chinnakkonda Vidyapoornachary fails to explicitly teach of wherein the memory controller is configured to determine whether to maintain the allocation of the first memory region based on a write latency, and wherein the write latency is a time for moving the written data in the first memory region to a second memory region except for the first memory region, based on the monitored size of the written data in the first memory region.
However, Gunda teaches of wherein the memory controller is configured to determine whether to maintain the allocation of the first memory region based on a write latency, and wherein the write latency is a time for moving the written data in the first memory region to a second memory region except for the first memory region, based on the monitored size of the written data in the first memory region (paragraph 26-31; where the relocation of random blocks is delayed; and therefore the allocation of which is maintained in order to maintain a lower latency and reduce the write amplification).
The combination of Jang, Chinnakkonda Vidyapoornachary, and Gunda teaches of wherein the memory controller is configured to determine whether to maintain the allocation of the first memory region based on a write latency, and wherein the write latency is a time for moving the written data in the first memory region to a second memory region except for the first memory region, based on the monitored size of the written data in the first memory region (Gunda, paragraph 26-31; in the combination, the moving of the data is delayed based on the desire to reduce the latency and write amplification).
Jang, Chinnakkonda Vidyapoornachary, and Gunda are analogous art because they are from the same field of endeavor, as they are directed to managing the storing of data.
It would have been obvious to one of ordinary skill in the art having the teachings Jang, Chinnakkonda Vidyapoornachary, and Gunda before the time of the effective filing of the claimed invention to incorporate the delaying of relocating the memory blocks in the combination of Jang and Chinnakkonda Vidyapoornachary as taught in Gunda. Their motivation would have been to more efficiently use the memory.
With respect to claims 8 and 17, the combination of Jang, Chinnakkonda Vidyapoornachary, and Gunda teaches of wherein the memory controller is configured to determine whether to maintain the allocation of the first memory region based on a write amplification factor, and wherein the write amplification factor is obtained by moving the written data in the first memory region to a second memory region except for the first memory region, based on the monitored size of the written data in the first memory region (Gunda, paragraph 26-31; in the combination, the moving of the data is delayed based on the desire to reduce the latency and write amplification as taught in Gunda).
The reasoning for obviousness is the same as indicated above with respect to claims 7 and 16.
With respect to claims 9 and 18, the combination of Jang, Chinnakkonda Vidyapoornachary, and Gunda teaches of the limitations cited and described above with respect to claims 7-8 and 16-17 for the same reasoning cited with respect to claims 7-8 and 16-17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Stoller et al. (US 2022/0300366) discloses performing background scans of the memory to determine error. When the error metric is below a threshold, the data is refreshed and relocated.
Choi et al. (US 2024/0070067) discloses the memory controller triggers migration of previously written data to the recovery area such that the data written in the target zone before the access error occurs are read from the target zone and the read data are written in the recovery area.
Earhart (US 2016/0283308) discloses a Read After Write (verify method which allows storage defects and write errors to be detected immediately and corrected.
Naik et al. (US 2018/0189135) discloses verifying programmed data after the data is written. Correction of error is performed based on the error rate in comparison to two different thresholds.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138