DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-19, of the instant application are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-4, 6-8, 10-11, 13-16, and 19-20, of US Patent 12,081,247 B2, as being described below. The patent claims include all of the limitations of the instant application claims, respectively. The patent claims also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims. As such, the instant application claims are anticipated by the patent claims and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”).
Instant Application 18/792,306.
US Patent 12,081,247 B2
Claims 1+2+4+8. A receiver circuit comprising: first mixer circuits that multiply first frequencies from first received signals by second frequencies of carrier signals to generate first demodulated signals, wherein the first received signals are indicative of first radio frequency signals; a first summing circuit that sums third frequencies from each of the first demodulated signals to generate a first summed signal; a first analog-to-digital converter circuit that converts the first summed signal into a first digital signal having fourth frequencies that are generated based on each of the first received signals; second mixer circuits that multiply fifth frequencies from second received signals by the second frequencies of the carrier signals to generate second demodulated signals, wherein the second received signals are indicative of second radio frequency signals; a second summing circuit that sums sixth frequencies from each of the second demodulated signals to generate a second summed signal; and a second analog-to-digital converter circuit that converts the second summed signal into a second digital signal.
2. The receiver circuit of claim 1, wherein the second digital signal has seventh frequencies that are generated based on each of the second received signals.
Claim 4.The receiver circuit of claim 1 further comprising: a channelizer circuit that separates the fourth frequencies from the first digital signal in a digital domain into first output signals based on the first radio frequency signals, wherein each of the first output signals has the third frequencies from a different one of the first demodulated signals.
8. The receiver circuit of claim 1, wherein each of the carrier signals has a unique frequency relative to other ones of the carrier signals.
Claim 3. The receiver circuit of claim 1 further comprising: amplification circuits that generate amplified signals by amplifying the first demodulated signals, wherein each of the amplification circuits comprises a low pass filter circuit that filters one of the first demodulated signals to generate one of the amplified signals, and wherein the first summing circuit sums seventh frequencies from the amplified signals to generate the first summed signal.
5. The receiver circuit of claim 4 further comprising: timing circuits that generate second output signals by delaying or shifting phases of the first output signals; and a processing circuit that performs a digital beam forming algorithm using information indicated by the second output signals.
6. The receiver circuit of claim 1 further comprising: filter circuits that filter the first demodulated signals to generate filtered signals, wherein the first summing circuit sums seventh frequencies from each of the filtered signals to generate the first summed signal.
7. The receiver circuit of claim 1, wherein the first analog-to-digital converter circuit has a first bandwidth that is greater than or equal to a second bandwidth of the first summed signal.
9. The receiver circuit of claim 1 further comprising: amplification circuits that generate amplified signals by amplifying the first received signals, wherein the first mixer circuits multiply seventh frequencies of the amplified signals by the second frequencies of the carrier signals to generate the first demodulated signals.
10+12+15. A transmitter circuit comprising: a first digital-to-analog converter circuit that converts a first digital signal into a first analog signal; a first splitter circuit that separates first frequencies from the first analog signal to generate first split signals; first filter circuits that filter second frequencies from the first split signals to generate first filtered signals having non-overlapping bandwidths; first mixer circuits that multiply third frequencies from the first filtered signals by fourth frequencies of carrier signals to generate first modulated signals; second filter circuits that generate second filtered signals by filtering the first modulated signals; a second digital-to-analog converter circuit that converts a second digital signal into a second analog signal; a second splitter circuit that separates fifth frequencies from the second analog signal to generate second split signals; third filter circuits that filter sixth frequencies from the second split signals to generate third filtered signals having non-overlapping bandwidths; and second mixer circuits that multiply seventh frequencies from the third filtered signals by the fourth frequencies of the carrier signals to generate second modulated signals.
12. The transmitter circuit of claim 10, wherein each of the carrier signals has a unique frequency relative to other ones of the carrier signals.
15. The transmitter circuit of claim 10 further comprising: a processing circuit that generates phase shifted or delayed frequencies in the first digital signal using a digital beam forming algorithm to cause radio frequency signals to have different phases or delays in order to steer a wave front of the radio frequency signals in a selected direction.
11. The transmitter circuit of claim 10 further comprising: amplification circuits that generate amplified signals by amplifying the second filtered signals, wherein radio frequency signals are generated based on the amplified signals.
13. The transmitter circuit of claim 10, wherein a processing circuit generates the first digital signal using information from radio frequency signals received by a receiver circuit.
14. The transmitter circuit of claim 10 further comprising: local oscillator circuits that generate the carrier signals, wherein the local oscillator circuits cause the carrier signals to have different ones of the fourth frequencies.
16+17. A method for receiving first and second radio frequency signals at a receiver circuit, wherein the method comprises: multiplying first frequencies from first electrical signals by second frequencies of carrier signals to generate first demodulated signals using first mixer circuits, wherein the first electrical signals are indicative of the first radio frequency signals; summing third frequencies from each of the first demodulated signals to generate a first summed signal using a first summing circuit; converting the first summed signal into a first digital signal using a first analog-to-digital converter circuit, wherein the first analog-to-digital converter circuit causes the first digital signal to have fourth frequencies that are generated based on the first electrical signals; multiplying fifth frequencies from second electrical signals by the second frequencies of the carrier signals to generate second demodulated signals using second mixer circuits, wherein the second electrical signals are indicative of the second radio frequency signals; summing sixth frequencies from each of the second demodulated signals to generate a second summed signal using a second summing circuit; and converting the second summed signal into a second digital signal using a second analog-to-digital converter circuit, wherein the second analog-to-digital converter circuit causes the second digital signal to have seventh frequencies that are generated based on the second electrical signals.
17. The method of claim 16 further comprising: separating the fourth frequencies from the first digital signal in a digital domain into first digital output signals based on eighth frequencies of the first radio frequency signals using a channelizer circuit, wherein each of the first digital output signals has ninth frequencies from a different one of the first demodulated signals.
18. The method of claim 17 further comprising: generating second digital output signals by delaying or shifting phases of the first digital output signals corresponding to a direction of a beam.
19. The method of claim 18 further comprising: performing a digital beam forming algorithm with a processing circuit using information indicated by the second digital output signals.
Claim 1+8. An electronically scanned array antenna system comprising a receiver circuit, wherein the receiver circuit comprises: first antennas that generate first received signals indicative of first frequencies of first radio frequency signals received by the first antennas; first mixer circuits that multiply second frequencies from the first received signals by third frequencies of carrier signals to generate first demodulated signals, wherein each of the carrier signals has a unique frequency relative to other ones of the carrier signals; a first summing circuit that sums fourth frequencies from each of the first demodulated signals to generate a first summed signal; a first analog-to-digital converter circuit that converts the first summed signal into a first digital signal having fifth frequencies that are generated based on each of the first received signals generated by the first antennas; programmable tuner circuits that generate first output signals that each comprise a subset of the first frequencies received by one of the first antennas; and a channelizer circuit that separates the fifth frequencies from the first digital signal in a digital domain into second output signals based on the first frequencies of the first radio frequency signals received by the first antennas, wherein each of the second output signals has the fourth frequencies from a different one of the first demodulated signals.
8. The electronically scanned array antenna system of claim 1, wherein the receiver circuit further comprises: second antennas that generate second received signals indicative of sixth frequencies of second radio frequency signals received by the second antennas; second mixer circuits that multiply seventh frequencies from the second received signals by the third frequencies of the carrier signals to generate second demodulated signals; a second summing circuit that sums eighth frequencies from each of the second demodulated signals to generate a second summed signal; and a second analog-to-digital converter circuit that converts the second summed signal into a second digital signal.
Claim 3. The electronically scanned array antenna system of claim 1, wherein the receiver circuit further comprises: amplification circuits that generate amplified signals by amplifying the first demodulated signals, wherein each of the amplification circuits comprises a low pass filter circuit that filters one of the first demodulated signals to generate one of the amplified signals, and wherein the first summing circuit sums sixth frequencies from the amplified signals to generate the first summed signal.
4. The electronically scanned array antenna system of claim 1, wherein the receiver circuit further comprises: timing circuits that generate third output signals by delaying or shifting phases of the second output signals.
6. The electronically scanned array antenna system of claim 1 further comprising filter circuits that filter the first demodulated signals to generate filtered signals, wherein the first summing circuit sums sixth frequencies from each of the filtered signals to generate the first summed signal.
7. The electronically scanned array antenna system of claim 1, wherein the first analog-to-digital converter circuit has a first bandwidth that is greater than or equal to a second bandwidth of the first summed signal.
2.The electronically scanned array antenna system of claim 1, wherein the receiver circuit further comprises: amplification circuits that generate amplified signals by amplifying the first received signals, wherein the first mixer circuits multiply sixth frequencies of the amplified signals by the third frequencies of the carrier signals to generate the first demodulated signals.
10+15. An electronically scanned array antenna system comprising a transmitter circuit, wherein the transmitter circuit comprises: a first digital-to-analog converter circuit that converts a first digital signal into a first analog signal; a first splitter circuit that separates first frequencies from the first analog signal to generate first split signals; first filter circuits that filter second frequencies from the first split signals to generate first filtered signals having non-overlapping bandwidths; first mixer circuits that multiply third frequencies from the first filtered signals by fourth frequencies of carrier signals to generate first modulated signals, wherein each of the carrier signals has a unique frequency relative to other ones of the carrier signals; second filter circuits that generate second filtered signals by filtering the first modulated signals; first antennas that generate first radio frequency signals based on fifth frequencies from the second filtered signals; and a processing circuit that generates phase shifted or delayed frequencies in the first digital signal using a digital beam forming algorithm to cause the first radio frequency signals generated by the first antennas to have different phases or delays in order to steer a wave front of the first radio frequency signals in a selected direction.
15. The electronically scanned array antenna system of claim 10, wherein the transmitter circuit further comprises: a second digital-to-analog converter circuit that converts a second digital signal into a second analog signal; a second splitter circuit that separates sixth frequencies from the second analog signal to generate second split signals; third filter circuits that filter seventh frequencies from the second split signals to generate third filtered signals having non-overlapping bandwidths; second mixer circuits that multiply eighth frequencies from the third filtered signals by the fourth frequencies of the carrier signals to generate second modulated signals; and second antennas that generate second radio frequency signals based on ninth frequencies from the second modulated signals.
11. The electronically scanned array antenna system of claim 10, wherein the transmitter circuit further comprises: amplification circuits that generate amplified signals by amplifying the second filtered signals, wherein the first antennas generate the first radio frequency signals based on the amplified signals.
13. The electronically scanned array antenna system of claim 10, wherein the processing circuit generates the first digital signal using information from second radio frequency signals received by a receiver circuit.
14. The electronically scanned array antenna system of claim 10, wherein the transmitter circuit further comprises: local oscillator circuits that generate the carrier signals, wherein the local oscillator circuits cause the carrier signals to have different ones of the fourth frequencies.
16. A method for receiving radio frequency signals at a receiver circuit in an electronically scanned array antenna system, wherein the method comprises: generating electrical signals indicative of first frequencies of the radio frequency signals that are received by antennas; multiplying second frequencies from the electrical signals by third frequencies of carrier signals to generate demodulated signals using mixer circuits, wherein each of the carrier signals has a unique frequency relative to other ones of the carrier signals; filtering the demodulated signals to generate filtered signals using filter circuits; summing fourth frequencies from each of the filtered signals to generate a summed signal using a summing circuit; converting the summed signal into a digital signal using an analog-to-digital converter circuit, wherein the analog-to-digital converter circuit causes the digital signal to have fifth frequencies that are generated based on the electrical signals generated by the antennas; and separating the fifth frequencies from the digital signal in a digital domain into first digital output signals based on the first frequencies of the radio frequency signals received by the antennas using a channelizer circuit, wherein each of the first digital output signals has sixth frequencies from a different one of the demodulated signals.
19. The method of claim 16 further comprising: generating second digital output signals by delaying or shifting phases of the first digital output signals corresponding to a direction of a beam.
20. The method of claim 19 further comprising: performing a digital beam forming algorithm with a processing circuit using information indicated by the second digital output signals.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 8-9, and 16, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tu (US PGPUB 2014/0169418 A1).
As per claim 1, Tu discloses a receiver circuit (Tu, Figs. 2, 8, and 10) comprising:
first mixer circuits (Tu, Fig. 2:203a) that multiply first frequencies from first received signals by second frequencies of carrier signals to generate first demodulated signals (Tu, Fig. 2:203a1:203a2:203a3), wherein the first received signals are indicative of first radio frequency signals (Tu, Fig. 2:202, and paragraph 30);
a first summing circuit (Tu, Fig. 2:203b) that sums third frequencies from each of the first demodulated signals to generate a first summed signal (Tu, Fig. 2, output of mixers to adder 203b);
a first analog-to-digital converter circuit that converts the first summed signal into a first digital signal having fourth frequencies that are generated based on each of the first received signals (Tu, Fig. 2:204, and Fig. 10:1004c, and paragraph 37, discloses The second signal processing unit 1004 can be realized with … an analog-to-digital converter (ADC));
second mixer circuits (Tu, Fig. 2:203a) that multiply fifth frequencies from second received signals by the second frequencies of the carrier signals to generate second demodulated signals (Tu, Fig. 2:203a), wherein the second received signals are indicative of second radio frequency signals (Tu, Fig. 2:202, and paragraph 30);
a second summing circuit (Tu, Fig. 2:203b) that sums sixth frequencies from each of the second demodulated signals to generate a second summed signal (Tu, Fig. 2:203b, output); and
a second analog-to-digital converter circuit that converts the second summed signal into a second digital signal (Tu, Fig. 2:204, and Fig. 10:ADC, shows a second ADC).
As per claim 2, Tu further discloses the receiver circuit of claim 1, wherein the second digital signal has seventh frequencies that are generated based on each of the second received signals (Tu, Fig. 10, output of second ADC).
As per claim 6, Tu further discloses the receiver circuit of claim 1 further comprising: filter circuits (Tu, Fig. 10:1004a) that filter the first demodulated signals to generate filtered signals (Tu, Fig. 10:1003:1004a), wherein the first summing circuit sums seventh frequencies from each of the filtered signals to generate the first summed signal (Tu, Fig. 10:1003:1004a).
As per claim 8, Tu further discloses the receiver circuit of claim 1, wherein each of the carrier signals has a unique frequency relative to other ones of the carrier signals (Tu, Fig. 2, shows oscillator).
As per claim 9, Tu further discloses the receiver circuit of claim 1 further comprising: amplification circuits (Tu, Fig. 10:LNA) that generate amplified signals by amplifying the first received signals (Tu, Fig. 10:1001:1002:LNA), wherein the first mixer circuits multiply seventh frequencies of the amplified signals by the second frequencies of the carrier signals to generate the first demodulated signals (Tu, Fig. 10:1002:1003).
As per claim 16, Tu discloses a method for receiving first and second radio frequency signals at a receiver circuit (Tu, Figs. 2, 8, and 10), wherein the method comprises:
multiplying first frequencies from first electrical signals by second frequencies of carrier signals to generate first demodulated signals using first mixer circuits (Tu, Fig. 2:203a1:203a2:203a3), wherein the first electrical signals are indicative of the first radio frequency signals (Tu, Fig. 2:202, and paragraph 30);
summing third frequencies from each of the first demodulated signals to generate a first summed signal using a first summing circuit (Tu, Fig. 2:203b);
converting the first summed signal into a first digital signal using a first analog-to-digital converter circuit (Tu, Fig. 2:204, and Fig. 10:1004c, and paragraph 37, discloses The second signal processing unit 1004 can be realized with … an analog-to-digital converter (ADC)), wherein the first analog-to-digital converter circuit causes the first digital signal to have fourth frequencies that are generated based on the first electrical signals (Tu, Fig. 2:202:204);
multiplying fifth frequencies from second electrical signals by the second frequencies of the carrier signals to generate second demodulated signals using second mixer circuits (Tu, Fig. 2:203a), wherein the second electrical signals are indicative of the second radio frequency signals (Tu, Fig. 2:202, and paragraph 30);
summing sixth frequencies from each of the second demodulated signals to generate a second summed signal using a second summing circuit (Tu, Fig. 2:203b); and
converting the second summed signal into a second digital signal using a second analog-to-digital converter circuit (Tu, Fig. 2:204, and Fig. 10:ADC, shows a second ADC), wherein the second analog-to-digital converter circuit causes the second digital signal to have seventh frequencies that are generated based on the second electrical signals (Tu, Fig. 2:202:204, and Fig. 10:ADC, shows output of second ADC).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, is/are rejected under 35 U.S.C. 103 as being unpatentable over Tu (US PGPUB 2014/0169418 A1) and further in view of Morrison (US PGPUB 2018/0278299 A1) and further in view of Husted (US PGPUB 2004/0235439 A1).
As per claim 3, Tu further discloses the receiver circuit of claim 1 further comprising: Tu does not explicitly disclose amplification circuits that generate amplified signals by amplifying the first demodulated signals, and wherein the first summing circuit sums seventh frequencies from the amplified signals to generate the first summed signal.
Morrison discloses amplification circuits that generate amplified signals by amplifying the first demodulated signals (Morrison, Fig. 5:509a:509b), and wherein the first summing circuit sums seventh frequencies from the amplified signals to generate the first summed signal (Morrison, Fig. 3:308).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu teachings by adjusting bandwidth of ADC, as taught by Morrison.
The motivation would be to provide an improved architecture for digital distributed antenna system (paragraph 10), as taught by Morrison.
Tu in view of Morrison does not explicitly disclose wherein each of the amplification circuits comprises a low pass filter circuit that filters one of the first demodulated signals to generate one of the amplified signals,
Husted discloses wherein each of the amplification circuits comprises a low pass filter circuit (Husted, paragraph 32) that filters one of the first demodulated signals to generate one of the amplified signals (Husted, Fig. 1:145-Q and 145-IP),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu in view of Morrison teachings by adjusting bandwidth of ADC, as taught by Morrison.
The motivation would be to provide a wireless circuits to operate simultaneously without reducing communication system efficiency and without increasing cost and complexity (paragraph 11), as taught by Husted.
Claim(s) 7 and 20, is/are rejected under 35 U.S.C. 103 as being unpatentable over Tu (US PGPUB 2014/0169418 A1) and further in view of Morrison (US PGPUB 2018/0278299 A1).
As per claim 7, Tu further discloses the receiver circuit of claim 1, wherein the Tu does not explicitly disclose first analog-to-digital converter circuit has a first bandwidth that is greater than or equal to a second bandwidth of the first summed signal.
Morrison discloses first analog-to-digital converter circuit has a first bandwidth that is greater than or equal to a second bandwidth of the first summed signal (Morrison, paragraph 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu teachings by adjusting bandwidth of ADC, as taught by Morrison.
The motivation would be to provide an improved architecture for digital distributed antenna system (paragraph 10), as taught by Morrison.
As per claim 20, please see the analysis of claim 7.
Conclusion
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/SYED HAIDER/Primary Examiner, Art Unit 2633
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