Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 17-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190393240 A1) hereafter referred to as Kim
In regard to claim 1 Kim teaches a [“FIG. 3 is a plan view of a three-dimensional semiconductor memory device”] 3D chip package structure, comprising:
a memory device [“three-dimensional semiconductor memory device”] comprising:
a memory wafer layer [“Memory cell array regions MA1 and MA2 may be sequentially arranged on the base substrate 115”] comprising at least one memory partition; and
a connecting layer [“Referring to FIGS. 3, 4, 5 and 6, a lower structure 110 including a peripheral circuit 107 may be disposed on a lower substrate 105. The lower substrate 105 may be, for example, a semiconductor substrate that may be formed of a semiconductor material such as, single crystal silicon or the like”] disposed at one side [i.e. bottom] of the memory wafer layer;
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wherein the connecting layer comprises at least one connecting quiet zone [i.e. on left and right in Fig. 4] and at least one connecting area [i.e. in the middle in Fig. 4], the at least one connecting quiet zone and the at least one connecting area are corresponding to [“The peripheral contact plugs P_Pa may pass through the gap-fill insulating layer 117 and the penetration region TH, to be electrically connected to the peripheral circuit 107” “Gate connection wirings G_Ia may be disposed to electrically connect the gate contact plugs G_Pa and the peripheral contact plugs P_Pa to each other”] the at least one memory partition, the at least one connecting quiet zone is adjacent to [see Fig. 3 Fig. 4] the at least one connecting area,
but does not state an area of the at least one connecting quiet zone is equal to or larger than the at least one connecting area.
However see that the memory comprises two parts i.e. the actual memory vertical channels “memory cell array regions MA1” “Bit lines BL as described above with reference to FIGS. 1 and 2 may be disposed on the vertical channel structures VS” where the memory is located and the gate electrodes G_L, G_M connections “In the first and second inner stepped regions C_ST1 and C_ST2, the inner intermediate contact pad C_Ma may include first intermediate contact pads C_Ma1 arranged in a stepped shape by the word lines of the first gate stack structure GS1”, whereas the “bridge region BG” has only one i.e. the “peripheral contact plugs P_Pa”, thus the “bridge region BG” occupies less area, see for example in Fig. 4 the P_Pa goes up, connects to a G_Pa and comes back down, however then the actual memory vertical channels also occupies space further to the left and right in Fig. 4.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include an area of the at least one connecting quiet zone is equal to or larger than the at least one connecting area.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to provide enough space for “the vertical channel structures VS” because in the memory architecture Kim does not say that the “peripheral contact plugs P_Pa” in the “bridge region BG” are not similar to the gate contact plugs G_Pa however additionally in the “memory cell array regions MA1” space is also needed for “the vertical channel structures VS”.
In regard to claim 2 Kim teaches wherein the connecting layer comprises at least one connecting pad [see Fig. 4 at the bottom of P_Pa “Peripheral contact plugs P_Pa may be disposed on the peripheral circuit 107” i.e. the part of 107 to which P_Pa connects is the “connecting pad”, the other parts of “peripheral circuit 107” is not “connecting pad”], and the at least one connecting pad is only disposed in the at least one connection area.
In regard to claim 3 Kim teaches further comprising at least one conductive pillar [see Fig. 4 the P_Pa “Peripheral contact plugs P_Pa may be disposed on the peripheral circuit 107” i.e. the part of 107 to which P_Pa connects is the “connecting pad”] connected to the at least one connecting pad, wherein the at least one conductive pillar is disposed corresponding to the at least one connection area.
In regard to claim 4 Kim teaches wherein the at least one connecting area is adjacent to an [see Fig. 4 the P_Pa is at edge of the bottommost gate electrodes G_L, G_M i.e. the edge of “first and second inner stepped regions C_ST1 and C_ST2”] edge of the at least one memory partition.
In regard to claim 5 Kim teaches wherein the at least one connecting area is more [see Fig. 3 see that the connections from the “bridge region BG” go to the left, right, top and bottom] than two connecting areas, and the at least one connecting quiet zone is one connecting quiet zone disposed between [see Fig. 3 is a repeating unit accross the die area] the any two of connecting areas.
In regard to claim 6 Kim teaches wherein the at least one connecting quiet zone is more [see Fig. 3 see that the connections from the “bridge region BG” go to the left, right, top and bottom] than two connecting quiet zones, and each area of the connecting quiet zones are same [see Fig. 3 the top and bottom appear different than left and right] or different.
In regard to claim 7 Kim teaches wherein each area of the connecting areas [see Fig. 3 see that the connections from the “bridge region BG” go to the left, right, top and bottom, see Fig. 3 the top and bottom appear different than left and right] are same or different.
In regard to claim 8 Kim teaches further comprising: a logic circuit device [“Referring to FIGS. 3, 4, 5 and 6, a lower structure 110 including a peripheral circuit 107 may be disposed on a lower substrate 105. The lower substrate 105 may be, for example, a semiconductor substrate that may be formed of a semiconductor material such as, single crystal silicon or the like”] connected to the memory device through the at least one conductive pillar and comprising: at least one circuit component [“peripheral circuit 107”], wherein a vertical projection of the at least one circuit component overlaps [see 105 overlaps the MA1, MA2 and C_ST1 and C_ST2] with a vertical projection of the at least one connecting quiet zone.
In regard to claim 9 Kim teaches wherein the logic circuit device comprises [“peripheral circuit 107 may be a circuit that may be formed in the control logic region 30” see Fig. 4 at the bottom of P_Pa “Peripheral contact plugs P_Pa may be disposed on the peripheral circuit 107”] at least one memory controller, and the at least one memory controller is electrically connected to the at least one conductive pillar.
In regard to claim 10 Kim teaches wherein the memory device comprises at least one redistribution layer [see Fig. 4 “peripheral circuit 107 may include peripheral wirings electrically connecting peripheral transistors, to constitute the peripheral transistors and circuits. The lower structure 110 may include the lower insulator 109 covering the peripheral circuit 107”], and the redistribution layer is disposed between the memory wafer layer and the connecting layer.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ha et al. (US 20190088566 A1) hereafter referred to as Ha
In regard to claim 11 Kim does not specifically teach wherein a thickness of the at least one redistribution layer is between 0.7μm to 0.9μm.
However this is common in the art, see Ha paragraph 0081 “The redistribution layers 142 may include via pad patterns, electrical connection structure pad patterns, and the like. Each of the redistribution layers 142 may have a thickness of approximately 0.5 μm to 15 μm”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include wherein a thickness of the at least one redistribution layer is between 0.7μm to 0.9μm.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that these dimensions are known to give good results for redistribution layer.
Claim(s) 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee et al. (US 20230162768 A1) hereafter referred to as Lee
In regard to claim 12 Kim teaches wherein the memory wafer layer comprises: circuit components connected in parallel to each other [see Fig. 2 the “Bit lines BL as described above with reference to FIGS. 1 and 2 may be disposed on the vertical channel structures VS”, see the channels are in parallel] and electrically connected to a power terminal [see BL on top] for receiving a source voltage; but does not teach and a compensation circuit electrically connected to the circuit components for outputting a compensation voltage to the circuit components; wherein at least one of the circuit components is away from the power terminal.
See Lee Fig. 10A see “FIG. 10A is a diagram illustrating an exemplary circuit diagram of a memory cell 1000a within the memory array circuit 200 or 800 in accordance with some embodiments of the present disclosure. As shown in FIG. 10A, in some embodiments, the memory cell 1000a includes eight units 1010-1080, in which seven units 1010-1070 are coupled in parallel, and a separate unit 1080 is coupled to a low-dropout regulator LDO to receive an external control voltage via a separated word line WLX. For example, each of the units 1010-1070 includes two transistors 1012 and 1014, . . . , 1072 and 1074 coupled in series. The unit 1080 includes transistors 1082 and 1084 coupled in series. In other embodiments, the number of units arranged within the memory cell 1000a may be four or sixteen, or any other practical number” “A capacitor 1090 is coupled between the bit line BL”. See that ground is a power terminal.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include and a compensation circuit electrically connected to the circuit components for outputting a compensation voltage to the circuit components; wherein at least one of the circuit components is away from the power terminal.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to regulate the current using the LDO for stable operation.
In regard to claim 13 Kim teaches wherein the compensation circuit is electrically connected to one connecting pad [see combination, this is from the LDO] for receiving a compensation source voltage.
In regard to claim 14 Kim teaches wherein the compensation circuit [see Lee Fig. 10A see LDO] is a low-dropout regulator.
In regard to claim 15 Kim teaches wherein the compensation voltage [see Lee Fig. 10A see source of 1084] is equal to the source voltage.
In regard to claim 16 Kim teaches wherein the power terminal [see combination this is ground, i.e. the Fig. 4 of Kim uses the same ground because ground is common] is electrically connected to one connecting pad.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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