DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of information disclosure statement(s) filed 20 may 2025 and 2 August 2024 respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 - 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harn et al; (Publication number: US 2011/0115057 A1), hereafter Harn, in view of Huang et al; (Publication number: US 2023/0317638 A1), hereafter Huang.
Regarding claim 1:
Harn discloses a wafer structure (Harn Figure 1 100), comprising:
a substrate (Harn [0014]);
a scribe line defining a chip unit on the substrate (Harn Figure 2 104; [0016]);
a chip circuit pattern disposed in a central region of the chip unit (Harn [0017] Figure 2 200); and
a peripheral metal pattern disposed at a peripheral region of the chip unit and surrounding the central region, wherein the peripheral metal pattern comprises a seal ring pattern surrounding the central region (Harn Figure 5 seal ring 212 of metal region surrounds the central region 210), and an alignment pattern (Harn Figure 5 304,306).
Harn does not disclose the alignment pattern disposed between the scribe line and the seal ring pattern.
However, Huang discloses a semiconductor device having functional patterns in redundant patterns in redundant regions of double seal ring. More particularly, Huang discloses a double seal ring comprising an inner seal ring 300 and outer signal ring 350 (see Huang Figure 1).
It would have been obvious to modify Harn to include a double seal ring such that the alignment pattern disposed between the scribe line and the seal ring pattern, as claimed. Those skilled in the art would appreciate the ability to support both separate dies and connected dies, depending on whether openings are left in the inner seal rings for interconnects.
Regarding claim 2:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein the seal ring pattern comprises a chamfer to vacate a corner region in the chip unit, and the alignment pattern is disposed in a corner region vacated by the chamfer (Harn [0024] relief zone 214).
Regarding claim 3:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein the peripheral metal pattern further comprises a plurality of dummy metal pads evenly distributed between the seal ring pattern and the alignment pattern (disclosed in combination by Huang Figure 1 functional patterns 410 and Harn Figure 5 304, 306).
Regarding claim 4:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein an outer edge of the alignment pattern is substantially collinear with an outer edge of the corresponding seal ring pattern (see Harn Figure 4 and positions of seal ring 212 and 304, 306).
Regarding claim 5:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein the alignment pattern is not overlapped with the scribe line when viewed from a top view direction (see Harn Figure 5).
Regarding claim 6:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein the chip circuit pattern is electrically insulated from the peripheral metal pattern (Harn [0024] or example, the seal ring may comprise a plurality of conductive layers, a plurality of insulating layers).
Regarding claim 7:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein the alignment pattern is L-shaped, square-shaped, cross-shaped, Z-shaped, or hourglass-shaped (Harn Figure 5 304, 306 square shaped).
Regarding claim 8:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein the seal ring pattern comprises a plurality of seal ring pattern layers disposed on the substrate in an overlapping manner (Huang Figure 1 300 and 350 seal rings are on overlapped along the y-direction).
Regarding claim 9:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein the alignment pattern comprises a plurality of alignment pattern layers disposed on the substrate in an overlapping manner and respectively disposed on a same layer as the corresponding plurality of seal ring pattern layers (Harn Figure 5 306, 304 are overlapping in X and Y direction as illustrated).
Regarding claim 10:
Harn (in view of Huang) discloses the wafer structure of claim 1, wherein the seal ring pattern comprises an inner seal ring pattern surrounding the central region and an outer seal ring pattern surrounding the inner seal ring pattern (disclosed in combination by Huang 350 and 300).
Regarding claim 11:
Harn (in view of Huang) discloses the wafer structure of claim 10, wherein the alignment pattern is disposed between the scribe line and the outer seal ring pattern (disclosed in combination of Huang Figure 1 350 at left side of 150 and Harn Figure 5 212).
Regarding claim 12:
Harn discloses a chip structure (Harn Figure 5 210), comprising:
a substrate comprising a central region and a peripheral region surrounding the central region (Harn Figure 1 [0014]);
a chip circuit pattern disposed at the central region (Harn [0017]); and
a peripheral metal pattern disposed at the peripheral region and comprising a seal ring pattern surrounding the chip circuit pattern, (Harn Figure 5 seal ring 212 of metal region surrounds the central region 210), and an alignment pattern (Harn Figure 5 304,306).
Harn does not disclose the alignment pattern disposed outside a closed region defined by the seal ring pattern.
However, Huang discloses a semiconductor device having functional patterns in redundant patterns in redundant regions of double seal ring. More particularly, Huang discloses a double seal ring comprising an inner seal ring 300 and outer signal ring 350 (see Huang Figure 1).
It would have been obvious to modify Harn to include a double seal ring such that the alignment pattern disposed between the scribe line and the seal ring pattern, as claimed. Those skilled in the art would appreciate the ability to support both separate dies and connected dies, depending on whether openings are left in the inner seal rings for interconnects.
Regarding claim 13:
Harn (in view of Huang) discloses the chip structure of claim 12, wherein the alignment pattern is disposed between an outer edge of the chip structure and the seal ring pattern (disclosed in combination of Huang 300 and Harn 306,304).
Regarding claim 14:
Harn (in view of Huang) discloses the chip structure of claim 12, wherein the seal ring pattern has a chamfer corresponding to a corner of the substrate, and the alignment pattern is disposed at the corner vacated by the chamfer (Harn [0024] relief zone 214).
Regarding claim 15:
Harn discloses a wafer structure (Harn Figure 1 100), comprising:
a substrate (Harn [0014]);
a scribe line defining a chip unit on the substrate (Harn Figure 5 104);
a chip disposed in the chip unit (Harn Figure 5 210); and
a seal ring surrounding the chip and located between the scribe line and the chip (Harn Figure 5 seal ring 212 of metal region surrounds the central region 210); and an alignment pattern (Harn Figure 5 304,306).an alignment mark
Harn does not disclose the alignment mark disposed between the scribe line and the seal ring.
However, Huang discloses a semiconductor device having functional patterns in redundant patterns in redundant regions of double seal ring. More particularly, Huang discloses a double seal ring comprising an inner seal ring 300 and outer signal ring 350 (see Huang Figure 1).
It would have been obvious to modify Harn to include a double seal ring such that the alignment pattern disposed between the scribe line and the seal ring, as claimed. Those skilled in the art would appreciate the ability to support both separate dies and connected dies, depending on whether openings are left in the inner seal rings for interconnects.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIHIR K RAYAN whose telephone number is (571)270-5719. The examiner can normally be reached Monday - Friday 9 - 5pm (EST).
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/MIHIR K RAYAN/ 5 August 2026Primary Examiner, Art Unit 2622
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