DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, & 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuribara et al. (US PGPub 20170026024)
As per claim 1:
Kuribara discloses in Fig. 1:
A multilayer electronic component comprising:
a stack including a plurality of dielectric layers (insulating layers 1a-1p) stacked together;
a first inductor (L1) including a first conductor layer (line electrode 8u) extending along a plane crossing a stacking direction of the plurality of dielectric layers, a first columnar conductor (via electrode 6be) extending in a direction parallel to the stacking direction and connected to a portion near a first end of the first conductor layer, and a second columnar conductor (via electrode 6bh) extending in a direction parallel to the stacking direction and connected to a portion near a second end of the first conductor layer being different from the first end; and
a second inductor (L2) including a second conductor layer (line electrode 8v) extending along a plane crossing the stacking direction, a third columnar conductor (via electrode 6bg) extending in a direction parallel to the stacking direction and connected to a portion near a first end of the second conductor layer, and a fourth columnar conductor (via electrode 6bf) extending in a direction parallel to the stacking direction and connected to a portion near a second end of the second conductor layer being different from the first end, wherein
the stack includes a first surface (bottom) and a second surface (top) located at both ends of the stack in the stacking direction, and a first side surface, a second side surface, a third side surface, and a fourth side surface connecting the first surface and the second surface to each other (insulating layers are presented as having a rectangular shape, thus having four side surfaces between the first and second surfaces),
the first side surface and the second side surface are opposite to each other (as seen in Fig. 1, wherein the first side surface is either a long side closest to 8u, or a short side closest to 6be),
the third side surface and the fourth side surface are opposite to each other (as seen in Fig. 1 wherein the third side surface is either a short side closest to 6be, or a long side closest to 8u),
the first inductor is arranged at a position closer to the first side surface than the second side surface (as seen in Fig. 1),
the second inductor is arranged at a position closer to the second side surface than the first side surface (as seen in Fig. 1),
at least part of the first conductor layer extends in a direction crossing an alignment direction of the first columnar conductor and the second columnar conductor at an angle other than an odd number multiple of 90 degrees (8u forms a zig-zag shape aligned with the directions of the side surfaces to traverse the distance of the alignment direction between 6be and 6bh, which is diagonal to the side surfaces), and
at least part of the second conductor layer extends in a direction crossing an alignment direction of the third columnar conductor and the fourth columnar conductor at an angle other than an odd number multiple of 90 degrees (8v forms a zig-zag shape aligned with the directions of the side surfaces to traverse the distance of the alignment direction between 6bg and 6bf, which is diagonal to the side surfaces).
As per claim 2:
Kuribara discloses in Fig. 1:
the first inductor is arranged at a position closer to the third side surface than the fourth side surface, and the second inductor is arranged at a position closer to the fourth side surface than the third side surface (as seen in Fig. 1).
As per claim 4:
Kuribara discloses in Fig. 1:
each of the first conductor layer and the second conductor layer includes a straight portion extending in a straight line, and the straight portion of the first conductor layer and the straight portion of the second conductor layer are parallel to each other (each conductor layer has a length parallel to a pair of sides of the dielectric layer, as seen in Fig.1).
As per claim 8:
Kuribara discloses in Fig. 1:
when a direction which is orthogonal to the stacking direction and in which the first side surface and the second side surface are aligned is referred to as a first direction (direction of the long sides of the dielectric layer), and a direction which is orthogonal to the stacking direction and in which the third side surface and the fourth side surface are aligned is referred to as a second direction (direction of the short sides of the dielectric layer), the second columnar conductor and the fourth columnar conductor are arranged between the first columnar conductor and the third columnar conductor in the second direction (as seen in Fig. 1), and a distance between the second columnar conductor and the fourth columnar conductor in the first direction is smaller than a distance between the first columnar conductor and the third columnar conductor in the first direction (as seen in Fig. 1).
Claim(s) 1 & 3-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yosui et al. (US PGPub 20150310994)
As per claim 1:
Yosui discloses in Figs. 5-6:
A multilayer electronic component comprising:
a stack including a plurality of dielectric layers (insulating layers 71-79) stacked together;
a first inductor (pattern coil 53A) including a first conductor layer (coil conductor 81A) extending along a plane crossing a stacking direction of the plurality of dielectric layers, a first columnar conductor (connected conductor 81C) extending in a direction parallel to the stacking direction and connected to a portion near a first end of the first conductor layer, and a second columnar conductor (via conductor 91) extending in a direction parallel to the stacking direction and connected to a portion near a second end of the first conductor layer being different from the first end; and
a second inductor (pattern coil 53B) including a second conductor layer (coil conductor 81B) extending along a plane crossing the stacking direction, a third columnar conductor (connected conductor 81D) extending in a direction parallel to the stacking direction and connected to a portion near a first end of the second conductor layer, and a fourth columnar conductor (unlabeled, but in the 81B equivalent position of 91) extending in a direction parallel to the stacking direction and connected to a portion near a second end of the second conductor layer being different from the first end, wherein
the stack includes a first surface (bottom) and a second surface (top) located at both ends of the stack in the stacking direction, and a first side surface, a second side surface, a third side surface, and a fourth side surface connecting the first surface and the second surface to each other (insulating layers are presented as having a rectangular shape, thus having four side surfaces between the first and second surfaces),
the first side surface and the second side surface are opposite to each other (as seen in Fig. 6, wherein the first side surface is short side closest to 81A),
the third side surface and the fourth side surface are opposite to each other (as seen in Fig. 6 wherein the third side surface is a long side closest to 91),
the first inductor is arranged at a position closer to the first side surface than the second side surface (as seen in Fig. 6),
the second inductor is arranged at a position closer to the second side surface than the first side surface (as seen in Fig. 6),
at least part of the first conductor layer extends in a direction crossing an alignment direction of the first columnar conductor and the second columnar conductor at an angle other than an odd number multiple of 90 degrees (columnar conductors of each coil are offset from the horizontal and vertical, such that lines following the horizontal and vertical intersect at non-odd multiples of 90 degrees), and
at least part of the second conductor layer extends in a direction crossing an alignment direction of the third columnar conductor and the fourth columnar conductor at an angle other than an odd number multiple of 90 degrees (columnar conductors of each coil are offset from the horizontal and vertical, such that lines following the horizontal and vertical intersect at non-odd multiples of 90 degrees).
As per claim 3:
Yosui discloses in Figs. 5-6:
the first conductor layer includes a first portion (solid box around portion of 81A in annotated Fig. 6 portion below) extending to approach the second side surface while going away from the first end of the first conductor layer, and a second portion (dashed box around portion of 81A in annotated Fig. 6 portion below) extending to approach the second side surface while going away from the second end of the first conductor layer, and the second conductor layer includes a third portion (solid box around portion of 81B in annotated Fig. 6 portion below) extending to approach the first side surface while going away from the first end of the second conductor layer, and a fourth portion (dashed box around portion of 81B in annotated Fig. 6 portion below) extending to approach the first side surface while going away from the second end of the second conductor layer.
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Annotated Fig. 6 Portion
As per claim 4:
Kuribara discloses in Fig. 1:
each of the first conductor layer and the second conductor layer includes a straight portion extending in a straight line, and the straight portion of the first conductor layer and the straight portion of the second conductor layer are parallel to each other (each conductor layer has lengths parallel to an adjacent side of the dielectric layer, such that lengths along the long side of the dielectric of each conductor are parallel to each other, as seen in Fig.6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6, 11, & 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuribara et al. (US PGPub 20170026024)
As per claim 5:
Kuribara discloses in Fig. 1:
the first conductor layer includes a first portion extending in one direction, and a second portion extending in a direction different from the one direction of the first portion, and the second conductor layer includes a third portion extending in one direction, and a fourth portion extending in a direction different from the one direction of the third portion (each of conductors 8u and 8v are shown to consist of portions extending along the length and width dimension of the dielectric layer, as seen in Fig. 1).
Kuribara is silent regarding:
the first conductor layer includes a first portion extending in one direction, and a second portion extending in a direction different from the one direction of the first portion and having a length different from a length of the first portion, and the second conductor layer includes a third portion extending in one direction, and a fourth portion extending in a direction different from the one direction of the third portion and having a length different from a length of the third portion.
At the time of filing, it would have been obvious to one of ordinary skill in the art for the first and second inductors to have the same dimensions, as the inductors have the same inductance ([0099]), and for the inductors to have symmetrically square coils, as a design parameter for determining the inductance, resistance, and size of the coils, as is well understood in the art.
It would be further obvious for the first portion and the second portion as well as the third portion and the fourth portion to have different lengths, as the shape and path of the conductors is based on the shape of the respective inductors L1 and L2, wherein the conductors must pass from the outer edge of the respective inductor, to the center of the other inductor ([0012]), such that the conductor must traverse the full length of the corresponding inductor and half the length of the other inductor, compared to half or less of the width of the corresponding inductor, and the specific path each conductor is a design parameter that can be selected to provide connectivity between the columnar conductors.
As per claim 6:
Kuribara is silent regarding:
a distance from the second portion to the fourth portion is shorter than a distance from the first portion to the third portion.
As a consequence of the combination of claim 5, a distance from the second portion to the fourth portion is shorter than a distance from the first portion to the third portion (the first and third portions may be the length portions connected closest to respective vias 6bg and 6be, while second and fourth portions may be width portions closer to respective vias 6bh and 6bf).
As per claim 11:
Kuribara discloses in Fig. 1:
A multilayer electronic component comprising:
a stack including a plurality of dielectric layers (insulating layers 1a-1p) stacked together; and
an inductor (L1) including a conductor layer (line electrode 8u) extending along a plane crossing a stacking direction of the plurality of dielectric layers, a first columnar conductor (via electrode 6be) extending in a direction parallel to the stacking direction and connected to a portion near a first end of the conductor layer, and a second columnar conductor (via electrode 6bh) extending in a direction parallel to the stacking direction and connected to a portion near a second end of the conductor layer being different from the first end, wherein
the conductor layer includes a first portion (length-extending portion closest to via 6be) and a second portion extending (width extending) in a direction crossing an alignment direction of the first columnar conductor and the second columnar conductor, extending in different directions.
Kuribara is silent regarding:
the conductor layer includes a first portion and a second portion extending in a direction crossing an alignment direction of the first columnar conductor and the second columnar conductor, extending in different directions, and having different lengths.
At the time of filing, it would have been obvious to one of ordinary skill in the art for the first and second inductors of Kuribara to have the same dimensions, as the inductors have the same inductance ([0099]), and for the inductors to have symmetrically square coils, as a design parameter for determining the inductance, resistance, and size of the coils, as is well understood in the art.
As a consequence of the combination, the conductor layer includes a first portion and a second portion extending in a direction crossing an alignment direction of the first columnar conductor and the second columnar conductor, extending in different directions, and having different lengths (the first portion traverses the full length of the corresponding inductor, and the second portion traverses half the width of the respective inductor, wherein the width and the length dimensions of the inductors is the same).
As per claim 14:
Kuribara discloses in Fig. 1:
the stack includes a first surface (bottom) and a second surface (top) located at both ends of the stack in the stacking direction, and a first side surface, a second side surface, a third side surface, and a fourth side surface connecting the first surface and the second surface to each other (insulating layers are presented as having a rectangular shape, thus having four side surfaces between the first and second surfaces),
the first side surface and the second side surface are opposite to each other (as seen in Fig. 1, wherein the first side surface is either a long side closest to 8u, or a short side closest to 6be),
the third side surface and the fourth side surface are opposite to each other (as seen in Fig. 1 wherein the third side surface is either a short side closest to 6be, or a long side closest to 8u), and
a distance between the second columnar conductor and the first side surface is larger than a distance between the first columnar conductor and the first side surface (seen in Fig. 1, wherein the first side surface is the shortest surface that is closest to via 6be).
Claim(s) 5-6, 11, & 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuribara et al. (US PGPub 20170026024)
As per claim 5:
Yosui et al. discloses in Figs. 5-6:
the first conductor layer includes a first portion (dashed box around portion of 81A in annotated Fig. 6 portion below) extending in one direction, and a second portion (solid box around portion of 81A in annotated Fig. 6 portion below) extending in a direction different from the one direction of the first portion, and the second conductor layer includes a third portion (dashed box around portion of 81B in annotated Fig. 6 portion below) extending in one direction, and a fourth portion (solid box around portion of 81B in annotated Fig. 6 portion below) extending in a direction different from the one direction of the third portion (each of conductors 8u and 8v are shown to consist of portions extending along the length and width dimension of the dielectric layer, as seen in Fig. 1).
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Annotated Fig. 6 portion (2)
Yosui is silent regarding:
the first conductor layer includes a first portion extending in one direction, and a second portion extending in a direction different from the one direction of the first portion and having a length different from a length of the first portion, and the second conductor layer includes a third portion extending in one direction, and a fourth portion extending in a direction different from the one direction of the third portion and having a length different from a length of the third portion.
At the time of filing, it would have been obvious to one of ordinary skill in the art for the first and second inductors to have the same dimensions as a design parameter based on the desired inductance of the coils, and for the inductors to have symmetrically square coils, as a design parameter for determining the inductance, resistance, and size of the coils, as is well understood in the art.
As a consequence of the combination, the respective lengths of the first & second portion and the third & fourth portion are different, as the second and third portion traverse only a partial length of square coil.
As per claim 6:
Yosui is silent regarding:
a distance from the second portion to the fourth portion is shorter than a distance from the first portion to the third portion.
As a consequence of the combination of claim 5, a distance from the second portion to the fourth portion is shorter than a distance from the first portion to the third portion (the second and fourth portions are only separated by the space between the inductors, the first and third are separated by the same space and an additional length).
As per claim 11:
Yosui et al. discloses in Figs. 5-6:
A multilayer electronic component comprising:
a stack including a plurality of dielectric layers (insulating layers 71-79) stacked together; and
an inductor (pattern coil 53A) including a conductor layer (coil conductor 81A) extending along a plane crossing a stacking direction of the plurality of dielectric layers, a first columnar conductor (connected conductor 81C) extending in a direction parallel to the stacking direction and connected to a portion near a first end of the conductor layer, and a second columnar conductor (via conductor 91) extending in a direction parallel to the stacking direction and connected to a portion near a second end of the conductor layer being different from the first end, wherein the conductor layer includes a first portion (From 81C to the upper right of the coil conductor 81A) and a second portion (lower right side of coil conductor 81A) extending in a direction crossing an alignment direction of the first columnar conductor and the second columnar conductor (the alignment direction between 81C and 91 is angled from the vertical, as seen in Fig. 6), extending in different directions, and having different lengths.
Yosui is silent regarding:
the conductor layer includes a first portion and a second portion extending in a direction crossing an alignment direction of the first columnar conductor and the second columnar conductor, extending in different directions, and having different lengths.
At the time of filing, it would have been obvious to one of ordinary skill in the art for the first and second inductors of Yosui to have the same dimensions, as a design parameter based on the desired inductance of the coils, and for the inductors to have symmetrically square coils, as a design parameter for determining the inductance, resistance, and size of the coils, as is well understood in the art.
As a consequence of the combination, the conductor layer includes a first portion and a second portion extending in a direction crossing an alignment direction of the first columnar conductor and the second columnar conductor, extending in different directions, and having different lengths (first portion includes two sides of the coil and two lengths that are partial length of the sides of the coil, and extending a full length of the coil vertically, with the second portion extending a partial side of the coil in the horizontal direction).
As per claim 13:
Yosui et al. discloses in Figs. 5-6:
the stack includes a first surface (bottom) and a second surface (top) located at both ends of the stack in the stacking direction, and a first side surface, a second side surface, a third side surface, and a fourth side surface connecting the first surface and the second surface to each other (insulating layers are presented as having a rectangular shape, thus having four side surfaces between the first and second surfaces),
the first side surface and the second side surface are opposite to each other (as seen in Fig. 6, wherein the first side surface is short side closest to 81A),
the third side surface and the fourth side surface are opposite to each other (as seen in Fig. 6 wherein the third side surface is a long side closest to 91),
the inductor is arranged at a position closer to the first side surface than the second side surface (as seen in Fig. 6),
the first portion includes the first end of the conductor layer and extends to approach the second side surface while going away from the first end (as seen at the upper right corner of coil 81C in Fig. 6), and the second portion includes the second end of the conductor layer and extends to approach the second side surface while going away from the second end (as seen in Fig. 6).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuribara et al. (US PGPub 20170026024) in view of Ishiwata et al. (US PGPub 20070103256)
As per claim 7:
Kuribara et al. does not disclose:
each of the first conductor layer and the second conductor layer includes a curved portion extending in a curve.
Ishiwata discloses in Figs. 1-2:
The formation of inductors (L1/L2) wherein conductor layers (conductve patterns 11-16) include a curved portion extending in a curve (as seen in Fig. 2).
At the time of filing, it would have been obvious to one of ordinary skill in the art
To form the conductor layers of Kuribara et al. with curved portions extending in a curve as opposed to sharp corners as a known in the art method of forming inductors from conductor layers as shown by Ishiwata (Fig. 2)
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yosui et al. (US PGPub 20150310994) in view of Ishiwata et al. (US PGPub 20070103256)
As per claim 7:
Yosui et al. does not disclose:
each of the first conductor layer and the second conductor layer includes a curved portion extending in a curve.
Ishiwata discloses in Figs. 1-2:
The formation of inductors (L1/L2) wherein conductor layers (conductve patterns 11-16) include a curved portion extending in a curve (as seen in Fig. 2).
At the time of filing, it would have been obvious to one of ordinary skill in the art
To form the conductor layers of Yosui et al. with curved portions extending in a curve as opposed to sharp corners as a known in the art method of forming inductors from conductor layers as shown by Ishiwata (Fig. 2)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the resultant combination of Kuribara et al. (US PGPub 20170026024) as applied to claim 11 above, and further in view of Ishiwata (US PGPub 20070103256).
The resultant combination discloses multilayer electronic component of claim 11, as rejected above.
As per claim 12:
The resultant combination does not disclose:
each of the first conductor layer and the second conductor layer includes a curved portion extending in a curve.
Ishiwata discloses in Figs. 1-2:
The formation of inductors (L1/L2) wherein conductor layers (conductve patterns 11-16) include a curved portion extending in a curve (as seen in Fig. 2).
At the time of filing, it would have been obvious to one of ordinary skill in the art
To form the conductor layers of The resultant combination with curved portions extending in a curve as opposed to sharp corners as a known in the art method of forming inductors from conductor layers as shown by Ishiwata (Fig. 2)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the resultant combination of Yosui et al. (US PGPub 20150310994) as applied to claim 11 above, and further in view of Ishiwata (US PGPub 20070103256).
The resultant combination discloses multilayer electronic component of claim 11, as rejected above.
As per claim 12:
The resultant combination does not disclose:
each of the first conductor layer and the second conductor layer includes a curved portion extending in a curve.
Ishiwata discloses in Figs. 1-2:
The formation of inductors (L1/L2) wherein conductor layers (conductve patterns 11-16) include a curved portion extending in a curve (as seen in Fig. 2).
At the time of filing, it would have been obvious to one of ordinary skill in the art
To form the conductor layers of The resultant combination with curved portions extending in a curve as opposed to sharp corners as a known in the art method of forming inductors from conductor layers as shown by Ishiwata (Fig. 2)
Allowable Subject Matter
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the limitations of claim 9 in combination with the limitations of claim 1 overcome the closest prior art of Yosui et al. and Kuribara et al. by specifically requiring the inductors to be inductors of separate respective high pass filters that are connected with a low pass filter there between, which is not disclosed or rendered obvious over Yosui et al. or Kuribara et al.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL S OUTTEN whose telephone number is (571)270-7123. The examiner can normally be reached M-F: 9:30AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at (571) 272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Samuel S Outten/ Primary Examiner, Art Unit 2843