DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-2, 4-7, 10, 12, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oprescu et al. (USP 6,411,242).
Regarding claim 1, Oprescu discloses an ADC architecture in figure 2 that teaches: an analog chopper (34) configured to shift an analog input (32) from an original frequency to a chopping frequency to generate a chopped analog signal (14) and a sigma delta modulator (16) coupled to an output of the analog chopper (34) to configured to digitize the chopped analog signal (14) at sampling frequency to generate a chopped digital signal and a digital chopper (18) coupled to output of a sigma delta modulator (16) and configured to demodulate the chopped digital signal to generate a demodulated chopped digital signal having a signal component at the original frequency (see figure 2 and it descriptions).
Regarding claim 12, Oprescu further teaches in figure 5, a digital filter (54) coupled to an output of the digital chopper ((18) and reject at least the chopping frequency (40) (see figure 5 and its descriptions).
Regarding claim 18, Oprescu further teaches in figures 2 and 5 an buffer/amplifier (14) between the analog chopper (34) and sigma delta (16) and configured to amplify the chopped analog signal (see figures 2 and 5 and their descriptions).
Regarding claim 19, Oprescu further teaches in figures 2 and 5 wherein the digital chopper circuit (18) is configured to multiply the chopped digital signal with a digital sinusoidal signal having the chopping frequency (40) (see figures 2 and 5 and their descriptions)
Claim 1-2, , 4-7, 10, 12, 16, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oprescu (USP 6,927,717).
Regarding claim 1, Oprescu discloses an ADC architecture in figure 2 that teaches: an analog chopper (34) configured to shift an analog input (32) from an original frequency to a chopping frequency to generate a chopped analog signal (14) and a sigma delta modulator (16) coupled to an output of the analog chopper (34) to configured to digitize the chopped analog signal (14) at sampling frequency to generate a chopped digital signal and a digital chopper (18) coupled to output of a sigma delta modulator (16) and configured to demodulate the chopped digital signal to generate a demodulated chopped digital signal having a signal component at the original frequency (see figure 2 and it descriptions).
Regarding claim 12, Oprescu further teaches in figure 5, a digital filter (54) coupled to an output of the digital chopper ((18) and reject at least the chopping frequency (40) (see figure 5 and its descriptions).
Regarding claim 18, Oprescu further teaches in figures 2 and 5 an buffer/amplifier (14) between the analog chopper (34) and sigma delta (16) and configured to amplify the chopped analog signal (see figures 2 and 5 and their descriptions).
Regarding claim 19, Oprescu further teaches in figures 2 and 5 wherein the digital chopper circuit (18) is configured to multiply the chopped digital signal with a digital sinusoidal signal having the chopping frequency (40) (see figures 2 and 5 and their descriptions)
Claim 1 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Motz et al. (US 2016/0252599).
Regarding claim 1, Motz discloses an architecture in figure 2 that teaches: an analog chopper (26) configured to shift an analog input from an original frequency to a chopping frequency to generate a chopped analog signal (26) and a sigma delta modulator (27) coupled to an output of the analog chopper to configured to digitize the chopped analog signal at sampling frequency to generate a chopped digital signal and a digital chopper (29) coupled to output of a sigma delta modulator and configured to demodulate the chopped digital signal to generate a demodulated chopped digital signal having a signal component at the original frequency (see figure 2 and it descriptions).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Oprescu as applied to claim 1 above, and further in view of Sharma (USP 9413,383).
Regarding claim 2, Oprescu fails to teach or suggest wherein the sigma delta is configured without a chopper circuit.
While, Sharma discloses a sigma delta architecture wherein the sigma delta is configured without a chopper operation in figure 6 (see col. 7, lines 46-50).
Therefore, it would have been obvious to one ordinary skill in the art at the time of effective filing date of the invention to implement an option wherein the sigma delta is configured without a chopper operation to obtain relatively high DC or low frequency offset of about -19 dB.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oprescu as applied to claim 1 above, and further in view of NA et al. (US 2019/0199367)
Regarding claim 4, Oprescu fails to clearly teach wherein the EA-modulator comprises an ADC and an analog loop filter coupled between the output of the analog chopper circuit and the ADC.
While, NA et al. discloses an architecture that teaches a sigma delta (10) in figure 1 wherein the sigma delta modulator comprises an ADC (120) and an analog loop filter (100) coupled between the output of the analog chopper circuit (34 in figure 2 of Oprescu) and the ADC (120).
Therefore, it would have been obvious to one ordinary skill in the art at the time of effective filing date of the invention to implement NA’s sigma delta architecture in Oprescu’s disclosure to satisfy the need of the invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oprescu as applied to claim 1 above, and further in view of Di Giandomenico et al (USP 7,486,214).
Regarding claim 4, Oprescu fails to clearly teach wherein the EA-modulator comprises an ADC and an analog loop filter coupled between the output of the analog chopper circuit and the ADC.
While, Di Giandomenico et al. discloses an architecture that teaches a sigma delta (150) in figure 2 wherein the sigma delta modulator comprises an ADC (164) and an analog loop filter (152) coupled between the output of the analog chopper circuit (34 in figure 2 of Oprescu) and the ADC (164).
Therefore, it would have been obvious to one ordinary skill in the art at the time of effective filing date of the invention to implement Di Giandomenico’s sigma delta architecture in Oprescu’s disclosure to satisfy the need of the invention.
Regarding claim 5, Di Giandomenico teaches wherein the analog loop filter (152) is implemented as continuous time loop filter.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oprescu as applied to claim 1 above, and further in view of Lien et al. (US 2019/0149164).
Regarding claim 4, Oprescu fails to clearly teach wherein the EA-modulator comprises an ADC and an analog loop filter coupled between the output of the analog chopper circuit (34 in figure 2 of Oprescu) and the ADC.
While, Lien et al. discloses an architecture that teaches a sigma delta (600) in figure 6 wherein the sigma delta modulator comprises an ADC (630) and an analog loop filter (635, from loop filter) coupled between the output of the analog chopper circuit (34 in figure 2 of Oprescu) and the ADC (630).
Therefore, it would have been obvious to one ordinary skill in the art at the time of effective filing date of the invention to implement Lien’s sigma delta architecture in Oprescu’s disclosure to satisfy the need of the invention.
Regarding claim 5, Lien teaches wherein the analog loop filter (635)) is implemented as continuous time loop filter (figure 6 is a continuous time delta sigma (see abstract and title), therefore, the loop filter is obviously a continuous time loop filter.
Regarding claim 6, Lien further teaches sigma delta architecture in figure 6 comprising multi-bit (2-bit) ADC configured to convert the chopper analog signal (34 in figure 2 of Oprescu) from analog to digital to generate the chopped digital signal (output from sigma delta modulator).
Regarding claim 7, Lien further teaches wherein multi-bit ADC has a bit equal to or larger that two bits (ADC 630 is 2 bit ADC (see para. 0057).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oprescu as applied to claim 1 above, and further in view of Zhang et al. (US 2021/0126648).
Regarding claim 4, Oprescu fails to clearly teach wherein the EA-modulator comprises an ADC and an analog loop filter coupled between the output of the analog chopper circuit (34 in figure 2 of Oprescu) and the ADC.
While, Zhang et al. discloses an architecture that teaches a sigma delta (800) in figure 8 wherein the sigma delta modulator comprises an ADC (1-bit ADC) and an analog loop filter (306) coupled between the output of the analog chopper circuit (34 in figure 2 of Oprescu) and the ADC.
Therefore, it would have been obvious to one ordinary skill in the art at the time of effective filing date of the invention to implement Zhang’s sigma delta architecture in Oprescu’s disclosure to satisfy the need of the invention.
Regarding claim 5, Zhang teaches wherein the analog loop filter (306) is implemented as continuous time loop filter (figure 8 is a continuous time delta sigma (see abstract), therefore, the loop filter is obviously a continuous time loop filter.
Regarding claim 10, Lien further teaches sigma delta architecture in figure 8 comprising a single-bit ADC configured to convert the chopper analog signal (34 in figure 2 of Oprescu) from analog to digital to generate the chopped digital signal (output from sigma delta modulator).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “wherein a ratio between the sampling frequency of the EA-modulator and the chopping frequency is larger than 100”.
Claim 8 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “wherein the sigma delta modulator comprises a feedback path that extends from an-the output of the sigma delta modulator to the of the sigma delta modulator, the feedback path comprising a second multi-bit DAC configured to convert the chopped digital signal back to analog”.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “wherein the second multi-bit DAC has a bit width equal to or larger than two bits”.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “wherein the sigma delta modulator comprises a feedback path that extends from an the output of the sigma delta modulator to the an input of the sigma delta modulator, the feedback path comprising a single-bit digital analog converter DAC configured to convert the chopped digital signa back to analog.
Claim 13 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “wherein the digital filter comprises a notch filter having a notch at least at the chopping frequency”.
Claim 14 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “wherein the digital filter comprises a lowpass filter configured to allow the signal component at the original frequency to pass through while attenuating signal components at the chopping frequency or higher”.
Claim 15 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “wherein the digital filter comprises a combination of a lowpass filter and a notch filter”.
Claim 16 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “a digital filter coupled between the sigma delta modulator and the digital chopper circuit and configured to reject harmonics of the chopping frequency.
Claim 17 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closet prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is “wherein the digital filter is configured to cause a filter delay and wherein the sensor circuit further comprises a delay element coupled between a chopping clock signal and the digital chopper circuit and wherein the delay element is configured to cause a delay of the chopping clock signal corresponding to the filter delay.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845