DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This communication is in response to the Application Filed on 08/02/2024
Claims 1–20 are pending in this application.
Drawings
The drawing(s) filed on 08/02/2024 are accepted by the Examiner.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/02/2024 and 05/20/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 02/04/2022. It is noted, however, that applicant has not filed a certified copy of the KR10-2022-0015079 application as required by 37 CFR 1.55. Note: according to the priority retrieval document on 10/04/2024 the priority document failed to be retrieved.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, the phrase " a number of the at least one MAC calculator, …, is less than a number of the plurality of output channels" renders the claim indefinite because it is unclear if this is based on the number output by the MAC channel being less than the number of output channels or if the number of MAC calculators needs to be less than the number of output channels. For the purpose of examination the examiner is interpreting it as the number of MAC calculators needs to be less than the number of output channels.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1, 2, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Brothers et al. (US 20220092409 A1, hereafter, "Brothers") in view of Robatmili et al. (US 20170083827 A1, hereafter, "Robatmili").
Regarding claim 1, Brothers teaches A data processing method for generating and displaying upscaled image data (See Brothers, ¶ [0114] A deconvolution operation generally comprises upsampling an input data array (so as to increase the number of data positions in either or both of the x and y directions), and then applying a filter to the upsampled input data array in order to generate an output data array. ¶ [0174], The data processing system may comprise and/or be in communication with a host microprocessor, and/or with a display for displaying output data associated with the neural network processing. Note: upsampling is increasing the amount of pixels which is the same as upscaling), the data processing method comprising:
obtaining image data comprising at least one input value (See Brothers, ¶ [0068], The input feature map may correspond to (or be derived from) any suitable data which is received by the data processing system for processing according to neural network processing in order to generate a useful output such as, for example, an image, an image from an Image Signal Processor (ISP), an image frame from video data, sound data or voice data, or other input data);
obtaining, in order to perform a convolution operation for a plurality of output channels corresponding to a neural network, at least one weight corresponding to the at least one input value for at least one output channel among the plurality of output channels (See Brothers, ¶ [0293], Each channel of the input data array may itself comprise an input data array having an x and y extent. In the case where the input data array comprises plural channels, the filter may also comprise plural channels (and correspondingly be three-dimensional, having a z extent corresponding to a number of channels of the filter), wherein each channel of the filter itself comprises a weight data array having an x and y extent, ..., In such cases, when performing neural network processing, in embodiments of the technology described herein, each channel of the input data array and/or filter array is subdivided into plural portions, and neural network processing is performed for each channel using the appropriate portions);
[determining at least one operation group corresponding to at least one multiply-accumulate (MAC) calculator, the at least one operation group and the at least one MAC calculator comprising a first MAC calculator that performs a first operation group, the first operation group comprising a first MAC operation for a first output channel, and a second MAC operation for a second output channel which does not overlap with the first MAC operation at a first operation time];
generating a plurality of output values corresponding to the plurality of output channels by performing MAC operations in the at least one MAC calculator by using the at least one input value and the at least one weight according to the at least one operation group (See Brothers, ¶ [0051],I n an embodiment, the processor is configured to perform a weighted sum as a multiply-accumulate operation, and accordingly the processor comprises one or more multiply-accumulate circuits (otherwise known as a multiplier-accumulator, or an “MAC unit”) for performing a multiply-accumulate operation);
generating upscaled image data based on the plurality of output values (See Brothers, ¶ [0276], As shown in FIGS. 11A and 11B, a transposed convolution may be desired to be performed by upsampling an input data array (input feature map) 1101 comprising a set of data positions 1102, to form an upsampled input data array 1103 (see FIG. 11A), and then applying a filter 1105 to the upsampled input data array 1103 to generate an output data array 1108 (see FIG. 11B)); and
displaying the upscaled image data on a display having a higher resolution than the image data (See Brothers, ¶ [0174], The data processing system may comprise and/or be in communication with a host microprocessor, and/or with a display for displaying output data associated with the neural network processing. Note: upsampling is increasing the amount of pixels which is the same as upscaling).
However, Brothers fail(s) to teach determining at least one operation group corresponding to at least one multiply-accumulate (MAC) calculator, the at least one operation group and the at least one MAC calculator comprising a first MAC calculator that performs a first operation group, the first operation group comprising a first MAC operation for a first output channel, and a second MAC operation for a second output channel which does not overlap with the first MAC operation at a first operation time.
Robatmili, working in the same field of endeavor, teaches: determining at least one operation group corresponding to at least one multiply-accumulate (MAC) calculator, the at least one operation group and the at least one MAC calculator comprising a first MAC calculator that performs a first operation group (See Robatmili, ¶ [0137], Each filter 1808 may correspond to a particular filter location 1804 in the filter queue 1702 of the corresponding multiply-accumulate unit), the first operation group comprising a first MAC operation for a first output channel (See Robatmili, ¶ [0140], FIG. 18D illustrates an example of a partial output 1810 of one of the multiply-accumulate units 1808 (e.g., 1808a) after executing the operation for the feature vector 1802 and the kernels (or weight factors) of the corresponding filters 1806 for all of the available channels of data. Note: Examiner is interpreting the partial output as the first output channel), and a second MAC operation for a second output channel which does not overlap with the first MAC operation at a first operation time (See Robatmili, ¶ [0138], At the second time the operation may use data from the stippled data channel. Each multiply-accumulate unit 1808 may have its respective filter 1806 with kernel (or weight factor) values. Note: Examiner is interpreting the second MAC operations at the second time as non-overlapping with the first operation time).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference to determining at least one operation group corresponding to at least one multiply-accumulate (MAC) calculator, the at least one operation group and the at least one MAC calculator comprising a first MAC calculator that performs a first operation group, the first operation group comprising a first MAC operation for a first output channel, and a second MAC operation for a second output channel which does not overlap with the first MAC operation at a first operation time based on the method of Robatmili’s reference. The suggestion/motivation would have been to accelerate the machine learning to reduce the overhead of data translation, data movement and feature extraction (See Robatmili, ¶ [0001–0010]).
Further, one skilled in the art could have combined the elements as described above by known method with no change in their respective functions, and the combination would have yielded nothing more than predictable results.
Therefore, it would have been obvious to combine Robatmili with Brothers to obtain the invention as specified in claim 1.
Regarding claim 2, Brothers in view of Robatmili teaches the data processing method of claim 1, [wherein the first MAC calculator is configured to perform the first MAC operation at a second operation time].
However, Brothers fail(s) to teach wherein the first MAC calculator is configured to perform the first MAC operation at a second operation time.
Robatmili, working in the same field of endeavor, teaches: wherein the first MAC calculator is configured to perform the first MAC operation at a second operation time (See Robatmili, ¶ [0138], At the second time the operation may use data from the stippled data channel. Each multiply-accumulate unit 1808 may have its respective filter 1806 with kernel (or weight factor) values).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference wherein the first MAC calculator is configured to perform the first MAC operation at a second operation time based on the method of Robatmili’s reference. The suggestion/motivation would have been to accelerate the machine learning to reduce the overhead of data translation, data movement and feature extraction (See Robatmili, ¶ [0001–0010]).
Further, one skilled in the art could have combined the elements as described above by known method with no change in their respective functions, and the combination would have yielded nothing more than predictable results.
Therefore, it would have been obvious to combine Robatmili with Brothers to obtain the invention as specified in claim 2.
Regarding claim 14, claim 14 is rejected the same as claim 1 and the arguments similar to that presented above for claim 1 are equally applicable to the claim 14, and all of the other limitations similar to claim 1 are not repeated herein, but incorporated by reference. Furthermore, Brothers teaches a data processing device comprising: memory storing instructions; and at least one processor operatively connected to the memory and configured to execute the instructions to (See Brothers, [FIG. 1, CPU 105, Off-Chip Memory 109]).
Regarding claim 15, claim 15 is rejected the same as claim 1 and the arguments similar to that presented above for claim 1 are equally applicable to the claim 15, and all of the other limitations similar to claim 1 are not repeated herein, but incorporated by reference. Furthermore, Brothers teaches a computer-readable recording medium having recorded thereon a program that, when executed by at least one processor, cause the at least one processor to (See Brothers, [FIG. 1, CPU 105, Off-Chip Memory 109]).
Claim(s) 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Brothers et al. (US 20220092409 A1, hereafter, "Brothers") in view of Robatmili et al. (US 20170083827 A1, hereafter, "Robatmili") further in view of Liu et al. (US 20200342295 A1, hereafter, "Liu") and further in view of Sudhir et al. (US 20210224629 A1, hereafter, "Sudhir").
Regarding claim 3, Brothers in view of Robatmili teaches the data processing method of claim 1,
[wherein the at least one input value and the at least one weight are sequentially input to the at least one MAC calculator, and
wherein the at least one input value and the at least one weight input to the at least one MAC calculator are synchronized].
However, Brothers and Robatmili fail(s) to teach wherein the at least one input value and the at least one weight are sequentially input to the at least one MAC calculator, and wherein the at least one input value and the at least one weight input to the at least one MAC calculator are synchronized;
Liu, working in the same field of endeavor, teaches: wherein the at least one input value and the at least one weight are sequentially input to the at least one MAC calculator (See Liu, [Claim 2], The multiply-accumulate calculation circuit suitable for a neural network according to claim 1, …, the selection-shift unit performs selection and shift operations on the feature product according to a weight coefficient of the neural network to obtain a product of the input data of the neural network and the weight coefficient of the neural network, and sequentially inputs data on each bit of the obtained product into the accumulation calculation circuit).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference to wherein the at least one input value and the at least one weight are sequentially input to the at least one MAC calculator based on the method of Liu’s reference. The suggestion/motivation would have been to reduce power consumption and provide high speed processing (See Liu, ¶ [0001–0004]).
However, Brothers, Robatmili and Liu fail(s) to teach wherein the at least one input value and the at least one weight input to the at least one MAC calculator are synchronized.
Sudhir, working in the same field of endeavor, teaches: wherein the at least one input value and the at least one weight input to the at least one MAC calculator are synchronized (See Sudhir, ¶ [0090], he MAC array 1428a contains a number of MAC units and accumulators for performing convolutions in parallel. In accordance with the present example, the MAC array 1428a is configured to perform a convolution between an associated input work batch and work batch filter to generate an output work batch. Convolutions involving the multiple input work batches and work batch filters associated with the convolution layer may be performed in parallel using the multiple compute engines. Note: To parallel process the operations the input would have to arrive at the same time or be synchronized).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference to wherein the at least one input value and the at least one weight input to the at least one MAC calculator are synchronized based on the method of Sudhir’s reference. The suggestion/motivation would have been to reduce the computations of convolution layers (See Sudhir, ¶ [0001–0003]).
Further, one skilled in the art could have combined the elements as described above by known method with no change in their respective functions, and the combination would have yielded nothing more than predictable results.
Therefore, it would have been obvious to combine Liu and Sudhir with Brothers and Robatmili to obtain the invention as specified in claim 3.
Regarding claim 17, claim 17 is rejected the same as claim 3 and the arguments similar to that presented above for claim 3 are equally applicable to the claim 17, and all of the other limitations similar to claim 3 are not repeated herein, but incorporated by reference.
Claim(s) 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Brothers et al. (US 20220092409 A1, hereafter, "Brothers") in view of Robatmili et al. (US 20170083827 A1, hereafter, "Robatmili") further in view Surti et al. (US 20220129521 A1, hereafter, "Surti").
Regarding claim 4, Brothers in view of Robatmili teaches the data processing method of claim 1,
[wherein the neural network is a pruned neural network,
wherein the pruned neural network has a first weight corresponding to an unpruned neural network set to 0 when the first weight is less than or equal to a predetermined value, and
wherein a weight for the first MAC operation at the first operation time is 0].
However, Brother and Robatmili fail(s) to teach wherein the neural network is a pruned neural network, wherein the pruned neural network has a first weight corresponding to an unpruned neural network set to 0 when the first weight is less than or equal to a predetermined value, and wherein a weight for the first MAC operation at the first operation time is 0.
Surti, working in the same field of endeavor, teaches: wherein the neural network is a pruned neural network (See Surti, ¶ [0412], As shown in FIG. 36B, weight pruning may be performed after a DNN model is trained by summing the weight values within a block and setting all weights in the block to zero if the absolute magnitude of the weights is below a threshold),
wherein the pruned neural network has a first weight corresponding to an unpruned neural network set to 0 when the first weight is less than or equal to a predetermined value (See Surti, ¶ [0412], Matrix 3612 may be pruned into a block sparse matrix 3614 by using, for example, a weight threshold of 0.4 and a 4×4 block. For each 4×4 block, the weights in the block may be summed and any block having an absolute magnitude that is below the threshold may have its weights set to zero), and
wherein a weight for the first MAC operation at the first operation time is 0 (See Surti, ¶ [0412], Matrix 3612 may be pruned into a block sparse matrix 3614 by using, for example, a weight threshold of 0.4 and a 4×4 block. For each 4×4 block, the weights in the block may be summed and any block having an absolute magnitude that is below the threshold may have its weights set to zero).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference to wherein the neural network is a pruned neural network, wherein the pruned neural network has a first weight corresponding to an unpruned neural network set to 0 when the first weight is less than or equal to a predetermined value, and wherein a weight for the first MAC operation at the first operation time is 0 based on the method of Surti’s reference. The suggestion/motivation would have been to increase processing efficiency and accelerating matrix operations (See Surti, ¶ [0003–0004]).
Further, one skilled in the art could have combined the elements as described above by known method with no change in their respective functions, and the combination would have yielded nothing more than predictable results.
Therefore, it would have been obvious to combine Surti with Brothers and Robatmili to obtain the invention as specified in claim 4.
Regarding claim 18, claim 18 is rejected the same as claim 4 and the arguments similar to that presented above for claim 4 are equally applicable to the claim 18, and all of the other limitations similar to claim 4 are not repeated herein, but incorporated by reference.
Claim(s) 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Brothers et al. (US 20220092409 A1, hereafter, "Brothers") in view of Robatmili et al. (US 20170083827 A1, hereafter, "Robatmili") further in view Lyuh et al. (US 20190079801 A1, hereafter, "Lyuh").
Regarding claim 5, Brothers in view of Robatmili teaches the data processing method of claim 1, [wherein the at least one MAC calculator each comprises one multiplier, one adder, and a flip-flop for storing an operation result].
However, Brother and Robatmili fail(s) to teach wherein the at least one MAC calculator each comprises one multiplier, one adder, and a flip-flop for storing an operation result.
Lyuh, working in the same field of endeavor, teaches: wherein the at least one MAC calculator each comprises one multiplier, one adder, and a flip-flop for storing an operation result (See Lyuh, ¶ [0052], In an embodiment, the PE 1110 may perform a multiply-accumulate (MAC) calculation using the multiplier 1114, the adder 1115, and the accumulator register 1116. The multiplier 1114, the adder 1115, and the accumulator register 1116 may be implemented in hardware using at least one flip-flop).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference wherein the at least one MAC calculator each comprises one multiplier, one adder, and a flip-flop for storing an operation result based on the method of Lyuh’s reference. The suggestion/motivation would have been to decrease performance overhead by reducing memory access (See Lyuh, ¶ [0003–0007]).
Further, one skilled in the art could have combined the elements as described above by known method with no change in their respective functions, and the combination would have yielded nothing more than predictable results.
Therefore, it would have been obvious to combine Lyuh with Brothers and Robatmili to obtain the invention as specified in claim 5.
Regarding claim 19, claim 19 is rejected the same as claim 5 and the arguments similar to that presented above for claim 5 are equally applicable to the claim 19, and all of the other limitations similar to claim 5 are not repeated herein, but incorporated by reference.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Brothers et al. (US 20220092409 A1, hereafter, "Brothers") in view of Robatmili et al. (US 20170083827 A1, hereafter, "Robatmili") further in view Bainville et al. (US 20190129719 A1, hereafter, "Bainville").
Regarding claim 10, Brothers in view of Robatmili teaches the data processing method of claim 1, [wherein a number of the at least one MAC calculator corresponding to the at least one operation group is less than a number of the plurality of output channels].
However, Brother and Robatmili fail(s) to teach wherein a number of the at least one MAC calculator corresponding to the at least one operation group is less than a number of the plurality of output channels.
Bainville, working in the same field of endeavor, teaches: wherein a number of the at least one MAC calculator corresponding to the at least one operation group is less than a number of the plurality of output channels (See Bainville, [Claim 13], The matrix computation engine as recited in claim 10, a number of the plurality of multiply-accumulate circuits is less than a number of matrix elements in the output vector).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference wherein a number of the at least one MAC calculator corresponding to the at least one operation group is less than a number of the plurality of output channels based on the method of Bainville’s reference. The suggestion/motivation would have been to reduce power consumption and keep high performance (See Bainville, ¶ [0002–0003, 0012]).
Further, one skilled in the art could have combined the elements as described above by known method with no change in their respective functions, and the combination would have yielded nothing more than predictable results.
Therefore, it would have been obvious to combine Bainville with Brothers and Robatmili to obtain the invention as specified in claim 10.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Brothers et al. (US 20220092409 A1, hereafter, "Brothers") in view of Robatmili et al. (US 20170083827 A1, hereafter, "Robatmili") further in view Chen (US 20200111235 A1, hereafter, "Chen") and further in view of Ware et al. (US 20200326939 A1, hereafter, "Ware").
Regarding claim 13, Brothers in view Robatmili teaches the data processing method of claim 1,
[wherein the at least one operation group is determined for a number of input values determined based on a size of a filter, and
wherein the at least one operation group is determined for each frame or in units of a plurality of frames].
However, Brothers and Robatmili fail(s) to teach wherein the at least one operation group is determined for a number of input values determined based on a size of a filter.
Chen, working in the same field of endeavor, teaches: wherein the at least one operation group is determined for a number of input values determined based on a size of a filter (See Chen, ¶ [0070], Although the multiplier-accumulator 402 will calculate each convolution result of the filter coefficients and the input feature data in a case in which the filter size is more than 1×1, the multiplier-accumulator 402 will calculate the product of I(m) and C(m,n) in a case in which the filter size is equal to 1×1. Note: the MAC operation is based a filter of size 1x1).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference to wherein the at least one operation group is determined for a number of input values determined based on a size of a filter based on the method of Chen’s reference. The suggestion/motivation would have been to efficiently process data and decrease processing time (See Chen, ¶ [0005–0014]).
However, Brothers, Robatmili and Chen fail(s) to teach wherein the at least one operation group is determined for each frame or in units of a plurality of frames.
Ware, working in the same field of endeavor, teaches: wherein the at least one operation group is determined for each frame or in units of a plurality of frames (See Ware, ¶ [0027], FIG. 7B illustrate a schematic block diagram of a logical overview of an exemplary multiplier-accumulator execution pipeline, according to one or more aspects of the present inventions, wherein the multiplier-accumulator execution pipeline includes a plurality of multiplier-accumulator circuitry, which is illustrated in block diagram form, to process data (e.g., image data of a stage of a frame)).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to modify Brothers’s reference to wherein the at least one operation group is determined for each frame or in units of a plurality of frames based on the method of Ware’s reference. The suggestion/motivation would have been to decrease processing time and increase data throughput (See Ware, ¶ [0002–0010]).
Further, one skilled in the art could have combined the elements as described above by known method with no change in their respective functions, and the combination would have yielded nothing more than predictable results.
Therefore, it would have been obvious to combine Chen and Ware with Brothers and Robatmili to obtain the invention as specified in claim 13.
Allowable Subject Matter
Claim(s) 6–9, 11, 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim(s) 6–9, 11, 12 and 20 contain subject matter that is not disclosed or made obvious in the cited art.
In regard to claim 6, when considering claim 6 as a whole, prior art of record fails to disclose or render obvious, alone or in combination:
“The data processing method of claim 2,
wherein after the first MAC calculator performs the second MAC operation at the first operation time, an accumulation value of the second MAC operation is stored in an external storage, and the accumulation value stored in the external storage is set as an initial value of the second MAC operation at the second operation time, and
wherein the first operation time and the second operation time are not consecutive but are separate from each other”.
In regard to claim 7, when considering claim 7 as a whole, prior art of record fails to disclose or render obvious, alone or in combination:
“The data processing method of claim 2, wherein after the first MAC calculator performs the first MAC operation at the second operation time, an accumulation value of the first MAC operation is stored in an external storage, and the accumulation value stored in the external storage is set as an initial value of the first MAC operation to be performed by a second MAC calculator at the second operation time”.
In regard to claim 11, when considering claim 11 as a whole, prior art of record fails to disclose or render obvious, alone or in combination:
“The data processing method of claim 1, wherein the determining of the at least one operation group comprises determining the at least one operation group by moving some of the MAC operations for the at least one output channel from the first operation group to a second operation group according to a priority of the at least one output channel, such that the MAC operations for the at least one output channel are in a same operation group”.
In regard to claim 12, when considering claim 12 as a whole, prior art of record fails to disclose or render obvious, alone or in combination:
“The data processing method of claim 1, wherein the determining of the at least one operation group comprises determining the at least one operation group by moving some of the MAC operations for the at least one output channel from the first operation group to a second operation group according to a priority of the at least one output channel and an other output channel other than the at least one output channel, such that there is no MAC operation for the other output channel between the MAC operations for the at least one output channel”.
In regard to claim 20, when considering claim 20 as a whole, prior art of record fails to disclose or render obvious, alone or in combination:
“The computer-readable medium of claim 15, wherein after the first MAC calculator performs the second MAC operation at the first operation time, an accumulation value of the second MAC operation is stored in an external storage, and the accumulation value stored in the external storage is set as an initial value of the second MAC operation at the second operation time, and wherein the first operation time and the second operation time are not consecutive but are separate from each other”.
In regard to claim 8–9, claim 8–9 depend on objected claim 7. Therefore, by virtue of their dependency, claim 8-9 is also indicated as objected subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Snelgrove et al. (US 20210271631 A1) teaches a computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.
Cho et al. (US 20210248475 A1) teaches perform convolution calculation based on the calculation information using a convolution calculation module to obtain an intermediate value in the convolution calculation process, obtain a memory address value corresponding to the obtained intermediate value of the plurality of obtained memory addresses using the address generation module, store the obtained intermediate value in the memory address value corresponding to the intermediate value, accumulate at least one intermediate value based on the memory address value corresponding to the intermediate value using a cumulative calculation module, and obtain a deconvolution calculation value with respect to the input data based on the accumulated at least one intermediate value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION J SATCHER whose telephone number is (703)756-5849. The examiner can normally be reached Monday - Thursday 5:30 am - 2:30 pm, Friday 5:30 am - 9:30 am PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henok Shiferaw can be reached at (571) 272-4637. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DION J SATCHER/Patent Examiner, Art Unit 2676
/SUMATI LEFKOWITZ/Supervisory Patent Examiner, Art Unit 2672
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