DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 ,3-8, 10, 11 and 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,4.7-11 and 14 of U.S. Patent No. 1,126,251. Although the claims at issue are not identical, they are not patentably distinct from each other because following observation is made:
Instant Application
Patent No. 11,126,251
1. A memory module for power management in memory, comprising: a first memory device; a second memory device; a controller; and a power management component configured to: receive a primary supply signal; modify the primary supply signal; and allocate a modified primary supply signal to the first memory device and the second memory device.
3. The memory module of claim 1, wherein the power management component comprises a power management integrated circuit (PMIC).
4. The memory module of claim 3, wherein the PMIC includes one or more regulators.
5. The memory module of claim 4, wherein the one or more regulators include a low-dropout (LDO) regulator, a buck-boost converter, a buck regulator, or a combination thereof.
7. The memory module of claim 1, wherein the power management component is configured to modify the primary supply signal based on an operation state.
8. The memory module of claim 7, wherein the operation state is a reduced power state or an active state.
10. The memory module of claim 8, wherein the reduced power state is a sleep state, a standby state, or an off state.
9. An apparatus, comprising: a non-volatile dual in-line memory module (NVDIMM), wherein the NVDIMM includes a first number of memory devices and a second number of memory devices coupled to a controller, wherein the NVDIMM is couplable to a host, and wherein the NVDIMM is configured to: perform operations on the first number of memory devices with a first set of signals from a power control manager, wherein the power control manager converts a number of input signals into the first set of signals based on power management criteria for the first number of memory devices; and perform operations on the second number of memory devices with a second set of signals from the power control manager while performing operations on the first number of memory devices with the first set of signals, wherein the power control manager converts the number of input signals into the second set of signals based on power management criteria for the second number of memory devices to increase efficiency of the apparatus by decreasing a magnitude of the second set of signals.
11. The apparatus of claim 9, wherein the power management component includes a power management integrated circuit (PMIC).
14. The apparatus of claim 12, wherein the one or more regulators include a low-dropout (LDO) regulator, a buck-boost converter, a buck regulator, or a combination thereof.
7. The apparatus of claim 6, wherein the operation state is an active state or a reduced power state.
8. The apparatus of claim 7, wherein the reduced power state is one of a sleep state, a standby state, or an off state.
11. A memory module for power management in memory, comprising: a first memory device; a second memory device; a controller; and a power management component configured to: receive a primary supply signal; modify the primary supply signal to be compatible with operation of the first memory device and modify the primary supply signal to be compatible with the second memory device; and allocate the modified primary supply signal to be compatible with the operation of the first memory device to the first memory device and the modified primary supply signal to be compatible with the second memory device to the second memory device.
1. An apparatus, comprising: a first number of memory devices coupled to a host via a first number of ports of the first number of memory devices, wherein a first number of commands are executed via a first number of signals from a power management component to transfer first data between the first number of memory devices and the host via the first number of ports, wherein the power management component converts a number of input signals into the first number of signals based on power management criteria for the first number of memory devices; and a second number of memory devices coupled to the first number of memory devices via a second number of ports, wherein a second number of commands via a second number of signals from the power management component are executed to transfer second data between the first number of memory devices and the second number of memory devices via the second number of ports while the first number of commands are executed to transfer the first data between the first number of memory devices and the host, wherein the power management component converts the number of input signals into the second number of signals based on power management criteria for the second number of memory devices to increase efficiency of the apparatus by decreasing a magnitude of the second number of signals.
15. A system for power management in memory, comprising: a host controller; and a memory module, comprising: a primary power supply; a plurality of devices including: a first memory device; a second memory device; and a controller; and a power management component configured to: modify a power supply voltage received from the primary power supply; and allocate a modified power supply voltage to each of the plurality of devices.
16. The system of claim 15, wherein the power management component is configured to allocate the modified power supply voltage to the first memory device based on power management criteria for the first memory device.
17. The system of claim 15, wherein the power management component is configured to allocate the modified power supply voltage to the second memory device based on power management criteria for the second memory device.
18. The system of claim 15, wherein the modified power supply voltage allocated to the first memory device is different from the modified power supply voltage allocated to the second memory device.
19. The system of claim 15, wherein the memory module is a dual in-line memory module (DIMM).
20. The system of claim 15, wherein the memory module is a non-volatile dual in-line memory module (NVDIMM).
1. An apparatus, comprising: a first number of memory devices coupled to a host via a first number of ports of the first number of memory devices, wherein a first number of commands are executed via a first number of signals from a power management component to transfer first data between the first number of memory devices and the host via the first number of ports, wherein the power management component converts a number of input signals into the first number of signals based on power management criteria for the first number of memory devices; and a second number of memory devices coupled to the first number of memory devices via a second number of ports, wherein a second number of commands via a second number of signals from the power management component are executed to transfer second data between the first number of memory devices and the second number of memory devices via the second number of ports while the first number of commands are executed to transfer the first data between the first number of memory devices and the host, wherein the power management component converts the number of input signals into the second number of signals based on power management criteria for the second number of memory devices to increase efficiency of the apparatus by decreasing a magnitude of the second number of signals.
4. The apparatus of claim 1, wherein the first number of signals and the second number of signals are different.
10. The apparatus of claim 9, wherein the NVDIMM is configured to perform operations on the first number of memory device with a third set of signal from the power control manager.
As demonstrated, the claims 1,4.7-11 and 14 of U.S. Patent No. 1,126,251 disclose all the features of claims 1 ,3-8, 10, 11 and 15-20 of the instant application with minor obvious variations. Thus, it would have been obvious to one of ordinary skill in the art having the claims 1,4.7-11 and 14 of Patent 1,126,251 to modify the claims to achieve the features of claims 1 ,3-8, 10, 11 and 15-20 of the instant application.
Claims 1,3-4,6,11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims -1-4,7,14-15 and 17 of U.S. Patent No. 12,135,600. Although the claims at issue are not identical, they are not patentably distinct from each other because following observation is made:
Instant Application
Patent NO. 12,135,600
1. A memory module for power management in memory, comprising: a first memory device; a second memory device; a controller; and a power management component configured to: receive a primary supply signal; modify the primary supply signal; and allocate a modified primary supply signal to the first memory device and the second memory device.
3. The memory module of claim 1, wherein the power management component comprises a power management integrated circuit (PMIC).
4. The memory module of claim 3, wherein the PMIC includes one or more regulators.
6. The memory module of claim 1, wherein the power management component comprises a capacitive voltage divider (CVD).
1. An apparatus, comprising: a first memory device; a second memory device coupled to the first memory device; a register clock driver coupled to the first memory device; and a controller coupled to the register clock driver, wherein the controller is configured to send a command to the first memory device via the register clock driver, and wherein the controller comprises: a power management component coupled to the first memory device and the second memory device, wherein the power management component is configured to: receive an input signal; convert the input signal by increasing a voltage of the input signal into a first signal to be compatible with the first memory device being a particular type of memory device; convert the input signal by decreasing a voltage of the input signal into a second signal to save power and to be compatible with the second memory device being a different particular type of memory device; and transmit the first signal to the first memory device and the second signal to the second memory device.
4. The apparatus of claim 3, wherein the power management component includes a power management integrated circuit (PMIC).
7. The apparatus of claim 6, wherein the PMIC includes one or more regulators, wherein the one or more regulators are configured to convert the modified primary supply signal.
3. The apparatus of claim 1, wherein the power management component includes a capacitive voltage divider (CVD).
11. A memory module for power management in memory, comprising: a first memory device; a second memory device; a controller; and a power management component configured to: receive a primary supply signal; modify the primary supply signal to be compatible with operation of the first memory device and modify the primary supply signal to be compatible with the second memory device; and allocate the modified primary supply signal to be compatible with the operation of the first memory device to the first memory device and the modified primary supply signal to be compatible with the second memory device to the second memory device.
12. The memory module of claim 11, further comprising a register clock driver (RCD).
13. The memory module of claim 11, further comprising a buffer.
14. The memory module of claim 11, further comprising registers.
1. An apparatus, comprising: a first memory device; a second memory device coupled to the first memory device; a register clock driver coupled to the first memory device; and a controller coupled to the register clock driver, wherein the controller is configured to send a command to the first memory device via the register clock driver, and wherein the controller comprises: a power management component coupled to the first memory device and the second memory device, wherein the power management component is configured to: receive an input signal; convert the input signal by increasing a voltage of the input signal into a first signal to be compatible with the first memory device being a particular type of memory device; convert the input signal by decreasing a voltage of the input signal into a second signal to save power and to be compatible with the second memory device being a different particular type of memory device; and transmit the first signal to the first memory device and the second signal to the second memory device.
2. The apparatus of claim 1, wherein the controller includes a buffer and a number of registers.
15. A system for power management in memory, comprising: a host controller; and a memory module, comprising: a primary power supply; a plurality of devices including: a first memory device; a second memory device; and a controller; and a power management component configured to: modify a power supply voltage received from the primary power supply; and allocate a modified power supply voltage to each of the plurality of devices.
16. The system of claim 15, wherein the power management component is configured to allocate the modified power supply voltage to the first memory device based on power management criteria for the first memory device.
17. The system of claim 15, wherein the power management component is configured to allocate the modified power supply voltage to the second memory device based on power management criteria for the second memory device.
18. The system of claim 15, wherein the modified power supply voltage allocated to the first memory device is different from the modified power supply voltage allocated to the second memory device.
19. The system of claim 15, wherein the memory module is a dual in-line memory module (DIMM).
20. The system of claim 15, wherein the memory module is a non-volatile dual in-line memory module (NVDIMM).
14. An apparatus, comprising: a first number of memory devices; a second number of memory devices coupled to the first memory devices via a number of ports; a register clock driver coupled to the first number of memory devices; and a controller coupled to the register clock driver, wherein the controller is configured to send a signal to the register clock driver to indicate which of the first number of memory devices will execute a command, and wherein the controller comprises: a power management component coupled to the first number of memory devices and the second number of memory devices, wherein the power management component is configured to: receive a number of input signals; convert the number of input signals by increasing a voltage of each of the number of signals into a first number of signals to be compatible with the first number of memory devices being a particular type of memory device; convert the number of input signals by decreasing a voltage of each of the number of input signals into a second number of signals to save power and be compatible with the second number of memory devices being a different particular type of memory device; and transmit the first number of signals to the first number of memory devices and the second number of signals to the second number of memory devices.
15. The apparatus of claim 14, wherein the apparatus is a dual in-line memory module (DIMM).
17. The apparatus of claim 14, wherein the second number of memory devices are non-volatile memory (NVM) devices.
As demonstrated, the claims 1-4,7,14-15 and 17 of U.S. Patent No. 1,126,251 disclose all the features of claims 1,3-4,6,11-20 of the instant application with minor obvious variations. Thus, it would have been obvious to one of ordinary skill in the art having the claims 1-4,7,14-15 and 17 of Patent 1,126,251 to modify the claims to achieve the features of claims 1,3-4,6,11-20 of the instant application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, and 7-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lym et al. (Lym) (Pub No. US 2020/0279588).
Regarding Claim 1 Lym discloses: A memory module [Fig.1, Fig.8 and Fig.9, Memory Module] for power management [Fig.8 and Fig.9 PMIC, Abstract [0066] power management integrated circuit configured to adjust a level] in memory, comprising: a first memory device; [Fig.9, item 1-k First Memory] a second memory device; [Fig.9, item 40, Second Memory] a controller [Fig.1, item 50, Memory controller]; and a power management component [Fig.9, item 82, PMIC] configured to: receive a primary supply signal; modify the primary supply signal; and allocate a modified primary supply signal to the first memory device and the second memory device. [Abstract, [009]-[0010] a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices. a plurality of devices including a plurality of first memories, a second memory. [0084] the PMIC 82, after adjusting the level of a battery power VIN_BT that is supplied from the battery module 60A, may supply power supply voltages to the first memories 20, the second memory 40, ]
Regarding Claim 2 Lym discloses: the primary supply signal is generated by a battery. [Fig.9, item 60A battery [0084]]
Regarding Claim 3 Lym discloses: the power management component comprises a power management integrated circuit (PMIC). [Fig.9, item 82, PMIC]
Regarding Claim 4 Lym discloses: the PMIC includes one or more regulators.[[0084] the PMIC adjusting (regulating) the level of a battery power.]
Regarding Claim 7 Lym discloses: the power management component is configured to modify the primary supply signal based on an operation state. [[0014] –[0015] at least one of an operating speed, an operating time, and an operating period of at least one of the plurality of memories is adjusted, [0102] an operating speed of a DRAM may vary depending on the level of the power supply voltage. [0143] The controller 50 may control at least one of an operating speed, an operating time, and an operating period of the first memories 20 and the second memory 40 based on the received temperature information. Alternatively, each of the first memories 20 and the second memory 40 may control its own operating speed, operating time, and operating period based on the temperature information received therein.]
Regarding Claim 8 Lym discloses: the operation state is a reduced power state or an active state. [[0095] claim 3 mode set unit configured to set or change modes of the voltage generators to one of an active mode, a sleep mode, and an off mode.]
Regarding Claim 9 Lym discloses: the modified primary supply signal is a higher voltage signal in the active state and a lower voltage signal in the reduced power state. [[0095] claim 3 mode set unit configured to set or change modes of the voltage generators to one of an active mode, a sleep mode, and an off mode.]
Regarding Claim 10 Lym discloses: the reduced power state is a sleep state, a standby state, or an off state. [[0095] claim 3 mode set unit configured to set or change modes of the voltage generators to one of an active mode, a sleep mode, and an off mode.]
Regarding Claim 11 Lym discloses: A memory module [Fig.1, Fig.8 and Fig.9, Memory Module] for power management in memory, [Fig.8 and Fig.9 PMIC, Abstract [0066] power management integrated circuit configured to adjust a level] comprising: a first memory device; [Fig.9, item 1-k First Memory] a second memory device; [Fig.9, item 40, Second Memory] a controller[Fig.1, item 50, Memory controller]; and a power management component [Fig.9, item 82, PMIC] configured to: receive a primary supply signal; [[0084], power supply from battery] modify the primary supply signal to be compatible with operation of the first memory device and modify the primary supply signal to be compatible with the second memory device; and allocate the modified primary supply signal to be compatible with the operation of the first memory device to the first memory device and the modified primary supply signal to be compatible with the second memory device to the second memory device. [Abstract, [009]-[0010] a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices. a plurality of devices including a plurality of first memories, a second memory. [0084] the PMIC 82, after adjusting the level of a battery power VIN_BT that is supplied from the battery module 60A, may supply power supply voltages to the first memories 20, the second memory 40, ]
Regarding Claim 12 Lym discloses: The memory module of claim , further comprising a register clock driver (RCD). [[0054] include a register clock driver (hereinafter referred to as “RCD”) 80]
Regarding Claim 13 Lym discloses: The memory module of claim 11, further comprising a buffer. [[0074] he memory module 210 may further include at least one of an RCD (register clock driver) 80, an SPD (serial presence detector) 84, and DBs (date buffers) 86. ]
Regarding Claim 14 Lym discloses: The memory module of claim 11, further comprising registers. [[0131] default values that are stored as a result that is obtained through a test by a manufacturer or a tester, may be stored in registers 20A]
Regarding Claim 15 Lym discloses: A system for power management [Fig.8 and Fig.9 PMIC, Abstract [0066] power management integrated circuit configured to adjust a level] in memory, [Fig.1, Fig.8 and Fig.9, Memory Module] comprising: a host controller; [Fig.1, item 50, Memory controller] and a memory module, [Fig.1, Fig.8 and Fig.9, Memory Module] comprising: a primary power supply; [[0084], power supply from battery] a plurality of devices including: a first memory device; [Fig.9, item 1-k First Memory] a second memory device; [Fig.9, item 40, Second Memory] and a controller; [Fig.1, item 50, Memory controller] and a power management component[Fig.8 and Fig.9 PMIC, Abstract [0066] power management integrated circuit configured to adjust a level] configured to: modify a power supply voltage received from the primary power supply; and allocate a modified power supply voltage to each of the plurality of devices. [Abstract, [009]-[0010] a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices. a plurality of devices including a plurality of first memories, a second memory. [0084] the PMIC 82, after adjusting the level of a battery power VIN_BT that is supplied from the battery module 60A, may supply power supply voltages to the first memories 20, the second memory 40, [0155] since only a group (rank), which is determined to have a temperature equal to or lower than the allowable value, operates and a group (rank), which is determined to have a temperature higher than the allowable value, is set to an idle mode, the temperature of the memory module 210 may be lowered while the function of the memory module 210 may be maintained. Claim 3, a mode set unit configured to set or change modes of the voltage generators to one of an active mode, a sleep mode, and an off mode. ]
Regarding Claim 16 Lym discloses: the power management component is configured to allocate the modified power supply voltage to the first memory device based on power management criteria for the first memory device. [Abstract, [009]-[0010] a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices. a plurality of devices including a plurality of first memories, a second memory. [0084] the PMIC 82, after adjusting the level of a battery power VIN_BT that is supplied from the battery module 60A, may supply power supply voltages to the first memories 20, the second memory 40, [0155] since only a group (rank), which is determined to have a temperature equal to or lower than the allowable value, operates and a group (rank), which is determined to have a temperature higher than the allowable value, is set to an idle mode, the temperature of the memory module 210 may be lowered while the function of the memory module 210 may be maintained. Claim 3, a mode set unit configured to set or change modes of the voltage generators to one of an active mode, a sleep mode, and an off mode. ]
Regarding Claim 17 Lym discloses: the power management component is configured to allocate the modified power supply voltage to the second memory device based on power management criteria for the second memory device. [Abstract, [009]-[0010] a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices. a plurality of devices including a plurality of first memories, a second memory. [0084] the PMIC 82, after adjusting the level of a battery power VIN_BT that is supplied from the battery module 60A, may supply power supply voltages to the first memories 20, the second memory 40, [0155] since only a group (rank), which is determined to have a temperature equal to or lower than the allowable value, operates and a group (rank), which is determined to have a temperature higher than the allowable value, is set to an idle mode, the temperature of the memory module 210 may be lowered while the function of the memory module 210 may be maintained. Claim 3, a mode set unit configured to set or change modes of the voltage generators to one of an active mode, a sleep mode, and an off mode. ]
Regarding Claim 18 Lym discloses: the modified power supply voltage allocated to the first memory device is different from the modified power supply voltage allocated to the second memory device. [[0158] power supply voltages that are supplied to the first memories 20 may be differentiated for the first memories 20 based on parameter characteristics, [0159] power supply voltages that are supplied to the first memories 20 may be differentiated for the first memories 20 based on a temperature]
Regarding Claim 19 Lym discloses: the memory module is a dual in-line memory module (DIMM). [[0068] a dual in-line memory module (DIMM)]
Regarding Claim 20 Lym discloses: the memory module is a non-volatile dual in-line memory module (NVDIMM). [[0063] memory module 200 (e.g., NVDIMM)]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-6 are are rejected under 35 U.S.C. 103 as being unpatentable over Lym et al. (Lym) (Pub No. US 2020/0279588) in view of Rowley (Pub NO. US 2020/0075061)
Regarding Claim 5 Lym does not teach the one or more regulators include a low-dropout (LDO) regulator, a buck-boost converter, a buck regulator, or a combination thereof.
However, Rowley teaches the one or more regulators include a low-dropout (LDO) regulator, a buck-boost converter, a buck regulator, or a combination thereof. [[0012] [0057] regulator and an example of an SVR can be a buck regulator, among other types of SVRs and LVRs. An LDO can be configured to operate at low quiescent voltages and/or currents]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use the buck regulator of Rowley,s system in Lym’s system to improve efficiency and reduce heat generation.
Regarding Claim 6 Lym does not teach the power management component comprises a capacitive voltage divider (CVD).
However, Rowley teaches the power management component comprises a capacitive voltage divider (CVD) [Abstract, a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD)]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use the capacitive voltage divider (CVD) of Rowley,s system in the PMIC of Lym’s system to improve efficiency of the system.
Conclusion
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/ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175