DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,3-4,21,11-15, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Prather et al. (Pub No. US 2019/0267071).
Regrading claim 1, Prather discloses: a memory module [Fig.9, Fig.10 ] for power management in memory, comprising: a first memory device comprising a first type of memory device; [Fig.9, item 907, DRAM memory] a second memory device comprising a second type of memory device that is different from the first type of memory device; [Fig.9, item 911, non-volatile NAND memory] a controller; [Fig.10, item 1006, CPU corresponds to a controller] and a power management component [Fig9, item 905, PMIC corresponds a power management component] configured to: receive a primary supply signal; [Fig.9, item 904, [0031] connector 903 receives corresponding a supply voltage 904 from an external device] based on the first memory device comprising the first type of memory device, modify the primary supply signal into a first modified primary supply signal; [[0031] The PMIC 905 can convert the supply voltage 904 to one or more output voltages (e.g., VDD, VDDQ, VPP, VSS, VSSQ, etc.), such as first output voltage 906 for use by one or more connected memories, such as DRAM memories 907 (e.g., which can correspond to the memory device 100 illustrated in FIG. 1 and described in greater detail above). In this regard, the first output voltage 906 can have a different voltage level (e.g., 1.1V, 1.3V, 1.5V, etc.) than that of the supply voltage 904 (e.g., 12V, 5V, 3.3V, etc.), and/or can have a different tolerance (e.g. ±1%, ±3%, ±5%, etc.) than that of the supply voltage 904 (e.g. ±5%, ±10%, etc.).] based on the second memory device comprising the second type of memory device, modify the primary supply signal into a second modified primary supply signal; [[0031] The PMIC 905 can further supply a second output voltage 910 to other internal devices, such as a non-volatile NAND memory 911. The second output voltage can have a different voltage level than that of the first output voltage 906, and/or can have a different tolerance than that of the second output voltage 906.] and allocate the first modified primary supply signal to the first memory device and the second modified primary supply signal to the second memory device.[[0031] The PMIC 905 can convert the supply voltage 904 to one or more output voltages (e.g., VDD, VDDQ, VPP, VSS, VSSQ, etc.), such as first output voltage 906 for use by one or more connected memories, such as DRAM memories 907. The PMIC 905 can further supply a second output voltage 910 to other internal devices, such as a non-volatile NAND memory 911.]
Regarding claim 3, Prather discloses: the power management component comprises a power management integrated circuit (PMIC). [PMIC 908 in Fig.9 and PMIC 1004 in Fig.10]
Regarding claim 4, Prather discloses: the PMIC includes one or more regulators. [[0022] [0024] a voltage regulator such as PMIC]
Regarding claim 21, Prather discloses: the first type of memory device comprises a volatile memory device and the second type of memory device comprises a non-volatile memory device. [Fig.9, non-volatile NAND memory and DRAM]
Regrading claim 11, Prather discloses: A memory module [Fig.9, Fig.10 ] for power management in memory, comprising: a first memory device comprising a first type of memory device; [Fig.9, item 907, DRAM memory] a second memory device comprising a second type of memory device; [Fig.9, item 911, non-volatile NAND memory] a controller; [Fig.10, item 1006, CPU corresponds to a controller] and a power management component [Fig9, item 905, PMIC corresponds a power management component] configured to: receive a primary supply signal; [Fig.9, item 904, [0031] connector 903 receives corresponding a supply voltage 904 from an external device] modify the primary supply signal into a first modified primary supply signal compatible with operation of the first memory device based on the first memory device comprising the first type of memory device; [[0031] The PMIC 905 can convert the supply voltage 904 to one or more output voltages (e.g., VDD, VDDQ, VPP, VSS, VSSQ, etc.), such as first output voltage 906 for use by one or more connected memories, such as DRAM memories 907 (e.g., which can correspond to the memory device 100 illustrated in FIG. 1 and described in greater detail above). In this regard, the first output voltage 906 can have a different voltage level (e.g., 1.1V, 1.3V, 1.5V, etc.) than that of the supply voltage 904 (e.g., 12V, 5V, 3.3V, etc.), and/or can have a different tolerance (e.g. ±1%, ±3%, ±5%, etc.) than that of the supply voltage 904 (e.g. ±5%, ±10%, etc.)] modify the primary supply signal [[to be]] into a second modified primary supply signal compatible with the second memory device based on the second memory device comprising the second type of memory device; [[0031] The PMIC 905 can further supply a second output voltage 910 to other internal devices, such as a non-volatile NAND memory 911. The second output voltage can have a different voltage level than that of the first output voltage 906, and/or can have a different tolerance than that of the second output voltage 906.] and allocate the first modified primary supply signal to be compatible with the operation of the first memory device to the first memory device and the second modified primary supply signal to be compatible with the second memory device to the second memory device. [[0031] The PMIC 905 can convert the supply voltage 904 to one or more output voltages (e.g., VDD, VDDQ, VPP, VSS, VSSQ, etc.), such as first output voltage 906 for use by one or more connected memories, such as DRAM memories 907. The PMIC 905 can further supply a second output voltage 910 to other internal devices, such as a non-volatile NAND memory 911.]
Regarding claim 12, Prather discloses: comprising a register clock driver (RCD). [Fig.1, item 130, internal clock circuit corresponds to a register clock driver]
Regarding claim 13, Prather discloses: further comprising a buffer. [[0018] input buffer]
Regarding claim 14, Prather discloses: further comprising registers. [[0033] a memory including one or more registers for storing information about the output voltage(s) of the PMIC]
Regrading claim 15, Prather discloses: a system for power management in memory, [Fig.9, Fig.10 ] comprising: a host controller; [[0024] receives a supply voltage 204 from an external device (e.g., a host device to which the memory device 200 is connected by the edge connector 202) and provides the supply voltage 204 to a voltage regulator such as PMIC 205. ] comprising: a primary power supply; [Fig.9, item 904, [0031] connector 903 receives corresponding a supply voltage 904 from an external device] a plurality of devices including: a first memory device comprising a first type of memory device; [Fig.9, item 907, DRAM memory] a second memory device comprising a second type of memory device; [Fig.9, item 911, non-volatile NAND memory] and a controller; [Fig.10, item 1006, CPU corresponds to a controller]and a power management component [Fig9, item 905, PMIC corresponds a power management component] configured to: based on the first memory device comprising the first type of memory device, [Fig.9, item 907, DRAM memory] modify a power supply voltage received from the primary power supply [Fig.9, item 904, [0031] connector 903 receives corresponding a supply voltage 904 from an external device] into a first modified power supply voltage; [[0031] The PMIC 905 can convert the supply voltage 904 to one or more output voltages (e.g., VDD, VDDQ, VPP, VSS, VSSQ, etc.), such as first output voltage 906 for use by one or more connected memories, such as DRAM memories 907 (e.g., which can correspond to the memory device 100 illustrated in FIG. 1 and described in greater detail above). In this regard, the first output voltage 906 can have a different voltage level (e.g., 1.1V, 1.3V, 1.5V, etc.) than that of the supply voltage 904 (e.g., 12V, 5V, 3.3V, etc.), and/or can have a different tolerance (e.g. ±1%, ±3%, ±5%, etc.) than that of the supply voltage 904 (e.g. ±5%, ±10%, etc.).] based on the second memory device [Fig.9, item 911, non-volatile NAND memory] comprising the second type of memory device, modify the power supply voltage received from the primary power supply into a second modified power supply voltage; [[0031] The PMIC 905 can further supply a second output voltage 910 to other internal devices, such as a non-volatile NAND memory 911. The second output voltage can have a different voltage level than that of the first output voltage 906, and/or can have a different tolerance than that of the second output voltage 906.] and allocate the first modified power supply voltage to the first memory device and the second modified power supply voltage to the second memory device each of the plurality of devices. [[0031] The PMIC 905 can convert the supply voltage 904 to one or more output voltages (e.g., VDD, VDDQ, VPP, VSS, VSSQ, etc.), such as first output voltage 906 for use by one or more connected memories, such as DRAM memories 907. The PMIC 905 can further supply a second output voltage 910 to other internal devices, such as a non-volatile NAND memory 911.
Regarding claim 18, Prather discloses: the first modified power supply voltage allocated to the first memory device is different from the second modified power supply voltage allocated to the second memory device. [[0031] The PMIC 905 can convert the supply voltage 904 to one or more output voltages (e.g., VDD, VDDQ, VPP, VSS, VSSQ, etc.), such as first output voltage 906 for use by one or more connected memories, such as DRAM memories 907 (e.g., which can correspond to the memory device 100 illustrated in FIG. 1 and described in greater detail above). In this regard, the first output voltage 906 can have a different voltage level (e.g., 1.1V, 1.3V, 1.5V, etc.) than that of the supply voltage 904 (e.g., 12V, 5V, 3.3V, etc.), and/or can have a different tolerance (e.g. ±1%, ±3%, ±5%, etc.) than that of the supply voltage 904 (e.g. ±5%, ±10%, etc.). The PMIC 905 can further supply a second output voltage 910 to other internal devices, such as a non-volatile NAND memory 911. The second output voltage can have a different voltage level than that of the first output voltage 906, and/or can have a different tolerance than that of the second output voltage 906.]
Regarding claim 19, Prather discloses: the memory module is a dual in-line memory module (DIMM). [[0021] DIMM]
Regarding claim 20, Prather discloses: the memory module is a non-volatile dual in-line memory module (NVDIMM). [[0031] memory module, such as a non-volatile DIMM (NVDIMM)]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 7, 9, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Prather et al. (Pub No. US 2019/0267071) in view of Lym (Pub NO. US 2020/0279588)
Regarding Claim 2 Prather does not explicitly teach the primary supply signal is generated by a battery.
However, Lym teaches the primary supply signal is generated by a battery [Fig.9, item 60A battery]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use a battery to power the memory module of Prather’s system as taught by Lym.
Using a battery to power a memory module provides continuous power to retain data and settings.
Regarding claim 7, Prather does not teach: the power management component is configured to modify the primary supply signal into the first modified primary supply signal or the second modified primary supply signal based on an operation state comprising a reduced power state or an active state.
However, Lym teaches the power management component is configured to modify the primary supply signal into the first modified primary supply signal or the second modified primary supply signal based on an operation state comprising a reduced power state or an active state. [[0014] – [0015] at least one of an operating speed, an operating time, and an operating period of at least one of the plurality of memories is adjusted, [0102] an operating speed of a DRAM may vary depending on the level of the power supply voltage. [0143] The controller 50 may control at least one of an operating speed, an operating time, and an operating period of the first memories 20 and the second memory 40 based on the received temperature information. Alternatively, each of the first memories 20 and the second memory 40 may control its own operating speed, operating time, and operating period based on the temperature information received therein.]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to modify the power supply in Prather’s system using Lym’s teaching to reduce overall power consumption.
Regarding claim 9 Lym teaches: at least one of the first modified primary supply signal or the second modified primary supply signal is a higher voltage signal in the active state and a lower voltage signal in the reduced power state. [[0095] claim 3 mode set unit configured to set or change modes of the voltage generators to one of an active mode, a sleep mode, and an off mode.]
Regarding claim 10 Lym teaches: the reduced power state is a sleep state, a standby state, or an off state. [[0095] claim 3 mode set unit configured to set or change modes of the voltage generators to one of an active mode, a sleep mode, and an off mode.]
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Prather et al. (Pub No. US 2019/0267071) in view of Rowley (Pub NO. US 2020/0075061)
Regarding Claim 5 Prather does not teach the one or more regulators include a low-dropout (LDO) regulator, a buck-boost converter, a buck regulator, or a combination thereof.
However, Rowley teaches the one or more regulators include a low-dropout (LDO) regulator, a buck-boost converter, a buck regulator, or a combination thereof. [[0012] [0057] regulator and an example of an SVR can be a buck regulator, among other types of SVRs and LVRs. An LDO can be configured to operate at low quiescent voltages and/or currents]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use the buck regulator of Rowley,s system in Prather’s system to improve efficiency and reduce heat generation.
Regarding Claim 6 Prather does not teach the power management component comprises a capacitive voltage divider (CVD).
However, Rowley teaches the power management component comprises a capacitive voltage divider (CVD) [Abstract, a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD)]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention use the capacitive voltage divider (CVD) of Rowley,s system in the PMIC of Prather’s system to improve efficiency of the system.
Claim 22 rejected under 35 U.S.C. 103 as being unpatentable over Prather et al. (Pub No. US 2019/0267071) in view Hass Costa et al. (Pub No. US 2018/0225059)
Regarding Claim 22 Prather does not teach the power management component is configured to modify the primary supply signal into the first modified primary supply signal by increasing the magnitude of the primary supply signal based on the first type of memory device comprising the volatile memory device.
However, Hass Costa teaches: the power management component is configured to modify the primary supply signal into the first modified primary supply signal by increasing the magnitude of the primary supply signal based on the first type of memory device comprising the volatile memory device. [[0035] instructions to increase power supplied to at least one component associated with the volatile memory responsive to determining to transition the system to a higher-performance mode]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to increase the power to the DRAM using Hass’s teaching to reduce latency.
Claim 23 rejected under 35 U.S.C. 103 as being unpatentable over Prather et al. (Pub No. US 2019/0267071) in view of Rowley (Pub No. US 2019/0278363)
Regarding claim 23, Prather does not teach the power management component is configured to modify the primary supply signal into the second modified primary supply signal by decreasing a magnitude of the primary supply signal based on the second type of memory device comprising the non-volatile memory device.
However, Rowley teaches the power management component is configured to modify the primary supply signal into the second modified primary supply signal by decreasing the magnitude of the primary supply signal based on the second type of memory device comprising the non-volatile memory device. [[0044] educe and/or turn off the power provided to some of the components of the storage device (119), such as the non-volatile memory (123),]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to reduce the power to the NVRAM in Prather’s system using Rowley’s teaching to reduce system power consumption.
Response to Arguments
Applicant’s arguments, see Remarks filed on 06/16/2026, with respect to the rejection(s) of claims 1-7,9-15 and 18-23 under USC 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art refinances.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAHID CHOUDHURY whose telephone number is (571)270-5153. The examiner can normally be reached Monday-Friday.
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/ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175
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