Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
This office action is FINAL.
Response to Arguments
Applicant’s arguments with respect to claim(s) [ 1-20 ] have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner maintains Malladi reference since there are no other arguments regarding this reference
Regarding 35 U.S.C. 112(f), amended limitation have overcome the 35 U.S.C. 112(f) interpretation, the previous interpretation has been withdrawn for claims 1-20.
Regarding 35 U.S.C. 102, amended limitation overcome the previous 35 U.S.C. 102 rejection for claims [1-3, 9-11,17-19], and thus are moot. New ground of rejection has been made in light of Das and O’Connor. Accordingly new grounds of rejection have been made for claims 1-20 under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [ 1-3, 4-11, 13-20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Malladi et al. (Pub No. US 20210374056), hereinafter "Malladi", In view of Das (Pub No. US 20200226018), hereinafter "Das"].
As per claim 1, Malladi significantly teaches a cache-coherent persistent memory (PMEM) device, comprising:
an input/output (I/O) interface (to coordinate I/O [Malladi PP 0126]);
a volatile memory device (The volatile memory may be [Malladi PP 0176]);
an error correction module which is configurable according to an I/O protocol (In various embodiments, the ECC and security block implement various Schemes for ECC including aside-band ECC [Malladi PP 0119])
a non-volatile storage device (a non-volatile computer-readable storage [Malladi PP 0040]); and
at least one processor configured to: receive a store command and data corresponding to the store command from a host device (Such a load-store interface may extend the coherence domain beyond an individual server, or CPU or host [Malladi PP 0085]) through the I/O interface (The controller 137 may include an additional “backdoor” 100 GbE or other network interface circuit 125 (in addition to the network interface used to connect to the host) [Malladi PP 0072]) according to a cache-coherent memory protocol (Additionally, the disclosed systems can receive, via the first controller, data via the network interface using the cache coherent protocol [Malladi PP 0156]);
based on the store command, control the volatile memory device to store the data (store the second data on the second memory based on the cache coherent protocol. [Malladi PP 0156]);
encode the data to generate encoded data using the error correction module (another ECC encoder that generates, encodes, or otherwise determines ECC code words. [Malladi PP 0070]); and
control the non-volatile storage device to store the encoded data (the non-volatile memory controller 124 is configured to store data [Malladi PP 0039]).
Malladi does not explicitly teach “wherein the error correction module comprises a cyclic redundancy check (CRC) module including a CRC encoder and a CRC decoder, and an error correction code (ECC) module including an ECC encoder and an ECC decoder;”
However, Das, in an analogous art, teaches wherein the error correction module comprises a cyclic redundancy check (CRC) module including a CRC encoder and a CRC decoder (A cyclic redundancy check (CRC) code generator 314 can include one or more CRC code generators [Das PP 0056], CRC decode logic 334 can check for errors [Das PP 0057]), and an error correction code (ECC) module including an ECC encoder and an ECC decoder (a forward error correction (FEC) encoder 316 , to encode the data with error correcting code (ECC). [Das PP 0056], The FEC decoder 332 can decode ECC bits [Das PP 0057]);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 2, Malladi significantly teaches wherein the at least one processor is further configured to: obtain the encoded data from the non-volatile storage device (The non-volatile memory system 102, in the depicted embodiment, includes an ECC storage module 150. The ECC storage module 150, in one embodiment, is configured to distribute storage of an ECC code word among a plurality of memory elements 123. For example, in certain embodiments, the ECC storage module 150 may determine ECC code words of data (e.g., encode data into ECC code words) [Malladi PP 0030]);
control the error correction module to decode the encoded data to reconstruct the data (In such an embodiment, there may be a higher likelihood that the correction module 202 may decode [Malladi PP 0079]);
control the volatile memory device to store the data (the volatile storage or memory media may be used to store at least portions of the databases, database instances, database management systems, data [Malladi PP 0165]);
receive a load command corresponding to the data from the host device through the I/O interface according to the cache-coherent memory protocol (The server-linking switch 112 may perform flow control, e.g., by reordering independent requests. In some embodiments, because the interface is load-store, RDMA is optional but there may be intervening RDMA requests that use the PCIe physical medium (instead of 100 GbE). In such an embodiment, a remote host may initiate an RDMA request, which may be transmitted to the enhanced capability CXL switch [Malladi PP 0090]); and
based on the load command, provide the data to the host device through the I/O interface (communicate to a host and other devices via an interface that consists of three channels in each direction: Request, Response, and Data [Malladi PP 0141]).
As per claim 3, Malladi significantly teaches wherein the volatile memory device comprises a dynamic random access memory (DRAM) device (volatile storage or memory media 1215, including but not limited to RAM, DRAM [Malladi PP 0165]), and wherein the non-volatile storage device comprises a non-volatile memory express (NVMe) solid-state drive (SSD) (a non-volatile computer-readable storage medium may include a floppy disk, flexible disk, hard disk, solid-state storage (SSS) (for example a solid-state drive (SSD)) [Malladi PP 0040]).
As per claim 5, Malladi does not explicitly teach “wherein the CRC encoder is configured to perform CRC encoding on the data based on a CRC code to generate CRC-encoded data; and the encoded data is generated based on the CRC-encoded data.”
However, Das, in an analogous art, teaches wherein the CRC encoder is configured to perform CRC encoding on the data based on a CRC code to generate CRC-encoded data (A cyclic redundancy check (CRC) code generator 314 can include one or more CRC code generators [Das PP 0056]); and
the encoded data is generated based on the CRC-encoded data (The TX logical sub-block 306 can include logic to prepare the data stream for transmission across the link. [Das PP 0056]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 6, Malladi does not explicitly teach “wherein the ECC encoder is configured to perform ECC encoding on the data based on an ECC code to generate ECC-encoded data, and the encoded data comprises the ECC-encoded data.”
However, Das, in an analogous art, teaches wherein the ECC encoder is configured to perform ECC encoding on the data based on an ECC code to generate ECC-encoded data (a forward error correction (FEC) encoder 316 , to encode the data with error correcting code (ECC). [Das PP 0056]), and the encoded data comprises the ECC-encoded data (A sender can encode a message in a redundant way by using an error-correcting code (ECC). [Das PP 0002]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 7, Malladi does not explicitly teach “wherein, based on receiving a configuration command according to the I/O protocol from the host device through the I/O interface, the at least one processor is further configured to perform a configuration procedure on at least one of the CRC module and the ECC module included in the error correction module.”
However, Das, in an analogous art, teaches wherein, based on receiving a configuration command according to the I/O protocol from the host device through the I/O interface (while controller 715 is to communicate with I/O devices [Das PP 0079]), the at least one processor is further configured to perform a configuration procedure on at least one of the CRC module and the ECC module included in the error correction module (The dynamic selection of FEC, CRC, and flit sizes can be performed autonomously by hardware and/or by hardware with software help. [Das PP 0054]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 8, Malladi in view of Das does not explicitly teach “wherein, based on receiving a configuration command according to the I/O protocol from the host device through the I/O interface, the at least one processor is further configured to perform at least one from among enabling at least one of the CRC module and the ECC module included in the error correction module, setting a type of a CRC code corresponding to the CRC module, and setting a type of an ECC code corresponding to the ECC module.”
However, Das, in an analogous art, teaches wherein, based on receiving a configuration command according to the I/O protocol from the host device through the I/O interface (while controller 715 is to communicate with I/O devices [Das PP 0079]), the at least one processor is further configured to perform at least one from among enabling at least one of the CRC module and the ECC module included in the error correction module (In embodiments, the CRC code generator 314 can be bypassed while maintaining clock integrity … The FEC encoder 316 can also be bypassed without compromising clock integrity. [Das PP 0056]), setting a type of a CRC code corresponding to the CRC module (In this example, the transmitter-side logical sub-block 400 includes two CRC generators: CRC # 1 Gen 404 and CR # 2 Gen 410. [Das PP 0062]), and setting a type of an ECC code corresponding to the ECC module (Further, in this example, 3 types of FEC encoders are used: ECC # 1 414 , ECC # 2 416 , and ECC # 3 418 . [Das PP 0064]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 9, Malladi significantly teaches wherein the at least one processor is further configured to control the error correction module to encode the data (another ECC encoder that generates, encodes, or otherwise determines ECC code words. [Malladi PP 0070]), and to control the non-volatile storage device to store the encoded data (the non-volatile memory controller 124 is configured to store data [Malladi PP 0039]), based on at least one from among detecting a change in a power state of the cache-coherent PMEM device, and receive flush command from the host device through the I/O interface (As mentioned above, one or more of the memory modules 135 may include persistent memory, or “persistent storage” (i.e., storage within which data is not lost when external power is disconnected), If a memory module 135 is presented as a persistent device, the controller 137 of the memory module 135 may manage the persistent domain, e.g., it may store, in the persistent storage data identified (e.g., as a result of an application making a call to a corresponding operating system function) by a processing circuit 115 as requiring persistent storage. In such an embodiment, a software API may flush caches and data to the persistent storage. [Malladi PP 0062]).
As per claim 10, Malladi significantly teaches a cache-coherent persistent memory (PMEM) device, comprising: an input/output (I/O) interface (to coordinate I/O [Malladi PP 0126]);
a volatile memory device (The volatile memory may be [Malladi PP 0176]);
an error correction module that is configurable according to an I/O protocol (the ECC and security block can include any other block that directly or indirectly communicates with the above two blocks. [Malladi PP 0118]),
a non-volatile storage device (a non-volatile computer-readable storage [Malladi PP 0040]); and
at least one processor configured to:
based on receiving a store command and data corresponding to the store command from a host device (Such a load-store interface may extend the coherence domain beyond an individual server, or CPU or host [Malladi PP 0085]) through the I/O interface (The controller 137 may include an additional “backdoor” 100 GbE or other network interface circuit 125 (in addition to the network interface used to connect to the host) [Malladi PP 0072]) according to a cache-coherent memory protocol (Additionally, the disclosed systems can receive, via the first controller, data via the network interface using the cache coherent protocol [Malladi PP 0156]), control the volatile memory device to store the data (store the second data on the second memory based on the cache coherent protocol. [Malladi PP 0156]),
based on at least one from among detecting a change in a power state of the cache- coherent PMEM device, and receiving a flush command from the host device through the I/O interface (As mentioned above, one or more of the memory modules 135 may include persistent memory, or “persistent storage” (i.e., storage within which data is not lost when external power is disconnected), If a memory module 135 is presented as a persistent device, the controller 137 of the memory module 135 may manage the persistent domain, e.g., it may store, in the persistent storage data identified (e.g., as a result of an application making a call to a corresponding operating system function) by a processing circuit 115 as requiring persistent storage. In such an embodiment, a software API may flush caches and data to the persistent storage. [Malladi PP 0062]) according to the I/O protocol, control the encoder module to encode the data to generate encoded data (another ECC encoder that generates, encodes, or otherwise determines ECC code words. [Malladi PP 0070]), and control the non-volatile storage device to store the encoded data (the non-volatile memory controller 124 is configured to store data [Malladi PP 0039]),
control the encoder correction module to decode the encoded data to reconstruct the data (In such an embodiment, there may be a higher likelihood that the correction module 202 may decode [Malladi PP 0079]),
control the volatile memory device to store the data (the volatile storage or memory media may be used to store at least portions of the databases, database instances, database management systems, data [Malladi PP 0165]), and
based on receiving a load command from the host device through the I/O interface according to the cache-coherent memory protocol, provide the data to the host device through the I/O interface (communicate to a host and other devices via an interface that consists of three channels in each direction: Request, Response, and Data (Malladi PP 0141)).
Malladi does not explicitly teach “wherein the error correction module comprises a cyclic redundancy check (CRC) module including a CRC encoder and a CRC decoder, and an error correction code (ECC) module including an ECC encoder and an ECC decoder;”
However, Das, in an analogous art, teaches wherein the error correction module comprises a cyclic redundancy check (CRC) module including a CRC encoder and a CRC decoder (A cyclic redundancy check (CRC) code generator 314 can include one or more CRC code generators [Das PP 0056], CRC decode logic 334 can check for errors [Das PP 0057]), and an error correction code (ECC) module including an ECC encoder and an ECC decoder (a forward error correction (FEC) encoder 316 , to encode the data with error correcting code (ECC). [Das PP 0056], The FEC decoder 332 can decode ECC bits [Das PP 0057]);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 11, Malladi significantly teaches wherein: the volatile memory device comprises a dynamic random access memory (DRAM) device (volatile storage or memory media 1215, including but not limited to RAM, DRAM [Malladi PP 0165]), and wherein the non-volatile storage device comprises a non-volatile memory express (NVMe) solid-state drive (SSD) (a non-volatile computer-readable storage medium may include a floppy disk, flexible disk, hard disk, solid-state storage (SSS) (for example a solid-state drive (SSD)) [Malladi PP 0040]).
As per claim 13, Malladi does not explicitly teach “wherein the CRC encoder is configured to perform CRC encoding on the data based on a CRC code to generate CRC-encoded data, the encoded data is-being generated based on the CRC-encoded data; and the CRC decoder is configured to perform CRC decoding on the CRC-encoded data based on the CRC code to obtain the data.”
However, Das, in an analogous art, teaches wherein the CRC encoder is configured to perform CRC encoding on the data based on a CRC code to generate CRC-encoded data (A cyclic redundancy check (CRC) code generator 314 can include one or more CRC code generators [Das PP 0056]), the encoded data is-being generated based on the CRC-encoded data (The TX logical sub-block 306 can include logic to prepare the data stream for transmission across the link. [Das PP 0056]); and
the CRC decoder is configured to perform CRC decoding on the CRC-encoded data based on the CRC code to obtain the data (CRC decode logic 334 can check for errors [Das PP 0057]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 14, Malladi does not explicitly teach “wherein the ECC encoder configured to perform ECC encoding on the data based on an ECC code to generate ECC-encoded data, the encoded data comprises the ECC-encoded data, and the ECC decoder is configured to perform ECC decoding on the ECC-encoded data based on the ECC code to obtain the data.”
However, Das, in an analogous art, teaches wherein the ECC encoder configured to perform ECC encoding on the data based on an ECC code to generate ECC-encoded data (a forward error correction (FEC) encoder 316 , to encode the data with error correcting code (ECC). [Das PP 0056]), the encoded data comprises the ECC-encoded data (A sender can encode a message in a redundant way by using an error-correcting code (ECC). [Das PP 0002]), and the ECC decoder is configured to perform ECC decoding on the ECC-encoded data based on the ECC code to obtain the data (The FEC decoder 332 can decode ECC bits in received data blocks and perform error correction. [Das PP 0057]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 15, Malladi does not explicitly teach “wherein, based on a receiving a configuration command according to the I/O protocol from the host device through the I/O interface, the at least one processor is further configured to perform a configuration procedure on at least one of the CRC module and the ECC module included in the encoder correction module.”
However, Das, in an analogous art, teaches wherein, based on a receiving a configuration command according to the I/O protocol from the host device through the I/O interface (while controller 715 is to communicate with I/O devices [Das PP 0079]), the at least one processor is further configured to perform a configuration procedure on at least one of the CRC module and the ECC module included in the encoder correction module (receiving a request to change the first set of CRC encoders to a second set of CRC encoders [Das PP 0165], receiving a request to change the first set of ECC encoders to a second set of ECC encoders [Das PP 0167]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 16, Malladi does not explicitly teach “wherein, based on a receiving a configuration command according to the I/O protocol from the host device through the I/O interface, the at least one processor is further configured to perform at least one from among: enabling at least one of the CRC module and the ECC module included in the encoder correction module, setting a type of a CRC code corresponding to the CRC module, and setting a type of an ECC code corresponding to the ECC module.”
However, Das, in an analogous art, teaches wherein, based on a receiving a configuration command according to the I/O protocol from the host device through the I/O interface (while controller 715 is to communicate with I/O devices [Das PP 0079]), the at least one processor is further configured to perform at least one from among: enabling at least one of the CRC module and the ECC module included in the encoder correction module (wherein the logical PHY comprises a CRC encoder bypass. [Das PP 0154], herein the logical PHY comprises a CRC decoder bypass. [Das PP 0156], wherein the logical PHY comprises an ECC encoder bypass. [Das PP 0158], wherein the logical PHY comprises an ECC decoder bypass. [Das PP 0160]), setting a type of a CRC code corresponding to the CRC module (a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. [Das PP 0153]), and setting a type of an ECC code corresponding to the ECC module (a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol; and a second set of ECC encoders corresponding to the second interconnect protocol. [Das PP 0157]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 17, Malladi significantly teaches a method of operating a persistent memory (PMEM) device, the method comprising:
receiving a store command and data corresponding to the store command from a host device (Such a load-store interface may extend the coherence domain beyond an individual server, or CPU or host [Malladi PP 0085]) through an input/output (I/O) interface (The controller 137 may include an additional “backdoor” 100 GbE or other network interface circuit 125 (in addition to the network interface used to connect to the host) [Malladi PP 0072]) according to a cache-coherent memory protocol (Additionally, the disclosed systems can receive, via the first controller, data via the network interface using the cache coherent protocol [Malladi PP 0156]);
based on the store command, storing the data in a volatile memory device (store the second data on the second memory based on the cache coherent protocol. [Malladi PP 0156]);
encoding the data using an error correction module to generate encoded data, wherein the error correction module is configurable according to an I/O protocol (another ECC encoder that generates, encodes, or otherwise determines ECC code words. [Malladi PP 0070])
storing the encoded data in a non-volatile storage device (the non-volatile memory controller 124 is configured to store data [Malladi PP 0039]).
Malladi does not explicitly teach “and comprises a cyclic redundancy check (CRC) module including a CRC encoder and a CRC decoder, and an error correction code (ECC) module including an ECC encoder and an ECC decoder”
However, Das, in an analogous art, teaches and comprises a cyclic redundancy check (CRC) module including a CRC encoder and a CRC decoder (A cyclic redundancy check (CRC) code generator 314 can include one or more CRC code generators [Das PP 0056], CRC decode logic 334 can check for errors [Das PP 0057]), and an error correction code (ECC) module including an ECC encoder and an ECC decoder (a forward error correction (FEC) encoder 316 , to encode the data with error correcting code (ECC). [Das PP 0056], The FEC decoder 332 can decode ECC bits [Das PP 0057]);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 18, Malladi significantly teaches obtaining the encoded data from the non-volatile storage device (The non-volatile memory system 102, in the depicted embodiment, includes an ECC storage module 150. The ECC storage module 150, in one embodiment, is configured to distribute storage of an ECC code word among a plurality of memory elements 123. For example, in certain embodiments, the ECC storage module 150 may determine ECC code words of data (e.g., encode data into ECC code words) [Malladi PP 0030]);
decoding the encoded data using the error correction module (In such an embodiment, there may be a higher likelihood that the correction module 202 may decode [Malladi PP 0079]);
storing the data in the volatile memory device (the volatile storage or memory media may be used to store at least portions of the databases [Malladi PP 0165]); and
receiving a load command corresponding to the data from the host device through the I/O interface according to the cache-coherent memory protocol (The server-linking switch 112 may perform flow control, e.g., by reordering independent requests. In some embodiments, because the interface is load-store, RDMA is optional but there may be intervening RDMA requests that use the PCIe physical medium (instead of 100 GbE). In such an embodiment, a remote host may initiate an RDMA request, which may be transmitted to the enhanced capability CXL switch [Malladi PP 0090]);
based on the load command, providing the data to the host device through the I/O interface (communicate to a host and other devices via an interface that consists of three channels in each direction: Request, Response, and Data (Malladi PP 0141)).
As per claim 19, Malladi teaches wherein the volatile memory device comprises a dynamic random access memory (DRAM) device (volatile storage or memory media 1215, including but not limited to RAM, DRAM [Malladi PP 0165]), and wherein the non-volatile storage device comprises a non-volatile memory express (NVMe) solid-state drive (SSD) (a non-volatile computer-readable storage medium may include a floppy disk, flexible disk, hard disk, solid-state storage (SSS) (for example a solid-state drive (SSD)) [Malladi PP 0040]).
As per claim 20, Malladi does not explicitly teach “receiving a configuration command according to the I/O protocol from the host device through the I/O interface; and performing a configuration procedure on at least one of the CRC module and the ECC module included in the error correction module.”
However, Das, in an analogous art, teaches receiving a configuration command according to the I/O protocol from the host device through the I/O interface (while controller 715 is to communicate with I/O devices [Das PP 0079]); and
performing a configuration procedure on at least one of the CRC module and the ECC module included in the error correction module (The dynamic selection of FEC, CRC, and flit sizes can be performed autonomously by hardware and/or by hardware with software help. [Das PP 0054], a request for a different FEC/CRC code [Das PP 0073]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi to incorporate Das’s teachings of CRC encoding/decoding and FEC encoding/decoding, in order to improve error performance (Forward Error Correction (FEC) can be used to limit an effective Bit Error Rate (BER) to an acceptable range … the redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message [Das PP 0002]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Claim(s) [ 4, 12] are rejected under 35 U.S.C. 103 as being unpatentable over [Malladi, In view of Das, in further view of O'Connor et al. (Pub No. US 10901839), hereinafter "O'Connor"].
As per claim 4, Malladi in view of Das does not explicitly teach “wherein an error rate of the volatile memory device is lower than an error rate of the non- volatile storage device, and an error rate of the cache-coherent PMEM device is higher than the error rate of the volatile memory device.”
However, O’Connor, in an analogous art, teaches wherein an error rate of the volatile memory device is lower than an error rate of the non- volatile storage device (traditional, low RBER DRAM devices may have RBERs in the range of about 1E-20 [O’Connor PP 0019], NAND flash device (whose bit error rate increases rapidly once the write endurance limit is reached). [O’Connor PP 0020]), and
an error rate of the cache-coherent PMEM device is higher than the error rate of the volatile memory device (Each of the plurality of memory devices is assigned a refresh rate and is characterized as one of a high random bit error rate (RBER) memory device and a low RBER memory device … The memory buffer device also includes common error correction logic configured to detect and correct error conditions in data read from both high RBER memory devices and low RBER memory devices. [O’Connor PP 0002]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi in view of Das to incorporate O’Connor’s teachings of differing error rates, in order to improve reliability and data integrity (The common error correction design described herein, which may be implemented by common error correction logic (hardware and/or software), can be utilized for both high RBER memory devices and low RBER memory devices while minimizing a performance impact on dynamic random access memory (DRAM) operation. [O’Connor PP 0020]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 12, Malladi in view of Das does not explicitly teach “wherein: an error rate of the volatile memory device is lower than an error rate of the non- volatile storage device, and an error rate of the cache-coherent PMEM device is higher than the error rate of the volatile memory device.”
However, Das, in an analogous art, teaches wherein: an error rate of the volatile memory device is lower than an error rate of the non- volatile storage device (traditional, low RBER DRAM devices may have RBERs in the range of about 1E-20 [O’Connor PP 0019], NAND flash device (whose bit error rate increases rapidly once the write endurance limit is reached). [O’Connor PP 0020]), and an error rate of the cache-coherent PMEM device is higher than the error rate of the volatile memory device (Each of the plurality of memory devices is assigned a refresh rate and is characterized as one of a high random bit error rate (RBER) memory device and a low RBER memory device … The memory buffer device also includes common error correction logic configured to detect and correct error conditions in data read from both high RBER memory devices and low RBER memory devices. [O’Connor PP 0002]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cache coherent memory device disclosed by Malladi in view of Das to incorporate O’Connor’s teachings of differing error rates, in order to improve reliability and data integrity (The common error correction design described herein, which may be implemented by common error correction logic (hardware and/or software), can be utilized for both high RBER memory devices and low RBER memory devices while minimizing a performance impact on dynamic random access memory (DRAM) operation. [O’Connor PP 0020]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM FUAD ALHWAMDEH whose telephone number is (571)272-5501. The examiner can normally be reached Mon-Fri 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAREEM FUAD ALHWAMDEH/ Examiner, Art Unit 2112
/ALBERT DECADY/ Supervisory Patent Examiner, Art Unit 2112
Prosecution Insights