9Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claims 1, 2, and 11 were amended.
This is a Final Action.
Response to Arguments
Applicant's arguments filed 07/23/2026 have been fully considered but they are not persuasive.
With respect to independent claims, and specifically, claim 1 and applicant argument on pages 7-8. Applicant argues “The Office Action concedes that Duzly does not teach this recovery feature of the claims2, relying on Post to support the rejection; Post does not. Post is generally concerned with storing redundant metadata for user data in the location that the user data is written and another location. With respect to the term "metadata" in this context, Post states "[t]hat metadata may include, for example, the logical address where the user data is going to be stored" (Post 1 [0068]). The use of the logical block for metadata suggests a fundamental difference between what Post is discussing and what is happening in the present claims. For example, in the system of the present claims, the logical address for data in the garbage collection will be unchanged in the L2P table. In fact, what is being stored in the third location is no longer traditional metadata for the written data, but rather a recovery artifact to "reach into" a physical location after it has been removed from the metadata of the copied data. Further, the Post explicitly requires access to "direction data" in the written metadata to locate the backup. The present claims rely on a predefined relationship that enables the location of the garbage collected physical address even when the written data is inaccessible.
Post is directed to recovering metadata for an unreadable page, not to preserving a source reference for garbage collection recovery as claimed. The purpose of Post is to recover metadata when a memory location becomes inaccessible (Post 1 [0010]; Fig. 7). Post's passing mention of garbage collection (Post 1 [0042]) merely lists garbage collection as one occasion on which redundant metadata may be looked up; it does not teach writing a source reference to a destination- related location during garbage collection in order to recover all data from the garbage collected physical location. The Office Action's stated reason to combine-"to improve metadata recoverability and robustness"-is, at most, a reason to duplicate metadata describing data at its current location. It supplies no reason to preserve a reference to a garbage collection source at a location keyed to the garbage collection destination. The proposed combination is thus supported only by impermissible hindsight drawn from Applicant's own disclosure. See MPEP § 2142”.
Examiner respectfully disagrees with the applicant. The rejection does not rely on Post’s logical-address metadata, by itself, as teaching the claimed physical address of the first physical storage unit. Rather, the references are relied upon for their respective teachings.
Duzly teaches relocation of valid data during garbage collection from a first physical storage location to a second physical storage location and corresponding updating of the logical-to-physical mapping. Kanno expressly teaches, in the garbage-collection context, preserving both the previous physical address and the new physical address of copied data. In Kanno’s GC operation, valid data are copied from a GC source block to a GC destination block, the device notifies the host of the logical address, previous flash address, and new flash address, and the host thereafter updates its LUT to map the new flash address to the logical address. Kanno further defines the previous flash address as the physical address of the previous physical storage location and the new flash address as the physical address of the new physical storage location. Thus, preservation of GC-source physical-address reference is not derived from Applicant’s disclosure.
Post is relied upon for a different feature: redundantly storing memory-management information at another physical location having a predetermined relationship to the primary location and recovering that information when the primary location is inaccessible. Contrary to Applicant’s characterization, Post does not limit “metadata” to a logical block address. Post expressly defines metadata broadly to include information used for logical-to-physical mapping and, more generally, information used to manage the operation and memory location of the NVM. Therefore, Post is not limited to consulting stored directional information; a predetermined physical/geometric relationship itself may identify the associated backup location.
Post also explains that redundant metadata may be obtained from a backup location when the current memory location becomes inaccessible and identifies GC as one of the memory-management operations in which such redundant metadata may be consulted. Accordingly, Post supplies the known technique of storing management information in a deterministically related physical location so that such information remains recoverable upon loss of access to the primary location.
Therefore, the proposed modification is not based on treating Post’s exemplary logical address as the claimed GC-source physical address. Rather, a POSITA would have applied Post’s known redundant metadata placement and recovery technique to the previous physical-address information expressly maintained by Kanno during GC. The resulting system would store the know previous/source physical-address information at a backup location having a predefined relationship to the newly written physical location, thereby permitting the source physical-address information to remain recoverable if the newly written location becomes inaccessible. This is the predictable application of Post’s redundancy technique to known item of GC-management information disclosed by Kanno, rather than a reconstruction derived from application’s disclosure.
In view of compact prosecution, examiner is proposing a claim which would overcome the current prior arts, incorporating the inventive concept:
1. (Proposed Amended) An apparatus comprising:
an interface to multiple physical units of a storage device; and
processing circuitry configured to:
obtain a first reference, including a physical address from a logical-to-physical (L2P) mapping table, to a first physical storage unit that is subject to a garbage collection operation, the first physical storage unit being part of the storage device;
locate data at the first physical storage unit using the physical address in the first reference;
write, using the interface, the data from the first physical storage unit to a second physical storage unit as part of the garbage collection operation;
write, using the interface, the first reference to the first physical storage unit to a third physical storage unit, wherein the second physical storage unit and the third physical storage unit are NAND pages, the third physical storage unit includes a spare area in which the first reference, including the physical address of the first physical storage unit, is written, and the third physical storage unit has a predefined physical relationship to the second physical storage unit comprising a page-like offset such that the third physical storage unit is identifiable from a second reference to the second physical storage unit by applying the page-line offset;
update the L2P mapping table to replace the first reference to the first physical storage unit with the second reference to the second physical storage unit;
after updating the L2P mapping table, detect an asynchronous power loss during the garbage collection operation that renders the second physical storage unit potentially corrupt;
in response to detecting the asynchronous power loss, identify the third physical storage unit from the second reference to the second physical storage unit based on the page-line offset;
retrieve, using the interface, the first reference including the physical address of the first physical storage unit from the spare area of the third physical storage unit;
locate the data at the first physical storage unit using the physical address in the retrieved first reference; and
rewrite, using the interface, the data from the first physical storage unit to the second physical storage unit to restore the data at the second physical storage unit.
None of the references explicitly teach the combination of a source PBA in a related NAND-page spare area, destination address derived page line offset and post L2P-update failure recovery using the still-good source copy. The support in the instant application can be found in Paragraphs 39-47, 53-67, Figs 5-7 and 9. If the claims are amended as recited above (verbatim), the application would be in condition for allowance, pending the eTD.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-6, 19 and 20 of Patent No. US 12,056,046. Although the conflicting claims are not identical, they are not patentably distinct from each other because
Instant Application
US Patent: US 12,056,046
1 and 11
1-2
2 and 12
1
3 and 13
19
4 and 14
20
5 and 15
1
6 and 16
1
7 and 17
3
8 and 18
4
9 and 19
5
9 and 19
6
This is an obviousness-type double patenting rejection because the conflicting claims have in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-11 and 15-20 rejected under 35 U.S.C. 103 as being unpatentable over Duzly et al. (US 2020/034307) in view of Post (US 2012/0198123) further in view of Kanno et al. (US 2019/0129841)
1. Duzly teaches, An apparatus comprising (Abstract, Duzly):
an interface to multiple physical units of a storage device; and processing circuitry configured to (Fig 1:140, 150 $ 160-1 – teaches an interface coupled to multiple physical storage units; Fig 2:141, 145 & 214 – teaches process circuitry, control mapping circuitry and Garbage collection circuitry):
obtain a first reference, including a physical address from a logical-to-physical (L2P) mapping table, to a first physical storage unit (fig 1, Paragraphs 11 and 44 – teaches logical-to-physical table 144 may be configured to store logical addresses with corresponding physical addresses of stored information in one or more storage media 160 of storage device 120, Duzly) that is subject to a garbage collection operation(Paragraph 51 – teaches that the first physical address/location is the source location involved in GC, i.e., the first physical storage unit is subject to the GC operation, Duzly & Paragraph 63 – teaches L2P table containing physical-address references for data subject to GC, wherein under BRI, the first physical address in the L2P table is the first reference, Duzly);
write, using the interface, the data from the first physical storage unit to a second physical storage unit as part of the garbage collection operation (Paragraph 51 - teaches when performing GC, a portion or sub-portion of valid data residing at a first physical address must be identified, reproduced in entirety in another physical location of memory identified by a second physical address, permitting the memory identified by the first physical address to be erased – thus disclosing copying valid data from first physical storage location to a second physical location during GC, Duzly);
update the L2P mapping table to replace the first reference to the first physical storage unit with the second reference to the second physical storage unit (Paragraph 63 - teaches L2P table 144 may be updated after performance of a GC operation… if a page of valid data identified by a first physical address and a first logical address is rewritten to a memory location identified by a second physical address, the storage controller 140 may update L2P table 144 to associate the first logical address with the second physical address – disclosing replacing the old physical address reference in the L2P table with the new Physical-address reference after GC relocation, Duzly).
Duzly does not explicitly teach,
locate data at the first physical storage unit using the physical address in the first reference;
write, using the interface, the first reference to the first physical storage unit to a third physical storage unit, the third physical storage unit having a predefined physical relationship to the second physical storage unit, the predefined physical relationship enabling the physical address in the first reference to the first physical storage unit to be located based on a second reference to the second physical storage unit when the second physical storage unit is inaccessible.
However, Post teaches,
write, using the interface, the first reference to the first physical storage unit to a third physical storage unit (Paragraph 8 - teaches the metadata may include the logical address or any other information generated by the memory interface for use in managing the NVM. The memory interface may additionally store redundant copies of the metadata at one or more other physical addresses; Fig 6:604,612 & 614– teaches writing metadata of a first physical address to another physical address. Under BRI, the “metadata of first physical address” is first reference to the first physical storage unit and the second physical address in Post is the third physical storage unit, Post), the third physical storage unit having a predefined physical relationship to the second physical storage unit (Paragraph 12 - teaches the other memory location … may have a particular geometric relationship or mapping with respect to the current memory location; the redundant metadata may be associated with user data stored in a previous page in the same block and a corresponding page of previous block of the same super block – thus disclosing that the other/backup physical storage unit is selected based on a predefined geometric/physical relationship to the current location, including same-block adjacent pages and corresponding pages in adjacent blocks of a superblock, Post), the predefined physical relationship enabling the physical address in the first reference to the first physical storage unit to be located (Paragraph 43 – the memory locations may be chosen such that there is a one-to-many mapping between the location with the redundant copy and the location with the original metadata and its associated user data- disclosing that the arrangement enables simple flags to identify the original location corresponding to redundant metadata, Post) based on a second reference to the second physical storage unit (Fig 7, Paragraphs 67-68 – teaches when access to the first memory location fails, the memory interface may read a second backup memory location. The second memory location may be selected based on its position in the non-volatile memory relative to the first memory location, Post) when the second physical storage unit is inaccessible (Fig 7, Paragraphs 65-70 – teaches determining whether the first memory location is accessible; if access fails it reads the backup location and when accessible, extracts the metadata associated with the first location, Post).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Duzly with Post because Duzly teaches GC relocation of valid data and corresponding L2P table updating, while Post teaches writing metadata of a first physical address to another physical address selected according to a predefined geometric relationship, such as an adjacent page or corresponding page in an adjacent block of a superblock, in order to improve metadata recoverability and robustness. A POSITA would be motivated to use Post’s redundant-metadata replacement technique in Duzly’s GC system so that reference information associated with a source physical location could be preserved in a physically related backup location, thereby improving reliability of memory management information during or after relation of data, using known memory-layout techniques for predictable benefit.
Kanno teaches,
locate data at the first physical storage unit using the physical address in the first reference (Paragraph 114 – teaches if the read operation control unit 22 receives the read request (read command) designating the physical address… the read operation control unit 22 reads the data from the location to be read, in the block to be read, based on this physical address, Kanno).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify the combination of Duzly and Post with Kanno because Kanno teaches obtaining and using a physical address to directly locate and read data from a physical storage location, thereby reducing address-translation processing and read latency, and further teaches maintaining previous and new physical addresses during garbage collection. A POSITA would therefore have been motivated to apply Kanno’s physical-address-based access technique to the Duzly/Post garbage collection and redundant metadata arrangement to directly identify and access the source data using the stored physical address reference, yielding the predictable benefit of efficient and reliable physical location access.
5. The combination of Duzly, Post and Kanno teach, The apparatus of claim 1, wherein the multiple physical storage units of the storage device are pages (Paragraph 21 teaches – NVM 120 can be organized into ‘blocks’, which are the smallest units of erase and further organized into ‘pages,’ which are the smallest programmable and readable units. Each memory location (e.g. page or block) of NVM 120 can be addressed using a physical address (e.g., a physical page address or physical block address), - disclosing that the physical storage unit may be pages, and that pages are physically addressable memory location, Post).
6. The combination of Duzly, Post and Kanno teach, The apparatus of claim 5, wherein the storage device is a NAND storage device, and wherein physical storage units subject to the garbage collection operation are in a block (Paragraph 21 - teaches NVM 120 can include NAND flash memory based on floating gate or charge trapping technology, Post).
7. The combination of Duzly, Post and Kanno teach, The apparatus of claim 6, wherein the predefined physical relationship is a page line offset (Claim 3 - teaches wherein the first directional field further comprises: an indicator of distance between the first and second logical addresses; Claim 6 – teaches determining an offset distance between a first physical address corresponding to the first logical address and a second physical address corresponding to a second physical address; and programming the indicator with the offset distance – disclosing the predefined relationship may include an offset distance between first and second physical addresses, stored as directional information, under BRI, that offset distance reads on a page line offset, Post).
8. The combination of Duzly, Post and Kanno teach, The apparatus of claim 6, wherein the predefined physical relationship is an offset NAND die (Paragraph 45 – teaches NVM 320 can include one or more dies (i.e., integrated circuits), such as die 0, die 1, die 2, and die 3; and Paragraph 21 – teaches The blocks from corresponding integrated circuits (e.g., blocks having the same position or block number) may form "super blocks." – discloses NAND memory organized into multiple dies and teaches corresponding block/page relationships across different dies via superblocks. Under BRI, selecting a corresponding page/block in another die reads on an offset NAND die relationship, Post).
10. The combination of Duzly, Post and Kanno teach, The apparatus of claim 5, wherein the first reference to a first physical storage unit is written to a spare area of the second physical storage unit (Paragraph 98, 197-199 & 275, Kanno).
Claims 11, 15-20 are similar to claims 1, 5-10 hence rejected similarly.
Claims 2-4 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Duzly et al. (US 2020/034307) in view of Post (US 2012/0198123) and Kanno (US 2019/0129841) further in view of Hsu et al. (US 2020/0081832)
All the limitation of claim 1 are taught above.
2. The combination of Duzly, Post and Kanno teach,
retrieve, using the interface, the first reference to the first physical storage unit from the third physical storage unit based on the predefined physical relationship (Fig 7; Paragraph 10 – teaches in response to determining that data read from a first page is not usable, the NVM interface may read a second page that also contains the metadata for the user data stored at the first page, and may extract the metadata from the second page and may extract the metadata from the second page; and Paragraph 68 & Fig 7:712 – teaches the second memory location may be selected based on its position in the NVM relative to the first memory location – disclosing retrieving metadata associated with a first physical location from another physical storage location chosen based on a predefined physical/geometric relationship. Under BRI, the retrieved metadata is the claimed first reference, Post);
locate the data at the first physical storage unit using the first reference retrieved from the third physical storage unit (Paragraph 18 – teaches detecting a first logical address at first physical address of the portion of the non-volatile memory die, extracting the first logical address from a header of the first physical address & 78 – teaches means for retrieving a logical address stored in the respective sub-portion, identified by a respective physical address – thus disclosing using the physical address reference to identify the corresponding first physical location and retrieve the information/data there, Duzly).
The combination of Duzly, Post and Kanno do not explicitly teach,
sense a failure during the garbage collection operation after updating the L2P mapping table to replace the first reference to the first physical storage unit with the second reference to the second physical storage unit; and
rewriting, using the interface, the data from the first physical storage unit to the second physical storage unit based on the failure.
However, Hsu teaches,
sense a failure during the garbage collection operation after updating the L2P mapping table to replace the first reference to the first physical storage unit with the second reference to the second physical storage unit (Fig 5:S312, S314, S320, S330 – teaches sensing an abnormal event during a garbage collection flow in which data is copied to a destination block and the L2P table is updated, Hsu); and
rewrite, using the interface, the data from the first physical storage unit to the second physical storage unit based on the failure (Claim 4 teaches - when it is determined that the abnormal event has occurred in the destination block, performing step A1: rolling back the L2P address mapping table according to the L2P address backup table and then performing the steps B and C; and Abstract teaches - Step B is copying partial valid data in at least one source block to a destination block according to a segmentation condition , Hsu).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify the combination of Duzly and Post in view of Hsu because Duzly teaches GC relocation, Post teaches storing and recovering source-related metadata/reference information at a physically related backup location, and Hsu teaches detecting an abnormal event during segmented garbage collection, rolling back the L2P table according to backup information, and then reperforming the copy/update sequence. A POSITA would have recognized that applying Hsu’s rollback and recovery mechanism to the Duzly/Post arrangement would have been predictable improved recovery from interrupted GC and prevented mapping inconsistency when failures occur after some mapping entries have already been updated.
3. The combination of Duzly, Post, Kanno and Hsu teach, The apparatus of claim 2, wherein the failure is asynchronous power loss during the garbage collection operation (Claim 4 - teaches the abnormal event comprises a power-off event or a write/read-back failure – disclosing abnormal/failure event can be a power off event which read on power loss, in the context of Hsu’s partial GC flow, this occurs during the GC operations Hsu).
4. The combination of Duzly, Post, Kanno and Hsu teach, The apparatus of claim 2, wherein the failure is a write failure for another physical storage unit subject to the garbage collection operation (Claim 4 - teaches the abnormal event comprises a power-off event or a write/read-back failure – disclosing abnormal/failure event can be a power off event which read on power loss; Hsu’s partial GC flow, the abnormal event occurs in the destination block i.e. another physical storage unit involved in the GC operation, Hsu).
Claims 12, 13 and 14 are similar to claims 2, 3 and 4, respectively hence rejected similarly.
Claim 9 are rejected under 35 U.S.C. 103 as being unpatentable over Duzly et al. (US 2020/034307) in view of Post (US 2012/0198123) and Kanno (US 2019/0129841) further in view of lo et al. (US 9,977,612)
All the limitation of claim 8 are taught above.
9. The combination of Duzly, Post and Kanno does not explicitly teaches, The apparatus of claim 8, wherein the predefined physical relationship maintains a same plane in the offset NAND die.
However, Lo teaches, wherein the predefined physical relationship maintains a same plane in the offset NAND die ( - superblocks can be utilized to achieve paralle or concurrent execution of multiple storage access operations… each block in a superblock can be on one die of a group of NVM dies… a superblock can be comprised of blocks from various planes in a group of dies… multiple blocks within a superblock may be on the same die/plane – disclosing NAND organization by dies and planes, and teaches superblock grouping across dies with die/plan based relationships. Under BRI, selecting a corresponding physical location in another die while preserving the same die/plan organization reads on the predefined physical relationship maintained a same plan in the offset NAND die, Lo).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify the combination of Duzly and Post in view of Lo because Duzly teaches GC relocation and L2P updating, Post teaches storing metadata of a first physical address at another physical location selected by a predefined geometric relationship, and Lo teaches that NAND memory was conventionally organized by dies, planes, blocks, pages and superblocks, including same die/plan arrangements. A POSITA would have recognized that applying Lo’s die/plan based NAND organization to the Duzly/Post system would have predictably enabled the related backup location to be according to known multi-die plane-aware layouts, thereby improving consistency and physical organization of metadata placement in the flash memory device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Camp et al. (US 9,389,792) – teaches reducing read-after-write errors using old data copy (Abstract, Claim 1).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMRESH SINGH whose telephone number is (571)270-3560. The examiner can normally be reached Monday-Friday 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ann J. Lo can be reached at (571) 272-9767. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMRESH SINGH/Primary Examiner, Art Unit 2159
