DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1 (Claims 1-6, 9, 12, and 13) in the reply filed on 09/30/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANG 20210335820.
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Regarding claim 1, figs. 8 of Kang discloses a ferroelectric memory device comprising:
a dielectric layer (IN2/ML1/IN1) including a plurality of ferroelectric areas(MP1) alternately arranged with a plurality of non-ferroelectric areas DP1 in a first direction DR2, the dielectric layer having a tubular structure;
a channel layer CL extending in the first direction on an inner wall of the dielectric layer; and
a gate stack structure GC including a plurality of conductive layers GC surrounding the plurality of ferroelectric areas of the dielectric layer, wherein the plurality of conductive layers are spaced apart in the first direction.
Regarding claim 13, fig. 8 of Kang discloses a ferroelectric memory device comprising:
a gate stack structure GC including a plurality of conductive layers GCs spaced apart in a first direction DR3;
a dielectric layer (IN2/ML1/IN1) disposed within the gate stack structure and including a plurality of ferroelectric areas forming memory cells alternately arranged with a plurality of non-ferroelectric areas in the first direction; and
a channel layer disposed on an inner wall of the dielectric layer.
Regarding claim 2, par [0066] of Kang discloses wherein the dielectric layer includes a hafnium oxide-based material.
Regarding claim 3, par [0066] and [0094] of Kang disclose wherein: the plurality of ferroelectric areas include hafnium oxide (HfO2), and the plurality of non-ferroelectric areas include silicon-doped hafnium oxide (HSO).
Regarding claim 4, par [0066] and [0094] of Kang discloses wherein: the dielectric layer includes a hafnium oxide-based material doped with a dopant, and the dopant includes one or more of zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr).
Regarding claim 9, Kang discloses wherein each of the plurality of non-ferroelectric areas includes an antiferroelectric area (IN2, IN1 – (hafnium oxide (HfO₂, also called hafnia) is intrinsically antiferroelectric) hafnium oxide – par [00141]) and a paraelectric area (DP1).
Regarding claim 12, fig. 9 of Kang discloses further comprising:
an insulating layer BR covering a sidewall of the gate stack structure; and
an air-gap AR formed between consecutive conductive layers of the plurality of conductive layers and adjacent to the insulating layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kang.
Regarding claim 5, Kang discloses claim 1, and discloses wherein each of the ferroelectric areas and the non-ferroelectric areas of the dielectric layer includes silicon-doped hafnium oxide (HSO).
Kang does not discloses a concentration of the silicon is greater in the plurality of non-ferroelectric areas than in the plurality of ferroelectric areas; wherein the concentration of the silicon is 4% or more and less than 9% in the plurality of ferroelectric areas, and is 9% or more in the plurality of non-ferroelectric areas.
Note that comparing Si‑Doped Dielectric Layers in Ferroelectric vs Non‑Ferroelectric Materials. In Si‑doped HfO₂ thin films, increasing silicon doping shifts the material from ferroelectric toward antiferroelectric/paraelectric behavior, with a clear change in dielectric constant, polarization hysteresis, and leakage characteristics. Ferroelectric vs Non‑Ferroelectric Si‑Doped Films
Ferroelectric Si‑doped HfO₂ Exhibits polarization hysteresis loops with remanent polarization and coercive field, indicating stable ferroelectric domains .
Dielectric constant is moderate; ferroelectric films generally have lower κ than antiferroelectric counterparts. Leakage current is relatively low, but increases with higher doping due to defect states.
Non‑ferroelectric (antiferroelectric/paraelectric) Si‑doped HfO₂, at higher Si doping, the film can transition to antiferroelectric behavior, showing double hysteresis loops from reversible antiferroelectric–ferroelectric transitions
Effect of Silicon Doping Concentration:
Low Si doping: Material remains ferroelectric with stable polarization and moderate dielectric constant. Intermediate doping: Partial transition to antiferroelectric; hysteresis loops broaden, dielectric constant rises. High doping: Strong antiferroelectric/paraelectric character; ferroelectricity suppressed; dielectric constant maximized
As such it would have been obvious form a device of Kang comprising wherein a concentration of the silicon is greater in the plurality of non-ferroelectric areas than in the plurality of ferroelectric areas; wherein the concentration of the silicon is 4% or more and less than 9% in the plurality of ferroelectric areas, and is 9% or more in the plurality of non-ferroelectric areas in order to form aFerroelectric vs Non‑Ferroelectric Materials.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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