DETAILED ACTION
This office action is in response to the amendment filed on 04/30/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
In re to claims 15-16 and 18, method claims 15-16 and 18 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-10, 14-16, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pullen US 2005/0010825.
Regarding Claims 1 and 15, Pullen teach (Figures 1and 3) an apparatus (300) comprising: a first phase on-timer (310-315) configured to produce a first reset signal (sent to 309) for determining a turn-off time instant of a high-side switch (307) of a first phase of a power converter (top phase); a feedback control circuit (329 and 330) configured to produce a first set signal (sent to 309) for determining a turn-on time instant of the high-side switch (307) of the first phase of the power converter; a second phase on-timer (321, 322, 324) configured to produce a second reset signal (sent to 320) for determining a turn-off time instant of a high-side switch (318) of a second phase (bottom phase) of the power converter; and a delay generator (331, 389, 328 and 325) configured to receive a first high side gate drive signal of the first phase (Hson1), and produce a delay signal (with 389 and 331) for determining a phase shift between a leading edge of the first high side gate drive signal (when 307 starts conducting) of the first phase and a leading edge of a second high side gate drive signal of the second phase ( when 318 starts conducting, see Fig. 1b when IL1 reaches maximum/minimum and when IL2 reaches maximum/minimum there is a phase shift between the signals determined by the controller which includes the delay circuitry). (For example: par. 8 and 12-17)
Regarding Claim 2, Pullen teach (Figures 1and 3) wherein the power converter is a dual-phase constant on-time power converter (300, par. 12) comprising: the first phase comprising a first step-down converter (at 480); and the second phase comprising a second step-down converter (at 481), and wherein an output inductor of the first step-down converter and an output inductor of the second step-down converter (404 and 427) are connected together and further connected to a load (at the output). (For example: par. 8 and 12-17)
Regarding Claims 3 and 16, Pullen teach (Figures 1and 3) wherein: the feedback control circuit (329-330) comprises a comparator (329) having an inverting input configured to receive a feedback signal (Vout), and a non-inverting input configured to receive a predetermined reference (Vref). (For example: par. 8 and 12-17)
Regarding Claim 4, Pullen teach (Figures 1and 3) wherein the first phase on-timer (310-313) and a first latch (309) form a first on-time generator (309-313) configured to generate a first on-time signal (385) fed into a first control logic block (308), and wherein: based on the first on-time signal, the first control logic block is configured to generate the first high-side gate drive signal and a first low-side gate drive signal (control signals for 306-307) for driving the high-side switch and a low-side switch (306-307) of the first phase of the power converter, respectively; and the first phase on-timer comprises a first ramp generator (with 311-312) configured to generate a first ramp signal, and a first threshold generator (Vref generator) configured to generate a first voltage threshold (Vref), and wherein the first reset signal (from 310) is generated once the first ramp signal exceeds the first voltage threshold (par. 13-15). (For example: par. 8 and 12-17)
Regarding Claim 7, Pullen teach (Figures 1and 3) further comprising a first comparator (310), wherein: an inverting input of the first comparator is configured to receive the first voltage threshold (317); a non-inverting input of the first comparator is configured to receive the first ramp signal (from 311); and an output of the first comparator is configured to generate the first reset signal (sent to 309, fig. 3). (For example: par. 8 and 12-17)
Regarding Claim 8, Pullen teach (Figures 1and 3) wherein: a set input (S of 309) of the first latch is configured to receive the first set signal generated by the feedback control circuit (329-330); a reset input (R of 309) of the first latch is configured to receive the first reset signal generated by the first phase on-timer (from 310); and an output of the first latch is configured to generate the first on-time signal (385). (For example: par. 8 and 12-17)
Regarding Claim 9, Pullen teach (Figures 1and 3) wherein the second phase on-timer (321-322 and 324) and a second latch (320) form a second on-time generator (320-322 and 324) configured to generate a second on-time signal (sent to 320) fed into a second control logic block (319), and wherein: based on the second on-time signal (386), the second control logic block (319) is configured to generate the second high-side gate drive signal and a second low-side gate drive signal for driving the high-side switch and a low-side switch (316 and 318) of the second phase of the power converter, respectively; and the second phase on-timer comprises a second ramp generator (324, 322) configured to generate a second ramp signal (sent to 321), and a second threshold generator configured to generate a second voltage threshold (vref), and wherein the second reset signal (sent to 320) is generated once the second ramp signal exceeds the second voltage threshold (par. 13-15). (For example: par. 8 and 12-17)
Regarding Claims 10 and 18, Pullen teach (Figures 1and 3) wherein: the second ramp generator (324 and 322) is similar to the first ramp generator (311-313) except that an error current is injected into the second ramp generator (from 333) to adjust current balancing between the first phase and the second phase of the power converter (top and bottom phases); and a configuration of the second latch (320) is similar to a configuration of the first latch except that a set input of the second latch is configured to receive the delay signal generated by the delay generator (from 231). (For example: par. 8 and 12-17)
Regarding Claim 14, Pullen teach (Figures 1and 3) wherein: the first phase is a master phase of the power converter; and the second phase is a slave phase of the power converter (par. 15). (For example: par. 8 and 12-17)
Regarding Claim 20, Pullen teach (Figures 1and 3) a dual-phase power (300) converter comprising: a first step-down converter (380) comprising a first high-side switch (307), a first low-side switch(306), and a first inductor (304), wherein: the first high-side switch and the first low-side switch are connected in series between an input voltage bus and ground (vin and gnd); and the first inductor is connected between a common node of the first high-side switch and the first low-side switch, and an output terminal of the power converter (at vout); a second step-down converter (at 381) comprising a second high-side switch (318), a second low-side switch (316), and a second inductor (327), wherein: the second high-side switch and the second low-side switch are connected in series between the input voltage bus and ground (Vin and gnd); and the second inductor is connected between a common node of the second high-side switch and the second low-side switch, and the output terminal of the power converter (at Vout); and a control apparatus (controller of fig. 3) comprising: a first phase on-timer (310-315) configured to produce a first reset signal (sent to 309) for determining a turn-off time instant of a high-side switch (307) of a first phase of the power converter (top phase); a feedback control circuit (329 and 330) configured to produce a first set signal (sent to 309) for determining a turn-on time instant of the high-side switch (307) of the first phase of the power converter; a second phase on-timer (321, 322, 324) configured to produce a second reset signal (sent to 320) for determining a turn-off time instant of a high-side switch (318) of a second phase (bottom phase) of the power converter; and a delay generator (331, 389, 328 and 325) configured to receive a first high side gate drive signal of the first phase and, produce a delay signal (with 389 and 331) for determining a phase shift between a leading edge of the first high side gate driver signal of the first phase and a leading edge of a second high side gate driver signal of the second phase ( when 318 starts conducting, see Fig. 1b when IL1 reaches maximum/minimum and when IL2 reaches maximum/minimum there is a phase shift between the signals determined by the controller which includes the delay circuitry). (For example: par. 8 and 12-17)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pullen in view of Wan US 20110304308 and in view of Yang 2005/0099164.
Regarding Claim 5, Pullen teach (Figures 1and 3) wherein a gate of the fourth ramp transistor (324) is configured to receive the first on-time signal through a ramp inverter (the switch 324 is controlled with Q _). (For example: par. 8 and 12-17)
Pullen does not teach wherein the first ramp generator comprises: a ramp generation current mirror comprising a first ramp transistor and a second ramp transistor, and wherein a gate of the first ramp transistor is connected to a gate of the second ramp transistor; a ramp generation current source connected in series with the first ramp transistor between an input voltage bus of the power converter and ground, and wherein a common node of the ramp generation current source and the first ramp transistor is connected to the gate of the first ramp transistor; a third ramp transistor and a ramp capacitor, and wherein the second ramp transistor, the third ramp transistor and the ramp capacitor are connected in series between the input voltage bus of the power converter and ground, and wherein the first ramp signal is generated at a common node of the third ramp transistor and the ramp capacitor; and a fourth ramp transistor connected in parallel with the ramp capacitor.
Wan teaches (Figures 7-8) wherein the first ramp generator (producing Vt1) comprises: a ramp generation current mirror (fig. 8) comprising a first ramp transistor and a second ramp transistor, and wherein a gate of the first ramp transistor is connected to a gate of the second ramp transistor (fig. 8); a ramp generation current source (Cs2) connected in series with the first ramp transistor between an input voltage bus of the power converter and ground (fig. 8), and wherein a common node of the ramp generation current source and the first ramp transistor is connected to the gate of the first ramp transistor (Fig. 8); a third ramp transistor (sw) and a ramp capacitor (C), and wherein the second ramp transistor, the third ramp transistor and the ramp capacitor are connected in series between the input voltage bus of the power converter and ground (Cs1 and C, Fig. 7), and wherein the first ramp signal is generated at a common node of the third ramp transistor and the ramp capacitor (node t1); and a fourth ramp transistor (q1) connected in parallel with the ramp capacitor (C). (For example: par. 32-34)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pullen to include wherein the first ramp generator comprises: a ramp generation current mirror comprising a first ramp transistor and a second ramp transistor, and wherein a gate of the first ramp transistor is connected to a gate of the second ramp transistor; a ramp generation current source connected in series with the first ramp transistor between an input voltage bus of the power converter and ground, and wherein a common node of the ramp generation current source and the first ramp transistor is connected to the gate of the first ramp transistor; a third ramp transistor and a ramp capacitor, and wherein the second ramp transistor, the third ramp transistor and the ramp capacitor are connected in series between the input voltage bus of the power converter and ground, and wherein the first ramp signal is generated at a common node of the third ramp transistor and the ramp capacitor; and a fourth ramp transistor connected in parallel with the ramp capacitor, as taught by Wan to improve transient ripple in the system.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pullen in view of Xi US 20190356225.
Regarding Claim 6, Pullen teach (Figures 1and 3) the apparatus.
Pullen does not teach wherein the first threshold generator comprises: a first threshold generation transistor and a second threshold generation transistor connected in series between an input voltage bus of the power converter and ground, and wherein a gate of the first threshold generation transistor is configured to receive the first high-side gate drive signal through a threshold generation inverter, and a gate of the second threshold generation transistor is configured to receive the first low-side gate drive signal; a first threshold generation resistor and a second threshold generation resistor connected in series between a common node of the first threshold generation transistor and the second threshold generation transistor, and ground; and a third threshold generation resistor and a threshold generation capacitor connected in series between a common node of the first threshold generation resistor and the second threshold generation resistor, and ground, and wherein the first voltage threshold is generated at a common node of the third threshold generation resistor and the threshold generation capacitor.
Xi teaches (Figure 5 and 9) the first threshold generator comprises: a first threshold generation transistor (q1) and a second threshold generation transistor (Q2) connected in series between an input voltage bus of the power converter and ground (Vcc and gnd), and wherein a gate of the first threshold generation transistor is configured to receive the first high-side gate drive signal (hson) through a threshold generation inverter (504), and a gate of the second threshold generation transistor is configured to receive the first low-side gate drive signal (lson); a first threshold generation resistor (r1) and a second threshold generation resistor (r2) connected in series between a common node of the first threshold generation transistor and the second threshold generation transistor, and ground (see fig. 5); and a third threshold generation resistor (R3) and a threshold generation capacitor (cth2) connected in series between a common node of the first threshold generation resistor and the second threshold generation resistor (R1-R2), and ground, and wherein the first voltage threshold (Vth) is generated at a common node of the third threshold generation resistor and the threshold generation capacitor. (For example: par. 76-78 and 103)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pullen to include the first threshold generator comprises: a first threshold generation transistor and a second threshold generation transistor connected in series between an input voltage bus of the power converter and ground, and wherein a gate of the first threshold generation transistor is configured to receive the first high-side gate drive signal through a threshold generation inverter, and a gate of the second threshold generation transistor is configured to receive the first low-side gate drive signal; a first threshold generation resistor and a second threshold generation resistor connected in series between a common node of the first threshold generation transistor and the second threshold generation transistor, and ground; and a third threshold generation resistor and a threshold generation capacitor connected in series between a common node of the first threshold generation resistor and the second threshold generation resistor, and ground, and wherein the first voltage threshold is generated at a common node of the third threshold generation resistor and the threshold generation capacitor, as taught by Yang to achieve fast transient responses.
Allowable Subject Matter
Claims 11-13, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claims 11 and 19; prior art of record fails to disclose either by itself or in combination: “… a first error current detection current mirror comprising a first error current detection transistor and a second error current detection transistor, and wherein: a drain of the first error current detection transistor is configured to receive a second current sense signal proportional to a current flowing through the high-side switch of the second phase of the power converter; a gate of the first error current detection transistor is connected to a gate of the second error current detection transistor and a drain of the first error current detection transistor; and a source of the first error current detection transistor is connected to ground; a third error current detection transistor having a source configured to receive a first current sense signal proportional to a current flowing through the high-side switch of the first phase of the power converter, and wherein the third error current detection transistor and the second error current detection transistor are connected in series, and a gate of the third error current detection transistor is connected to a first predetermined bias voltage; a second error current detection current mirror comprising a fourth error current detection transistor and a fifth error current detection transistor; a third error current detection current mirror comprising a sixth error current detection transistor and a seventh error current detection transistor; and an eighth error current detection transistor coupled between the second error current detection current mirror and the third error current detection current mirror, and wherein: the fourth error current detection transistor, the eighth error current detection transistor and the sixth error current detection transistor are connected in series between a bias voltage bus and ground; a gate of the eighth error current detection transistor is connected to a second predetermined bias voltage; a common node of the fourth error current detection transistor and the eighth error current detection transistor is connected to the source of the third error current detection transistor; a common node of the eighth error current detection transistor and the sixth error current detection transistor is connected to a common node of the third error current detection transistor and the second error current detection transistor; and the fifth error current detection transistor and the seventh error current detection transistor are connected in series between the bias voltage bus and ground, and wherein the error current is generated at a common node of the fifth error current detection transistor and the seventh error current detection transistor.”
Claims 12 and 17; prior art of record fails to disclose either by itself or in combination: “…delay generation current mirror comprising a first delay generation transistor and a second delay generation transistor, and wherein a gate of the first delay generation transistor is connected to a gate of the second delay generation transistor; a delay generation current source connected in series with the first delay generation transistor between an input voltage bus of the power converter and ground, and wherein a common node of the delay generation current source and the first delay generation transistor is connected to the gate of the first delay generation transistor; a first delay generation capacitor, and wherein the second delay generation transistor and the first delay generation capacitor are connected in series between the input voltage bus of the power converter and ground; a third delay generation transistor connected in parallel with the first delay generation capacitor; a first delay generation resistor and a second delay generation resistor connected in series between the input voltage bus of the power converter and ground; a third delay generation resistor and a second delay generation capacitor connected in series between a common node of the first delay generation resistor and the second delay generation resistor, and ground; a delay generation comparator having a non-inverting input connected to a common node of the second delay generation transistor and the first delay generation capacitor, an inverting input connected to a common node of the third delay generation resistor and the second delay generation capacitor, and an output configured to generate the delay signal; a leading-edge one-shot circuit configured to receive a gate drive signal of the high-side switch of the first phase of the power converter, and generate a pulse signal in response to a leading edge of the gate drive signal of the high-side switch of the first phase of the power converter; and a delay generation latch having a set input configured to receive the delay signal, a reset input configured to receive the pulse signal, and an output connected to a gate of the third delay generation transistor.”
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Response to Arguments
Applicant's arguments filed 04/30/2026 have been fully considered but they are not persuasive.
Applicant argued that “Accordingly, the signals generated by edge delay units 388 and 389 are used to control dead time between phases, rather than to determine a phase shift between leading edges of two high- side gate drive signals. The dead time inherently relates to a non-overlap interval between switching transitions, whereas the claimed phase shift defines a timing relationship between corresponding leading edges of two control signals, which is fundamentally different in both function and implementation. Therefore, Pullen fails to disclose the newly amended features of "a delay generator configured to receive a first high-side gate drive signal of the first phase, and produce a delay signal for determining a phase shift between a leading edge of the first high-side gate drive signal of the first phase and a leading edge of a second high-side gate drive signal of the second phase" (emphasis added)”. However, the claims recite that there is a phase shift not how the phase shift is generate and the delay generator includes not only the 388-389 circuitry includes circuitry 331, 389, 328 and 325 which together generate the claimed delay signal which takes into account the drive signals, the delay and the relationship between Vout and Vref. Figure 1b show the inductor current IL1 and IL2 of each phase when the IL1 reaches its minimum and starts to rise the first high side gate drive signal of the first phase is high and when the IL2 also reaches its minimum and starts to rise the first high side gate driver signal of the second phase is high, this means that the phase shift between the signal IL1 and IL2 reflects the timing relationship between the drive signals. See Figure below at points 1 and 2 when the drive signal of each phase are high this create a phase shift between the signals.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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