DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s Amendment filed on 11/17/2025 in which claims 1, 16 and 20 have been amended and entered of record.
Claims 1-20 are presented for examination.
Response to Argument
Applicant's arguments filed on 11/17/2025 with respect to the amended independent claims 1, 16 and 20 have been considered but are not persuasive because the arguments are based substantially on the newly added limitations by the applicant to the independent claims. Please see the rejection below.
Drawings
Newly amended limitation: “a power supply unit (PSU) controller configured to provide a first voltage level at the first pin to convey a corresponding assignment, and provide a second voltage level at the second pin to convey a corresponding initial activity state”. However, according to Fig. 4, the first pin is directly tied to a 3.3V supply voltage. It is unclear how the system board be able to “convey a corresponding assignment” for each PSU independently as discloses in par [0041] “PIN1 may be utilized for assigning whether a PSU is to operate as a primary PSU or a secondary PSU” while all PSU are tied to the 3.3V supply rail, not to the PSU controller.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, Newly amended limitation: “a power supply unit (PSU) controller configured to provide a first voltage level at the first pin to convey a corresponding assignment, and provide a second voltage level at the second pin to convey a corresponding initial activity state;
wherein the first voltage level is different from the second voltage level,”. There is no disclosure explicitly for the voltage level of the first pin is different from the voltage level of the second pin.
Claims 16 and 20 are similarly rejected as claim 1 above.
Claims 1-15 and 17-19 are rejected due to the rejections of claims 1 and 16. above.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Regarding claim 1, Newly amended limitation “a second voltage level at the second pin to convey a corresponding initial activity state”. The disclosure does not clearly enable the limitation. For example, paragraph [0041] discloses “a voltage level utilized to convey the active state may be different from a voltage level utilized to convey the sleep state. In a number of embodiments, the primary PSU may be configured with the active state and the secondary PSUs may initially be configured with the sleep state”. However, the disclosure also discloses the second pin PIN2 are connected to each other (Fig. 4). It is unclear how the PSU controller is capable of setting one PSU in active state and the other in sleep state. Furthermore, since PIN2 of all DSP are connected to ground through a transistor that control by the PSU controller, it is unclear how the PSU controller can set to a different voltage level than the grounded state “initially”.
Claims 16 and 20 are similarly rejected as claim 1 above.
Claims 1-15 and 17-19 are rejected due to the rejections of claims 1 and 16.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YEH et al., US Patent Publication 20150177805; hereinafter “YEH”.
Regarding claim 20, YEH discloses a method of managing power supplies (Fig. 1), comprising:
determining, by a power supply unit (PSU) controller (Fig. 1, server 30), an assignment [0013] [0014] [0020] among a plurality of power supplies (Fig. 1, 10a and 10b) coupled to a system board (Fig. 1, 20) based on a first voltage level applied to a first configuration pin (Fig. 1, IIC) of each of the plurality of power supplies; and
providing a second voltage level [0024] to a second configuration pin (Fig. 1, I/O) of each of the plurality of power supplies (Fig. 1, 10a and 10b) to convey a corresponding activity state ([0024] “When the present loading power is higher than the heavy loading power, the first controller 121a sets a low voltage level on the first I/O port (I/O)”);
wherein the first voltage level is different from the second voltage level ([0024] low level is different from high), and wherein a power supply operates in an active state if the second voltage level is less than an activation threshold value [0024], the activation threshold value comprising a voltage value stored in a memory element of the PSU (0027] indicates controllers 121a and 121b are processor base thus the pins are controlled by program that stored in memory).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over YEH et al., US Patent Publication 20150177805; hereinafter “YEH” in view of OCHIAI, US Patent Publication 20150323978; hereinafter “OCHIAI”.
Regarding claim 1, YEH discloses a power supply system (Fig. 1), comprising:
a system board (Fig. 1, 20);
two or more power supplies (Fig. 1, 10a and 10b) electrically coupled to the system board (Fig. 1, 20), wherein:
each of the two or more power supplies is configured with a first pin and a second pin (Fig. 1, IIC and I/O) [0020];
the first pin (Fig. 1, IIC) is utilized by each of the two or more power supplies to determine an assignment [0013] [0014] [0020]; and
the second pin (Fig. 1, I/O) is utilized by each of the two or more power supplies to determine an activity state [0013] [0014] [0020]; and
a power supply unit (PSU) controller (Fig. 1, server 30) configured to provide a first voltage level at the first pin (Fig. 1, IIC) to convey a corresponding assignment [0020], and provide a second voltage level at the second pin to convey a corresponding initial activity state;
wherein the first voltage level is different from the second voltage level ([0024] low level is different from high), and wherein each of the power supplies operates in an active state if the second voltage level is less than an activation threshold value [0024].
YEH does not disclose the PSU controller provide a second voltage level at the second pin to convey a corresponding initial activity state. OCHIAI discloses a power supply system having a PSU controller (Fig. 1, 14) provide a voltage level for convey an activity state (Fig. 1, T1 and T2 provide e1 and e2 to power supplies 22 and 23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YEH to incorporate the teaching of OCHIAI and have the PSU controller provide a second voltage level at the second pin to convey a corresponding initial activity state. Doing so would allow the PSU controller fully control the PSUs at the initial state before setting which PSU is a primary PSU.
Regarding claim 2, the combination of YEH and OCHIAI discloses the power supply system of claim 1 above, YEH also discloses the assignment is configured to indicate that one of the two or more power supplies is a primary power supply [0013] [0014] [0020].
Regarding claim 3, the combination of YEH and OCHIAI discloses the power supply system of claim 2 above, YEH also discloses the assignment is configured to indicate that remaining power supplies of the two or more power supplies is a secondary power supply [0013] [0014] [0020].
Regarding claim 16, YEH discloses a power supply (Fig. 1), comprising:
at least one logic circuit (Fig. 1, 121a, 121b or 20) [0019] [0020];
a first configuration pin (Fig. 1, IIC) [0020], configured to determine an assignment [0020];
a second configuration pin (Fig. 1, I/O), that is utilized by the at least one logic circuit to determine an activity state of the power supply [0013] [0014] [0020] a power supply unit (PSU) controller (Fig. 1, server 30) configured to provide a first voltage level at the first configuration pin (Fig. 1, IIC) to convey a corresponding assignment [0020], and wherein a second voltage level at the second configuration pin conveys a corresponding initial activity state;
wherein the first voltage level is different from the second voltage level ([0024] low level is different from high), and wherein the power supply operates in an active state if the second voltage level is less than an activation threshold value [0024].
YEH does not disclose the PSU controller provide a second voltage level at the second pin to convey a corresponding initial activity state. OCHIAI discloses a power supply system having a PSU controller (Fig. 1, 14) provide a voltage level for convey an activity state (Fig. 1, T1 and T2 provide e1 and e2 to power supplies 22 and 23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified YEH to incorporate the teaching of OCHIAI and have the PSU controller provide a second voltage level at the second pin to convey a corresponding initial activity state. Doing so would allow the PSU controller fully control the PSUs at the initial state before setting which PSU is a primary PSU.
Regarding claim 17, the combination of YEH and OCHIAI discloses the power supply of claim 16 above, YEH also discloses the assignment is configured to indicate that the power supply is either a primary power supply or a secondary power supply [0013] [0014] [0020].
Regarding claim 18, the combination of YEH and OCHIAI discloses the power supply of claim 17 above, YEH also discloses activity state is either an active state or a sleep state [0013] [0014] [0020].
Regarding claim 19, the combination of YEH and OCHIAI discloses the power supply of claim 16 above, YEH also discloses the voltage level is checked in a periodic interval [0013] (the controller constantly monitors for loading status and change the setting accordingly).
Claim(s) 4-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of YEH and OCHIAI in view of Landman et al., US Patent Publication 20120284441; hereinafter “Landman”.
Regarding claim 4, the combination of YEH and OCHIAI discloses the power supply system of claim 3 above, the combination of YEH and OCHIAI does not disclose each of the secondary power supplies are ranked within an order of priority. Landman discloses a power supply having a plurality of secondary power supplies are ranked within an order of priority (Fig. 1 and Fig. 3) [0009]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of YEH and OCHIAI to incorporate the teaching of Landman and provide secondary power supplies are ranked within an order of priority. Doing so would allow higher efficiency by further divide power level required by the load and only turn on respective secondary power supplies that match the power requirement by the load, or turning on a correct number of secondary power supplies when the main supply is failed.
Regarding claim 5, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 4 above, Landman also discloses the ranks comprise at least a first secondary (Fig. 1, First Slave Module 46), a second secondary [0024] [0026], and a third secondary [0024] [0026].
Regarding claim 6, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 4 above, YEH also discloses the activity state includes an active state [0013] [0014] [0020].
Regarding claim 7, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 6 above, YEH also discloses the activity state includes a sleep state [0013] [0014] [0020] (inactive is a sleep state).
Regarding claim 8, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 7 above, YEH also discloses the primary power supply is configured with an active state [0013] [0014] [0020].
Regarding claim 9, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 8 above, YEH also discloses the second pin is configured to be associated with a voltage level that: is present at the second pin; and is readable by the power supply [0013] [0014] [0020].
Regarding claim 10, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 9 above, YEH also discloses the activity state is changed in response to a change in the voltage level present at the second pin [0013] [0014] [0020].
Regarding claim 11, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 10 above, YEH also discloses each of the two or more power supplies is configured to change corresponding activity state in response to both a current assignment and the voltage level at the second pin [0013] [0014] [0020].
Regarding claim 12, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 11 above, YEH also discloses the change in activity state is based on a predetermined operational configuration [0013] [0014] [0020].
Regarding claim 13, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 12 above, YEH also discloses the predetermined operational configuration is setup through one or more logic circuits [0013] [0014] [0020] (low and high indicate logic level; server and I/O ports are also indication of digital logic circuits).
Regarding claim 15, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 13 above, YEH also discloses the change in activity state occurs without a signal from a centralized control software [0013] [0014] [0020].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of YEH, OCHIAI and Landman in view of Riggio et al., US Patent Publication 20040012986; hereinafter “Riggio”.
Regarding claim 14, the combination of YEH, OCHIAI and Landman discloses the power supply system of claim 13 above, the combination of YEH, OCHIAI and Landman does not explicitly disclose the change in activity state occurs in less than 100 milliseconds. Riggio discloses a control signal in power supply system that change a state much less than 100 milliseconds [0202]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of YEH, OCHIAI and Landman to incorporate the teaching of Sarti and allow the change in activity state occurs in less than 100 milliseconds. Doing so would increase response time for the power supply system since the current state of the art in the logic control speed is much faster than millisecond and there is no reason to slow down the response time of the system.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAI H TRAN whose telephone number is (571)270-0668. The examiner can normally be reached M - F 8:30 - 5:00.
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/THAI H TRAN/Examiner, Art Unit 2836 /REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836