DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 2, 4 – 5, 7 – 10 and 12 – 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jones (US 2005/0189585).
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(Claim 1) Jones teaches a power semiconductor device comprising:
a first trench (228 left) recessed into a semiconductor layer in a first direction (top to bottom) from a surface of the semiconductor layer, and extending in a second direction (front to back) different from the first direction;
a source contact region (266/260 interface, paragraph 41) in contact with the surface of the semiconductor layer, and spaced apart from the first trench in the second direction;
a source region (260) in contact with the source contact region and one side of the first trench, and having first conductivity type (N) impurities;
a well region (220) in contact with a bottom surface and one side of the source region, and in contact with both sides and bottom surface of the first trench, and having second conductivity type (P) impurities;
a drift region (206) in contact with a bottom surface of the well region and having the first conductivity type (N) impurities; and
a junction resistance reduction region (232) disposed in the well region (220), and in contact with the drift region (206) and the bottom surface of the first trench (228), and having the first conductivity type (N) impurities.
(Claim 2) Jones teaches wherein the source contact region (266/260 interface) extends further along a third direction (left to right) perpendicular to the second direction (front to back).
(Claim 4) Jones teaches wherein the first direction (top to bottom) is perpendicular to the second direction (front to back).
(Claim 5) Jones teaches the power semiconductor device, further comprising (paragraph 41)
a drain region (204) disposed below the drift region (206) and having the first conductivity type (N) impurities.
(Claim 7) Jones teaches the power semiconductor device, further comprising:
a well contact region (264) penetrating the source region from the well region, and in contact with the surface of the semiconductor layer, and having the second conductivity type (P+) impurities.
(Claim 8) Jones teaches the power semiconductor device, further comprising:
a source electrode layer (266) in contact with each of the source contact region (266/260 interface) and the well contact region (264).
(Claim 9) Jones teaches a power semiconductor device comprising:
a plurality of trenches (228) recessed in a first direction (top to bottom) from a surface of a semiconductor layer into the semiconductor layer, and extending in a second direction (front to back) different from the first direction, the plurality of trenches being spaced apart from each other in a third direction (left to right);
a source region (260) disposed in the third direction between the plurality of trenches and having first conductivity type (N) impurities;
a well region (220) in contact with a bottom surface and one side of the source region (260), and in contact with both side and bottom surface of each of the plurality of trenches (228), and having second conductivity type (P) impurities;
a drift region (206) in contact with a bottom surface of the well region (220) and having the first conductivity type (N) impurities; and
a plurality of junction resistance reduction regions (232) disposed in the well region (220), disposed in contact with the bottom surface and the drift region of each of the plurality of trenches, being spaced apart from each other in the third direction, and having the first conductivity type (N) impurities.
(Claim 10) Jones teaches wherein the source region (260) is disposed from the surface of the semiconductor layer to a first depth, and
wherein the plurality of trenches (228) are disposed from the surface of the semiconductor layer to a second depth deeper than the first depth.
(Claim 12) Jones teaches wherein the second direction (front to back) is perpendicular to the first direction (top to bottom) and the third direction (left to right) is perpendicular to each of the first and the second directions, respectively.
(Claim 13) Jones teaches the power semiconductor device, further comprising (268 paragraph 41) a drain region (204) disposed below the drift region (206) and having the first conductivity type (N) impurities.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jones (US 2005/0189585) in view of Chun et al. (US 20180108774).
(Claim 3) Jones teaches the power semiconductor device, further comprising:
a first gate insulating layer (234, paragraph 21) disposed on an inner wall of the first trench; and
a first gate electrode layer (242, paragraph 20) disposed on the first gate insulating layer in the first trench.
Jones lacks the first gate electrode layer extending above the surface of the semiconductor layer, and covering at least a portion of the surface of the semiconductor layer.
However, Chun et al. teach the first gate electrode layer (fig. 2 #700) extending (702) above the surface of the semiconductor layer, and covering at least a portion of the surface of the semiconductor layer for the benefit of forming an all-around gate (paragraph 55).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of forming an all-around gate.
(Claim 6) Jones teaches the power semiconductor device, further comprising:
a second trench (232 right) recessed in the first direction into the semiconductor layer from the surface of the semiconductor layer, and extending in the second direction, and spaced apart from the source contact region in the second direction;
a second gate insulating layer (234) disposed on an inner wall of the second trench; and
a second gate electrode layer (242) disposed on the second gate insulating layer in the second trench.
Jones lacks the second gate electrode layer extending above the surface of the semiconductor layer, and covering at least a portion of the surface of the semiconductor layer.
However, Chun et al. teach the second gate electrode layer extending above the surface of the semiconductor layer, and covering at least a portion of the surface of the semiconductor layer for the benefit of forming an all-around gate (paragraph 55).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of forming an all-around gate.
(Claim 11) Jones teaches the power semiconductor device, further comprising:
a gate insulating layer (234) disposed on the surface of the semiconductor layer between an inner wall of each of the plurality of trenches; and
a gate electrode layer (242) disposed on the gate insulating layer in the trench.
Jones lacks a gate electrode layer extending above the surface of the semiconductor layer, and covering at least a portion of the surface of the semiconductor layer.
However, Chun et al. teach a gate electrode layer extending above the surface of the semiconductor layer, and covering at least a portion of the surface of the semiconductor layer for the benefit of forming an all-around gate (paragraph 55).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of forming an all-around gate
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
August 11, 2026
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