DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Gambini & Rabaey ("A 100KS/s 65dB DR Sigma-Delta ADC with 0.65V supply voltage", IEEE 2007) in view of Rueger et al. (US 7,298,308 B1).
Regarding Claim 1, Gambini teaches:
An integrator operating based on a variable current (Fig. 4, Page 203, Left Column, Section III disclosing a switched-capacitor integrator operating on variable/programmable bias current), comprising:
an operational amplifier (Fig. 4, Page 203, Left Column, Section III disclosing operational amplifiers/OTAs), comprising:
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Fig. 4 of Gambini reproduced for ease of reference.
an amplifying stage circuit, configured to provide an amplification gain (Fig. 4, Page 203, Left Column, Section III disclosing differential input pairs M1, M2 providing open-loop gain); and
a bias circuit, coupled to the amplifying stage circuit, configured to control a bias condition of the amplifying stage circuit according to the variable current output from a variable current source (Fig. 4, Page 203, Right Column, Section III disclosing an integrated PTAT/programmable bias circuit providing variable current via triode load M6 and current mirrors to the OTA);
wherein: in a sampling phase of the integrator, the variable current source switches the variable current to a sampling current value (Fig. 2, Fig. 5, Page 202, Right Column, Section II disclosing non-overlapping sampling phase φ1 and integration phase φ2 with dynamic/programmable current control);
in an integration phase of the integrator, the variable current source switches the variable current to an integration current value (Fig. 2, Fig. 5, Page 202, Right Column, Section II disclosing integration phase φ2 operating under variable bias current control).
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Fig. 5 of Gambini reproduced for ease of reference.
Gambini, however, does not explicitly disclose:
the sampling current value is less than the integration current value (i.e., explicitly reducing current during the sampling phase relative to the integration phase within the clock phase timing).
In the same field of endeavor (power-efficient delta-sigma modulator integrators), Rueger teaches controlling power consumption in an integrator by setting/switching bias currents dynamically (Figs. 4A–4C; Column 2, lines 30–53; Column 3, lines 12–25). Specifically, Rueger discloses adjusting and scaling operational amplifier bias current dynamically such that bias current is kept lower during lower-demand intervals to save power and boosted higher during high-demand settling intervals (Column 2, lines 44–53; Column 4, lines 10–25), thereby teaching reducing the bias current level during phase periods requiring less charging capability relative to integration/settling periods requiring fast transient response.
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Fig. 4C of Rueger reproduced for ease of reference.
It would have been obvious to a person having ordinary skill in the art (POSITA) before the effective filing date of the claimed invention to modify the variable bias control scheme of the switched-capacitor integrator in Gambini to switch the variable current source such that the sampling current value is less than the integration current value (Isampling < Iintegration), as taught by Rueger.
The motivation for incorporating Rueger's phase-dependent bias scaling into Gambini's switched-capacitor integrator is to significantly reduce overall power consumption without compromising performance. As taught by Rueger, reducing amplifier bias current during operational phases where full bandwidth/charging capability is not strictly required saves static power, while boosting current during the integration phase ensures fast settling and preserves system speed and dynamic range. Applying this optimization to Gambini's dynamic bias architecture yields the predictable result of lowering power dissipation during sampling phases while maintaining required settling accuracy during integration phases.
The modified combination of Gambini in view of Rueger thereby teaches all limitations of claim 1.
Regarding Claim 2: Gambini discloses an operational amplifier integrator circuit (Fig. 4) where bias voltages/currents generated by a self-referenced current mirror with programmable degeneration (PTAT bias circuit with M7–M10 / M5–M6) are used to control the bias conditions of the operational amplifier.
Rueger discloses using current mirrors driven by bias sources (e.g., DACs/switches) to generate internal bias control voltages/currents that control amplifier power and bias conditions (Figs. 4B, 4C, col. 4, lines 20–50).
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Fig. 4B of Rueger reproduced for ease of reference.
It would have been obvious to a person having ordinary skill in the art (POSITA) at the time of the invention to configure the bias circuit of Gambini using current mirror circuits (as taught by both Gambini and Rueger) to generate bias voltages corresponding to the variable bias current in order to efficiently scale operational amplifier bias conditions.
Regarding Claims 3 & 4: Gambini discloses a programmable bias current source adjusted by digital control signals (trimming bits B1–B5 controlling degenerated MOS loads/switches in Fig. 4).
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Fig. 4A of Rueger reproduced for ease of reference.
Rueger explicitly discloses a variable current source formed by a set of current sources/switches or selectable current mirrors controlled in sync with operating cycles to switch between different current ratios and values for an integrator amplifier (Fig. 4A, Fig. 4B, col. 3, line 10 to col. 4, line 25). Specifically, Rueger teaches switching different current mirrors/branches into a constant current path using switches turned on during distinct phase/sample control settings.
Combining Gambini's multi-phase operational amplifier integrator with Rueger's switched current mirror array to switch current ratios/values between sampling and integration phases would be obvious to a POSITA to achieve dynamic power savings.
Regarding Claims 5 & 6: The technique recited in Claims 5 and 6 describes a standard switched-capacitor / dynamic bias current mirror (sample-and-hold biasing), wherein a transistor is diode-connected via a switch in one phase to sample a reference current onto a gate capacitor, and subsequently disconnected in another phase to hold the control voltage and output a biased current.
Gambini utilizes switched-capacitor technology and sampling/integration phases φ1/ φ2).
Dynamic current-copier/switched-capacitor biasing techniques are well known in the art of low-power analog IC design (as demonstrated in low-power operational amplifier biasing schemes referenced in Rueger, col. 1, lines 40–44). It would be obvious to a POSITA to implement dynamic voltage-storage (switched-capacitor) biasing in Gambini's/Rueger's variable bias generator to reduce continuous power consumption during idle or sampling phases.
Regarding Claims 7 & 8: Claims 7 and 8 combine the dual-current/dual-mode switched current sources of Claims 3–4 with the dynamic voltage storage (switched-capacitor sample-and-hold biasing) of Claims 5–6.
Gambini teaches phase-controlled switched-capacitor integrator operational amplifiers. Rueger teaches adjusting integrator bias current between operational modes using multiple current source branches and switches.
Combining multiple constant reference sources with switched current-copier/current-mirror paths to separately control sampling and integration phase bias currents is a straightforward combination of known circuit elements (switched-capacitor current mirrors and multi-source bias generators) according to established rules to achieve predictable power reduction.
Regarding Claims 9 & 10: Gambini explicitly discloses that "The speed of the operational amplifiers can be programmed by changing their bias current, determined by a self-referenced current mirror with digitally trimmed triode MOS degeneration that provides a 31:1 ratio of maximum to minimum output current (Fig. 4); bias voltages are distributed directly in the voltage domain..." (Section III, page 203).
Scaled biasing proportional to operating clock frequency is a standard design principle: higher operating frequencies require higher bandwidth/slew rates (and thus higher integration bias current), whereas lower operating frequencies allow lower integration bias current to conserve power.
It would have been obvious to a POSITA to scale the integration phase bias current of Gambini's integrator based on the operating frequency (as explicitly taught by Gambini's programmable speed/current control), resulting in the second (higher) frequency selecting a second (higher) integration current value.
Conclusion
The prior art, Pavan (WO 2010/119456), Rueger (US 7,298,308), Sato (US 2008/0261542), US 7,068,024 (Huang), Laouej et al. (A Very Low Power Delta Sigma Modulator Using Optimized Bulk Driven Telescopic OTA for Biomedical Devices ©2020 IEEE), Li et al. (A Capacitive-Coupled Chopper Instrumental Amplifier Designed for Brain-Machine-Interface Circuits, EMIE 2022 / April 15-17, 2022 in Hangzhou, China) made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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