Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-11 rejected under 35 U.S.C. 103 as being unpatentable over Charpentier et al. (WO 2017070290 A1 and Charpentier hereinafter.) in view of Yamada et al. (US A1 and Yamada hereinafter.).
Regarding claim 1, Charpentier discloses a gate drive circuit for driving a plurality of power devices [fig. 1a, switches 102/108 in and 106/104 sharing nodes V+ and ground], comprising: a gate driving circuit [Ice monitoring circuit shown in fig. 5 with para. 35-36 disclosing the use of Ice monitoring with 2LTOff procedure] configured to generate a gate drive signal for each of the plurality of a power device [Ice monitoring circuits driving each transistor 102, 108, 106 and 104]; and a drive capability switching circuit [Ice monitoring circuit shown in fig. 5] configured to switch two-level turn-off (2LTOfff) with fig. 3 showing a 1st level turn off, second level turn off following full turn off of the associated power transistor], wherein the drive capability switching circuit is configured to set the gate drive capability to a first capability during a first period of the turn-off transition period [fig. 3 and para 23, 1st level turn off showing lower gate voltage 304 than gate full on], and to a second capability that is lower than the first capability during a second period of the turn-off transition period [2nd level turn off period showing a gate voltage] that is subsequent to the first period [2nd level turn off occurring after 1st level turn off], wherein the first period corresponds to a period for passing through a region in which a drain current of the plurality of power devices fluctuates due to a self-excited oscillation between the plurality of power devices in order to suppress the self-excited oscillation [para. 23 and fig. 3, Ic oscillating during 1st and 2nd level turn off period and stopping at full turn off], and wherein the second period corresponds to a period for suppressing a surge voltage of the plurality of power devices [para. 23 describing spike and ring suppression].
Charpentier does not explicitly disclose the plurality of power devices connected in parallel
However, Yamada discloses the plurality of power devices connected in parallel [fig. 2 showing power devices 11a and 110b connected in parallel].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Charpentier to include the plurality of parallel connected power devices as taught by Yamada to improve parallel switching circuit timing performance.
Regarding claim 2, Charpentier in view of Yamada discloses further wherein the drive capability switching circuit includes a comparator [Charpentier, 512] configured to compare an inter-terminal voltage between main terminals of the power device [Charpentier, voltage from 508 onto a first input of 512] with a predetermined threshold voltage [Charpentier, voltage from 502 onto a second input of 512], so as to generate a comparison signal, and a switch configured to switch the gate drive capability according to the comparison signal [Charpentier, 502 turning off or on 508 with a switching signal].
Regarding claim 3, Charpentier does not explicitly disclose wherein the threshold voltage is a variable value.
However, Charpentier shows [fig. 5] MCU 502 placing a threshold onto comparator 512 with the comparator comparing an incoming voltage from Sic FET 508 with this threshold in the prevention of damaging voltages of a switching device[para. 6 and 35 of Charpentier].
Therefore, it would be obvious to one skilled in the art before the effective filing date to have the incoming threshold voltage as taught by Charpentier to be adjustable so as to improve dynamic capabilities in prevention of damaging FET devices by having differing threshold voltages.
Furthermore, applicant has disclosed in claim 2 this voltage as predetermined, suggesting this voltage is not adjustable.
Regarding claim 5, Charpentier in view of Yamada discloses further wherein the drive capability switching circuit includes a timer [Charpentier, fig. 5, MCU 502] configured to generate a timer signal that changes its logic level when a predetermined time has elapsed after at least one of turn-off timing and turn-on timing of the power device [Charpentier, fig. 8 and para. 28], and a switch configured to switch the gate drive capability according to the timer signal [Charpentier, output of 502 wherein 502 acts as a switching output].
Regarding claim 6, Charpentier in view of Yamada discloses further wherein the drive capability switching circuit further includes a gate resistor [Charpentier, inherent high gate impedance of FET], so that the switch switches a resistance value of the gate resistor [Charpentier, gate voltage applied to gate impedance reaches a turn on voltage thereyby turning on 508].
Regarding claim 7, Charpentier in view of Yamada discloses further wherein the drive capability switching circuit further includes a gate capacitance [Charpentier, inherent gate capacitance of 508], so that the switch switches between connection and disconnection of the gate capacitance [Charpentier, gate switched to ground].
Regarding claim 8, Charpentier in view of Yamada discloses further wherein the drive capability switching circuit further includes a DC voltage source configured to generate a negative potential lower than a reference potential [ground], so that the switch switches an off potential of the gate drive signal between the negative potential and the reference potential [Charpentier, gate of 508 applied to ground thereby switching 508].
Regarding claim 9, Charpentier in view of Yamada discloses further wherein the drive capability switching circuit decreases the gate drive capability from a first gate drive capability [Charpentier, FET 508 off] to a second gate drive [Charpentier, FET 508 on] capability during at least one of the turn-off transition period and the turn-on transition period of the power device [Charpentier, para. 35], and afterward increases the same from the second gate drive capability to the first gate drive capability again [Charpentier, FET 508 going from on to off].
Regarding claim 10, Charpentier in view of Yamada discloses an electric power conversion device comprising: a power module configured to include at least one said power device [Charpentier, FET 508]; and the gate drive circuit [Charpentier, opamp 504] according to claim 1 [Charpentier, as shown in fig. 5].
Regarding claim 11, Charpentier in view of Yamada discloses further wherein the power module includes a plurality of the power devices connected in parallel to each other [110a and 110b connected in parallel as shown in fig. 2 of Yamada].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Charpentier in view of Yamada further in view of Mednik et al. (US 10778080 B1 and Mednik hereinafter.) further in view of "5183" (CN 111835183 A and “5183” hereinafter.).
Regarding claim 4, Charpentier in view of Yamada discloses further wherein the drive capability switching circuit includes a comparator [Charpentier, 512] configured to compare an inter-terminal voltage between a control terminal and a main terminal [inter-terminal voltage between Vce and ground] of the power device with a predetermined threshold voltage [Charpentier, comparator voltage on 512 from 502], so as to generate the comparison signal [Charpentier, output of comparator]. Charpentier in view of Yamada does not explicitly disclose a latch configured to receive input of the comparison signal so as to generate a latch signal, and a switch configured to switch the gate drive capability according to the latch signal.
However, Mednik discloses [fig. 7] a latch [130] configured to receive input of the comparison signal [output of 131] so as to generate a latch signal.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the invention as described by Charpentier in view of Yamada to include the latch and switch as taught by Mednik to improve high switching frequency performance in a switching circuit.
Charpentier in view of Yamada further in view of Mednik does not explicitly disclose a switch configured to switch the gate drive capability according to the latch signal.
However, “5183” discloses [fig. 3] a switch [Q1] configured to switch the gate drive capability [drive signal on gate of 140] according to the latch signal [122 controlling Q1].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the invention as described by Charpentier in view of Yamada in view of Mednik to include the switch and latch signal as taught by "5183" to improve switching circuit performance by reducing high frequency noises and unwanted glitches.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Charpentier in view of Yamada further in view of Yasako et al. (US 20190296653 A1 and Yasako hereinafter.).
Regarding claim 12, Charpentier in view of Yamada discloses all the features regarding claim 11 as indicated above. Charpentier in view of Yamada does not explicitly disclose the electric power conversion device further comprising an external control terminal electrically connected to control terminals of the plurality of power devices, wherein control wiring lengths, which are connection path lengths between the external control terminal and the control terminals of the plurality of power devices, are different from each other.
However, Asako discloses the electric power conversion device further comprising an external control terminal electrically connected to control terminals of the plurality of power devices [fig. 5], wherein control wiring lengths, which are connection path lengths between the external control terminal and the control terminals of the plurality of power devices, are different from each other [para. 8 and 96-100]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Charpentier in view of Yamada to include the external control terminal connected to control terminals of the plurality of power devices and the differing control wiring lengths as taught by Yasako to improve a switching circuits performance by suppressing unwanted voltage differences from occurring between switching elements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, Otake (US-10320380-B2) is cited to teach a gate driving circuit.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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