DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 14-16, 18, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. (US 11,444,612 B2), hereinafter Agarwal, in view of Wang (US 6,064,262).
Regarding claim 1, Agarwal discloses, in figure 1, a circuit, comprising:
first and second input terminals configured to collectively receive a differential input signal (Col. 3, Lines 22-23, “differentially receive input signals, such as a positive input signal (INP) and a negative input signal (INM)”);
first and second output terminals (1st_stage_out_minus and 1st_stage_out_plus);
first and second transistors having respective first terminals (transistor Q1 & Q2), respective second terminals (source of Q1 & Q2), and respective third terminal (drain of Q1 & Q2), the first terminals respectively coupled to the first and second input terminals (gate of Q1 coupled to INP and gate of Q2 coupled to INM);
third and fourth transistors having respective first terminals (transistors Q3 & Q4), respective second terminals (source of Q3 & Q4), respective third terminals (drain of Q3 & Q4), and respective bodies (bodies of Q3 & Q4), the first terminals respectively coupled to the respective second terminals of the first and second transistors (gates of transistors Q3 & Q4 are coupled to the source of Q1 & Q2 via R1 & R2, respectively), the third terminals respectively coupled to the first and second output terminals (drain of Q3 & Q4 are coupled to the output terminals, 1st_stage_out_minus and 1st_stage_out_plus, via the source of Q3 & Q4, respectively), but fails to disclose the bodies respectively coupled to a first body interface; and
a body bias controller configured to provide a first body voltage to the first body interface based on a common mode voltage of the differential input signal.
However, Wang discloses, in figure 2 & 3, the bodies of the third and fourth transistors respectively coupled to a first body interface (bodies of transistors Q1 & Q2 coupled to body interface VREF); and
a body bias controller configured to provide a first body voltage to the first body interface based on a common mode voltage of the differential input signal (Col. 3, Lines 45-50, “The voltage controller 150 is typically a feedback circuit that measures the differential output voltage and common mode voltage for particular input signal values, and then adjusts the signals applied to the backgate terminals [i.e., bodies of Q1 & Q2] to yield the desired differential output and common mode voltage values”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the body bias controller of Wang in the circuit of Agarwal, to achieve the benefit of providing additional gain to the amplifier circuit while eliminating unintended characteristic variations between the transistors (Wang, Col. 3, Lines 23-41).
Regarding claim 14, Agarwal in view of Wang disclose the circuit of claim 1, and Agarwal continues to disclose, in figure 2, wherein the first and second transistors are n-channel field-effect transistors (Col. 3, Lines 1-6, “input transistor pair [i.e., Q1 & Q2] can comprise P-type metal-oxide-semiconductor transistors…in other examples, transistors Q1 & Q2 are different types of transistors [i.e., n-type]”), and the first, second, and third terminals of the first and second transistors are respective gate, source, and drain terminals of the first and second transistors (transistors Q1 & Q2 have respective gate, source, and drain terminals as the first, second, and third terminals), and wherein the third and fourth transistors are p-channel field-effect transistors (Col. 3, Lines 7-17, “current mirror includes NMOS (N-type metal-oxide-semiconductor) transistors Q3 and Q4…In other examples, transistors Q3 and Q4 are different types of transistors [i.e., p-type]”), and the first, second, and third terminals of the third and fourth transistors are respective gate, source, and drain terminals of the third and fourth transistors (transistors Q3 & Q4 have respective gate, source, and drain terminals as the first, second, and third terminals).
Regarding claim 15, Agarwal discloses, in figure 1, a circuit, comprising:
first and second input terminals configured to collectively receive a differential input signal (Col. 3, Lines 22-23, “differentially receive input signals, such as a positive input signal (INP) and a negative input signal (INM)”);
first and second output terminals (1st_stage_out_minus and 1st_stage_out_plus);
first and second transistors having respective first terminals (transistor Q1 & Q2), respective second terminals (source of Q1 & Q2), and respective third terminal (drain of Q1 & Q2), the first terminals respectively coupled to the first and second input terminals (gate of Q1 coupled to INP and gate of Q2 coupled to INM);
third and fourth transistors having respective first terminals (transistors Q3 & Q4), respective second terminals (source of Q3 & Q4), respective third terminals (drain of Q3 & Q4), and respective bodies (bodies of Q3 & Q4), the first terminals respectively coupled to the respective second terminals of the first and second transistors (gates of transistors Q3 & Q4 are coupled to the source of Q1 & Q2 via R1 & R2, respectively), the third terminals respectively coupled to the first and second output terminals (drain of Q3 & Q4 are coupled to the output terminals, 1st_stage_out_minus and 1st_stage_out_plus, via the source of Q3 & Q4, respectively), but fails to disclose the bodies respectively coupled to a first body interface; and
a body bias controller configured to provide a body voltage to the first body interface.
However, Wang discloses, in figure 2 & 3, the bodies of the third and fourth transistors respectively coupled to a first body interface (bodies of transistors Q1 & Q2 coupled to body interface VREF); and
a body bias controller configured to provide a body voltage to the first body interface (Col. 3, Lines 45-50, “The voltage controller 150 is typically a feedback circuit that measures the differential output voltage and common mode voltage for particular input signal values, and then adjusts the signals applied to the backgate terminals [i.e., bodies of Q1 & Q2] to yield the desired differential output and common mode voltage values”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the body bias controller of Wang in the circuit of Agarwal, to achieve the benefit of providing additional gain to the amplifier circuit while eliminating unintended characteristic variations between the transistors (Wang, Col. 3, Lines 23-41).
Regarding claim 16, Agarwal in view of Wang disclose the circuit of claim 15, and Wang continues to disclose, in figure 2 & 3, wherein the body bias controller is further configured to control the body voltage based on a common mode voltage of the differential input signal (Col. 3, Lines 45-50, “The voltage controller 150 is typically a feedback circuit that measures the differential output voltage and common mode voltage for particular input signal values, and then adjusts the signals applied to the backgate terminals [i.e., bodies of Q1 & Q2] to yield the desired differential output and common mode voltage values”).
Regarding claim 18, Agarwal in view of Wang disclose the circuit of claim 15, and Agarwal continues to disclose, in figure 2, wherein the first and second transistors are n-channel field-effect transistors (Col. 3, Lines 1-6, “input transistor pair [i.e., Q1 & Q2] can comprise P-type metal-oxide-semiconductor transistors…in other examples, transistors Q1 & Q2 are different types of transistors [i.e., n-type]”), and the first, second, and third terminals of the first and second transistors are respective gate, source, and drain terminals of the first and second transistors (transistors Q1 & Q2 have respective gate, source, and drain terminals as the first, second, and third terminals), and wherein the third and fourth transistors are p-channel field-effect transistors (Col. 3, Lines 7-17, “current mirror includes NMOS (N-type metal-oxide-semiconductor) transistors Q3 and Q4…In other examples, transistors Q3 and Q4 are different types of transistors [i.e., p-type]”), and the first, second, and third terminals of the third and fourth transistors are respective gate, source, and drain terminals of the third and fourth transistors (transistors Q3 & Q4 have respective gate, source, and drain terminals as the first, second, and third terminals).
Regarding claim 20, Agarwal in view of Wang disclose the circuit of claim 15, and Agarwal continues to disclose, in figure 2, wherein the first and second transistors are n-channel field-effect transistors (Col. 3, Lines 1-4, “input transistor pair [i.e., Q1 & Q2] can comprise P-type metal-oxide-semiconductor transistors”), and the first, second, and third terminals of the first and second transistors are respective gate, source, and drain terminals of the first and second transistors (transistors Q1 & Q2 have respective gate, source, and drain terminals as the first, second, and third terminals), and wherein the third and fourth transistors are p-channel field-effect transistors (Col. 3, Lines 7-17, “current mirror includes NMOS (N-type metal-oxide-semiconductor) transistors Q3 and Q4…In other examples, transistors Q3 and Q4 are different types of transistors [i.e., p-type]”), and the first, second, and third terminals of the third and fourth transistors are respective gate, source, and drain terminals of the third and fourth transistors (transistors Q3 & Q4 have respective gate, source, and drain terminals as the first, second, and third terminals).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Agarwal in view of Wang as applied to claims 1, 14-16, 18, & 20 above, and further in view of Mustafi et al. (US 11,405,030 B1), hereinafter Mustafi.
Regarding claim 12, Agarwal in view of Wang discloses the circuit of claim 1, but fails to disclose sixteenth and seventeenth transistors having respective first terminals, respective second terminals, and respective third terminals, the first terminals respectively coupled to a clamp voltage, the second terminals respectively coupled to the respective first terminals of the third and fourth transistors.
However, Mustafi discloses, in figure 2, sixteenth and seventeenth transistors having respective first terminals (transistors 258 & 256), respective second terminals (drains of 258 & 256), and respective third terminals (source of 258 & 256), the first terminals respectively coupled to a clamp voltage (gate of transistors 258 & 256 is coupled to clamp voltage, Vclamp), the second terminals respectively coupled to the respective first terminals of the third and fourth transistors (drain of 258 is coupled to the gate of 208 via current path 206 to resistor 252, across transistor 250 to ground, through current source 230 and capacitor 232. The drain of transistor 256 is coupled to the gate of 214 via resistor 252, transistor 250, ground, current source 240, and capacitor 242. See figure 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the transistors of Mustafi in the circuit of Agarwal and Wang, to achieve the benefit of clamping the transistors to below a voltage threshold thereby protecting the circuit over voltage stress (Mustafi, Col. 4 & 5, Lines 51-67 & 1-11).
Allowable Subject Matter
Claims 2-11, 13, 17, & 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TYLER J PERENY/ Examiner, Art Unit 2842
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