DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation "the first body interface" in lines 11-12. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted “the first body interface” to read “the body interface”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. (US 11,444,612 B2), hereinafter Agarwal, in view of Wang (US 6,064,262), and further in view of Ivanov et al. (US 2021/0242844 A1), hereinafter Ivanov.
Regarding claim 21, as best understood based on the 35 U.S.C. 112(b) rejection made above, Agarwal discloses, in figure 1, a circuit, comprising:
first and second input terminals configured to collectively receive a differential input signal (Col. 3, Lines 22-23, “differentially receive input signals, such as a positive input signal (INP) and a negative input signal (INM)”);
first and second output terminals (1st_stage_out_minus and 1st_stage_out_plus);
first and second transistors having respective first terminals (transistor Q1 & Q2), respective second terminals (source of Q1 & Q2), and respective third terminal (drain of Q1 & Q2), the first terminals respectively coupled to the first and second input terminals (gate of Q1 coupled to INP and gate of Q2 coupled to INM);
third and fourth transistors having respective first terminals (transistors Q3 & Q4), respective second terminals (source of Q3 & Q4), respective third terminals (drain of Q3 & Q4), and respective bodies (bodies of Q3 & Q4), the first terminals respectively coupled to the respective second terminals of the first and second transistors (gates of transistors Q3 & Q4 are coupled to the source of Q1 & Q2 via R1 & R2, respectively), the third terminals respectively coupled to the first and second output terminals (drain of Q3 & Q4 are coupled to the output terminals, 1st_stage_out_minus and 1st_stage_out_plus, via the source of Q3 & Q4, respectively), but fails to disclose the bodies respectively coupled to a body interface; and
a body bias controller configured to provide a body voltage to the body interface, the body bias controller comprising a current source coupled to the body interface.
However, Wang discloses, in figure 2 & 3, the bodies of the third and fourth transistors respectively coupled to a body interface (bodies of transistors Q1 & Q2 coupled to body interface VREF); and
a body bias controller configured to provide a first body voltage to the body interface (Col. 3, Lines 45-50, “The voltage controller 150 is typically a feedback circuit that measures the differential output voltage and common mode voltage for particular input signal values, and then adjusts the signals applied to the backgate terminals [i.e., bodies of Q1 & Q2] to yield the desired differential output and common mode voltage values”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the body bias controller of Wang in the circuit of Agarwal, to achieve the benefit of providing additional gain to the amplifier circuit while eliminating unintended characteristic variations between the transistors (Wang, Col. 3, Lines 23-41).
In combination, Agarwal and Wang fail to disclose the body bias controller comprising a current source coupled to the body interface.
However, Ivanov discloses, in figure 4, the body bias controller comprising a current source coupled to the body interface (Para [0031], “voltage at V.sub.bdy terminal 460 is generated by injecting current from I.sub.bdy current source 464 through resistor 462”…current source 464 coupled to the body interface 460).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the current source of Ivanov in the body bias controller of Agarwal and Wang, to achieve the benefit of supporting a common mode voltage range outside the upper and lower rail voltages while employing the “body effect” to increase the threshold voltages of the interfaced transistors (Ivanov, Para [0023], [0032] & [0034]).
Allowable Subject Matter
Claims 1 & 3-20 are allowed.
Claim 1 is allowed because none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
seventh and eighth transistors having respective first terminals, respective second terminals, respective third terminals, and respective bodies, the first terminals respectively coupled to the respective second terminals of the fifth and sixth transistors, the third terminals respectively coupled to the first and second output terminals, and the bodies respectively coupled to a second body interface, wherein the body bias controller is further configured to provide a second body voltage to the second body interface based on the common mode voltage of the differential input signal.
Claim 15 is allowed because none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
wherein the body bias controller comprising a current mirror circuit coupled to the body interface, the current mirror circuit configured to provide a current based on a first current through the first transistor and a second current through the second transistor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mustafi et al. (US 11,405,030 B1) [Figure 2. Discloses a comparator having: a first transistor coupled to a first input terminal; a first current source coupled to the first transistor; a second transistor coupled to a second input terminal and coupled to the first current source; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the second transistor; a fifth transistor coupled in series with the first transistor; a sixth transistor coupled in series with the second transistor; a seventh transistor coupled to the first input terminal and coupled as a source follower to the fifth transistor; and an eighth transistor coupled to the second input terminal and coupled as a source follower to the sixth transistor. The comparator also including a differential amplifier coupled to the first output terminal and coupled to the second output terminal.]
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571) 272-4189. The examiner can normally be reached M-F 7:30-5.
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/TYLER J PERENY/Examiner, Art Unit 2836
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