Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-18 are presented for examination.
Title
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-6 and 8-17 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-3, 6 and 8-13 of U.S. Patent No. 12080357. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-6 and 8 of the examined application are anticipated and the same scope of invention by claims 1-3 and 6of the reference such as a memory device comprising: a memory block connected to a plurality of word lines; a peripheral circuit configured to perform a program operation, including a plurality of program loops, on memory cells that are connected to a selected word line among the plurality of word lines, and configured to apply a program voltage to the selected word line and a pass voltage to an unselected word line among the plurality of word lines in each of the plurality of program loops; and a control logic configured to, while a level of the program voltage being applied to the selected word line is maintained in a program loop among the plurality of program loops, control the peripheral circuit to switch the pass voltage from a first voltage level to a second voltage level different from the first voltage level.
6. Claims 9-14 of the examined application are anticipated and the same scope of invention by claims 8-10 of the reference such as a memory device comprising: a memory block connected to a plurality of word lines including a selected word line and an unselected word line; a peripheral circuit configured to perform a program operation, including a plurality of program loops, on memory cells that are connected to the selected word line; and a control logic configured to control the peripheral circuit to apply a program voltage to the selected word line and a pass voltage to the unselected word line with multiple time periods including a first, a second and a third time periods in order in a program loop among the plurality of program loops, wherein the control logic controls the peripheral circuit to: during the first time period, apply the pass voltage having a first voltage level to the selected word line and the unselected word line, during the second time period, apply the program voltage to the selected word line and maintaining the first voltage level of the pass voltage applied to the unselected word line, and during the third time period, apply the pass voltage having a second voltage, different from the first voltage level, to the unselected word line and maintain a voltage level of the program voltage applied to the selected word line.
7. Claims 15-17 of the examined application are anticipated and the same scope of invention by claims 11-13 of the reference such as a method of operating a memory device performing a program operation including a plurality of program loops on memory cells that are connected to a selected word line among a plurality of word lines, the method comprising: applying a program voltage to the selected word line; and applying a pass voltage to an adjacent word line that is adjacent to the selected word line while the program voltage is applied to the selected word line, wherein the applying the pass voltage comprises: switching the pass voltage from a first voltage level to a second voltage level higher than the first voltage level while maintaining a voltage level of the program voltage being applied to the selected word line.
The claims 7 and 18 of examined application are obvious over the claims of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites wherein the pass voltage having the first voltage level is applied to the selected word line before the program voltage is applied while in the reference claimed a program voltage applied to a selected word line. However, Fig. 3 of Shin et al. Pub. No. 20090040833 discloses the pass voltage (Vpass) having the first voltage level (Vpass) is applied to the selected word line WLi before the program voltage (Vpgm).
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-8 and 15-18 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Shin et al. Pub. No. 20090040833.
As per claims 1-3, 6 and 15, Fig. 2 of Shin is directed to a memory device comprising: a memory block (110) connected to a plurality of word lines (WL0-WLn-1) ; a peripheral circuit (120-140) configured to perform a program operation (Fig. 3), including a plurality of program loops (Fig. 5), on memory cells that are connected to a selected word line (WLi, Fig. 3) among the plurality of word lines, and configured to apply a program voltage (Vpgm) to the selected word line and a pass voltage (Vpass) to an unselected word line (WL i-1) among the plurality of word lines in each of the plurality of program loops; and a control logic (150) configured to, while a level of the program voltage being applied to the selected word line is maintained in a program loop among the plurality of program loops, control the peripheral circuit to switch the pass voltage from a first voltage level (Vpass) to a second voltage (Vpass+) level different from the first voltage level.
As per claim 4, Fig. 4 of Shin discloses wherein an application time of the second voltage level of the pass voltage in a first program loop is longer than that of a second program loop following the first program loop.
As per claim 5, Fig. 4 of Shin discloses wherein a sum of an application time of the first voltage level of the pass voltage and an application time of the second voltage level of the pass voltage is constant in the plurality of program loops.
As per claim 7, Fig. 3 of Shin discloses wherein the pass voltage having the first voltage level is applied to the selected word line before the program voltage is applied.
As per claim 8, Fig. 4 and a paragraph 47 of Shin disclose wherein an application time of the second voltage level of the pass voltage increases as the plurality of program loops proceed.
As per claim 16, Fig. 4 of Shin discloses wherein a time point of the switching is adjusted as the plurality of program loops proceed (loop#1 to loop #K).
As per claim 17, Fig. 4 of Shin discloses wherein the time point of the switching becomes earlier as the plurality of program loops proceed (if less programming a few loops).
As per claim 18, Fig. 3 of Shin discloses wherein, before applying the program voltage to the selected word line, the pass voltage having the first voltage level is applied to the selected word line and the adjacent word line.
11. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
12. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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