Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the claimed listing filed on 08/05/2024.
Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US12056352B2 (In Applicant’s IDS submission, ‘Gasparakis’, receipt date 11/05/2024)
As per claim 1: See the comparing limitations in the table below:
Current Application
US. Pat. US12056352B2 (App. US17/955,286)
1. A processor configured to:
generate data storage information that describes, for a first stage of a data processing pipeline, that data output by the first stage of the data processing pipeline is processed as input data by a second stage of the data processing pipeline; and
generate one or more optimization instructions for the data processing pipeline that cause the data output by the first stage of the data processing pipeline to be removed from a first memory location after the data is input to the second stage.
2. The processor of claim 1, wherein the one or more optimization instructions include at least one instruction that causes the data to be discarded from memory based on the data being processed as input data by the second stage and not by any other stage of the data processing pipeline
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3. The processor of claim 1, wherein the one or more optimization instructions include at least one instruction that causes the data to be evicted from the first memory location and written to a second memory location based on the data being processed as input data by the second stage and a third stage of the data processing pipeline.
5. The processor of claim 3, wherein the one or more optimization instructions include the at least one instruction based on a threshold duration separating the second stage of the data processing pipeline and the third stage of the data processing pipeline
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4. The processor of claim 3, wherein the first memory location is prioritized for search over the second memory location by a data retrieval procedure of an additional processor implementing the data processing pipeline.
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6. The processor of claim 3, wherein the one or more optimization instructions include the at least one instruction based on memory requirements of the data processing pipeline indicating that an available capacity of the first memory location will be exceeded during execution of the data processing pipeline between the second stage and the third stage.
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7. The processor of claim 3, wherein the one or more optimization instructions include at least one additional instruction that causes the data to be retrieved from the second memory location at a time that occurs before the third stage of the data processing pipeline is executed.
8. The processor of claim 7, wherein the at least one additional instruction causes the data to be retrieved from the second memory location and placed in the first memory location that is accessed first by a data retrieval procedure of an additional processor implementing the data processing pipeline.
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9. The processor of claim 7, wherein the time that occurs before the third stage is a fourth stage of the data processing pipeline associated with at least one of a memory usage that is below a memory usage threshold, and a compute usage that exceeds a compute usage threshold.
1. A method comprising:
computing, for each of a plurality of stages of a data processing pipeline, resource usage information that describes a memory usage and a compute usage of the data processing pipeline stage;
generating data storage information that describes, for each of the plurality of stages of the data processing pipeline, whether data output by the data processing pipeline stage is processed as input data by another one of the plurality of stages of the data processing pipeline; and
generating optimization instructions for the data processing pipeline based on the resource usage information and the data storage information, the optimization instructions including an instruction that causes data output by a first one of the plurality of stages
to be discarded from memory after the data output by the first one of the plurality of stages is input to a second one of the plurality of stages.
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15. The method of claim 1, wherein the instruction that causes data output by the first one of the plurality of stages to be discarded from memory after the data output by the first one of the plurality of stages is input to the second one of the plurality of stages instructs the data output by the first one of the plurality of stages to be maintained in memory until accessed by a threshold number of the plurality of stages, wherein the second one of the plurality of stages comprises a least one of the threshold number of the plurality of stages during execution of the data processing pipeline.
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10. The method of claim 1, wherein the optimization instructions further include an instruction that causes data output by the second one of the plurality of stages to be evicted from a first memory location and written to a second memory location in response to detecting that the data output by the second one of the plurality of stages is used as input data for a third one of the plurality of stages and a threshold duration separates the second one of the plurality of stages and the third one of the plurality of stages during execution of the data processing pipeline
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11. The method of claim 10, wherein the first memory location is prioritized for search by a data retrieval procedure of a processor implementing the data processing pipeline over the second memory location.
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The method of claim 1, wherein the data processing pipeline is being executed by at least one processor and the compute usage for each of the plurality of stages of the data processing pipeline is a percentage value specifying an available processing capacity of the at least one processor during the data processing pipeline stage.
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12. The method of claim 10, wherein the optimization instructions further include an instruction that causes the data output by the second one of the plurality of stages to be retrieved from the second memory location at a time that occurs before executing the third one of the plurality of stages of the data processing pipeline.
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14. The method of claim 12, wherein the time that occurs before executing the third one of the plurality of stages of the data processing pipeline corresponds to one of the plurality of stages of the data processing pipeline having associated resource usage information indicating that the compute usage of the data processing pipeline stage satisfies a compute usage threshold.
- Current Claims 1-9 of the Application are directed to a processor.
- Current Claims 10-16 and 17-20 of the Application are directed to a processor and a system, respectively.
- Claims 10-16 and 17–20 recite the limitations corresponding to the processor of current claims 1-9, and would be compared in the same manner as above to the method of the US patent.
The Claims in the current Application recite to extend the claimed functionality of the method in the US patent to processors and a system. From the table above, the features in the current claims are rearranged in comparison to the limitations in the claims of the US patent. Although the claims at issue are not identical, they are not patentable distinct from each other.
Therefore, it would be obvious to one of the ordinary skills in the art before the effective filing of the invention to modify current claims (as seen in the compared table above) from the US patent claims for extending coverage.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 10-11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Taher et al., US Pat. 11500673 B2 (Applicant’s IDS submission, receipt date 11/05/2024), in view Viglas et al., "Maximizing the Output Rate of Multi-Way Join Queries over Streaming Information Sources", 2003, Proceedings of the 29th VLDB Conference, Berlin, Germany, 12 pages.
As per Claim 1: Taher discloses the limitations as below:
1. A processor configured to:
generate data storage information that describes, for a first stage of a data processing pipeline, that data output by the first stage of the data processing pipeline is processed as input data by a second stage of the data processing pipeline;
(See Abstract: “The method identifies one
or more tasks to be executed from defined tasks that are defined declaratively as a number of stages of input data ,
data transformations , and output data .”)
and
generate one or more optimization instructions for the data processing pipeline
(See Abstract: “A method for dynamically generating an optimized processing pipeline for tasks is provided.”. See col., 3, lines 36-41, “… able to collate multiple tasks into a single pipeline and optimize the pipeline stages in real time. This optimization consists of removing tasks that are
not required by the users, and de-duplication of common stages of data transformation between tasks. This provides an inherent performance benefit.”: “This optimization consists of removing tasks” reads on optimization instructions)
Taher does not explicitly disclose,
“that cause the data output by the first stage of the data processing pipeline to be removed from a first memory location after the data is input to the second stage.”
Viglas discloses,
“that cause the data output by the first stage of the data processing pipeline to be removed from a first memory location after the data is input to the second stage.”
(See in p. 1, in sec. Instruction, “pipelined join operator”. See p. 12, left col., “T(1) =……
From this size, however, we have to discard the inputs handled during the first second of execution
since these have been already propagated. After the first second, the contribution of the next second to the output becomes T(2) =……”)
Viglas mentions discarding the inputs handled during the first second of execution since these have been already propagated. The inputs handled reads on the optimized instruction being removed.
Moreover, Taher discusses removing tasks that are not required by user suggested that the code that is no longer needed is recognized by user, while Viglas mentions that code is no longer needed, and in the technological art, the removal would benefit the performance.
Therefore, it would be obvious to an ordinary of skills in the art before the effectiveness of the application to combine generating optimized instruction ‘tasks’ by Taher and discarding the input handling after transmitting arrival in the second stage of the teaching of Viglas.
The combination would yield predictable results because they are unused instructions, and discarding is for performance benefits such as free memory.
As per Claim 2: Incorporated with claim 1 above, Taher and combining Viglas, where
Taher discloses, “The processor of claim 1, wherein the one or more optimization instructions include at least one instruction that causes the data to be discarded from memory”
(Taher: See col., 3, lines 36-41)
And Viglas discloses,
“ based on the data being processed as input data by the second stage and not by any other stage of the data processing pipeline.”
(Viglas: See p. 12, left col., “T(1) =……
From this size, however, we have to discard the inputs handled during the first second of execution
since these have been already propagated. After the first second, the contribution of the next second to the output becomes T(2) =……”)
Therefore, it would be obvious to an ordinary of skills in the art before the effectiveness of the application to further combine generating optimized instruction ‘tasks’ by Taher and discarding the input handling after transmitting arrival in the second stage of the teaching of Viglas.
The combination would yield predictable results because they are unused instructions, and discarding is for performance benefits such as free memory.
As per Claims 10-11: Claims 10-11 recite a processor, where the claims recite the claimed limitations having claimed functionality corresponding to Claims 1-2. The rejection of the claims would be with the rationales addressed in the rejection of the method claims 1-2.
As per Claims 17-18: Claims 17-18 recite a system, where the claims recite the claimed limitations having claimed functionality corresponding to Claims 1-2. The rejection of the claims would be with the rationales addressed in the rejection of the method claims 1-2.
As per Claim 19: Incorporating the limitations of claim 17, Taher and combining Viglas, where Taher further discloses
19. The system of claim 17, wherein the memory system is configured to
transfer the data from the first memory location to a second memory location based on the data being processed as input data by the second stage and a third stage of the data
processing pipeline.
(See Taher Fig. 4c, where Task 1, 420, Task 2 430, and read as ‘the data being processed as input data’, and “stage 2, stage 4, stage 5 (read as second stage, and second memory location) and “stage 6, stage 7, stage 8 (read third stage, and third memory location))
Allowable Subject Matter
Claims 3-9, 12-16, and 20 are objected to under applying prior arts but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In the office action, the claims are rejected under double patenting that requires filing terminal disclaim approved by the TC.
Conclusion
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TTV
July 22, 2026
/Ted T. Vo/
Primary Examiner, Art Unit 2191
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