DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 03/23/2026. Claims 3, 9, and 15 were canceled. 1-2, 4-8, 10-14 and 16-20 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-8, 10-14 and 16-20 have been considered but are moot in view of the current rejection.
A new reference Huang et al. US 2017/0277471 is cited in this Office Action necessitated by the amendment.
Applicant argues regarding independent claim 7, page 4 of the remarks, “Gorobets discloses a decision step in Fig. 9A (step 197) that tests whether any deferred scrubs remain before ending processing, but it does not frame this as checking a list in response to a ‘maintenance command.’”
The Examiner respectfully disagrees. “Two entry points to the processing are shown in FIG. 9, at 115 when a scrub trigger event is detected and at 117 when a command to execute deferred scrubs is received.” Paragraph [0168] of Gorobets. In the step 115, the memory is monitored for a scrub trigger event, para 0169 of Gorobets. At step 117, a command to execute deferred scrubs is received. Therefore, the checking is done in response to receiving a command to execute scrub operations.
Applicant argues regarding independent claim 13, “Halbert … nowhere teaches, for example, that any register itself indicates when maintenance (scrubbing) is required due to read/write statistics. Halbert’s registers merely hold error counts; they do not provide an explicit maintenance-requirement flag driven by actual read/write traffic.”
The Examiner respectfully disagrees. Nowhere in the claims a “maintenance-requirement flag” is recited. Halbert’s error recording occurs due to read and write activity. Halbert teaches “mode register 238 includes one or more multipurpose registers to store error count information. In one embodiment, mode register 238 includes one or more fields that can be set by memory controller 220 to enable the resetting of the error count information.” Paragraph [0045]. Halbert further teaches “ECS [error check and scrub] 170 includes logic to set a mode register 144 of memory device 140 to trigger ECS mode.” Paragraph [0040].
In view of the new reference and the foregoing remarks, independent claims 1, 7, and 13 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
As enumerated in the table below, instant claims 1-20 are anticipated by claims 1, 16, and 27 of US Patent 12,086,421.
Status
Instant Application
US Patent 12,086,421
Obvious in view of Gorobets et al. US 2006/0039196 and in further view of Huang et al. US 2017/0277471
1. (Currently Amended) A device, comprising: scrub memory; and a controller configured to: enter a maintenance operation mode to retrieve, from the scrub memory, information corresponding to main memory locations; store corrected data at the main memory locations; determine a required maintenance command count based on a number of read and write commands; and exit the maintenance operation mode based on completing a number of maintenance operations.
1. A memory device, comprising: a main memory with main memory locations configured to store data; an internal error correction code (ECC) engine for detecting and correcting errors; one or more mode registers accessible to an external controller and configured to store usage information about a required maintenance command count, wherein the required maintenance command count is based on a number of read and write commands, wherein the external controller is configured to issue a maintenance command based on an interrogation of the mode registers, and wherein a sequence of read/write commands is scheduled with a number of maintenance commands based on the required maintenance command count; and a scrub memory configured to selectively store information about main memory locations, wherein the information is associated with error correction performed by the ECC engine.
Same scope
2. The device of claim 1, wherein the number of maintenance operations is based on a parameter received with a maintenance command.
Claim 1.
Same scope
4. The device of claim 1, wherein the maintenance operation mode is entered in response to receiving a command, and the command is exempt of the main memory locations.
Claim 1.
Same scope
5. The device of claim 1, wherein the maintenance operation mode is entered in response to receiving a command based on hotness of data exchanged.
Claim 1.
Same scope
6. The device of claim 1, wherein the maintenance operation mode is entered in response to receiving a command based on a time lapse interval.
Claim 1.
Obvious in view of Gorobets et al. US 2006/0039196
7. A method comprising: in response to receiving a read command, reading data at a memory location; in response to using error correction for the read data, storing the memory location in a list; and flagging, based on a threshold, the memory location; and checking a status of the list in response to receiving a maintenance command.
16. A method to operate a memory device, the memory device comprising a main memory and a scrub memory, the method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; correcting errors in data read during the accessing; storing, at the scrub memory, information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold; determining a required maintenance command count based on a number of read and write commands; providing information in mode registers accessible to an external controller, the information including the required maintenance command count, wherein a sequence of read/write commands is scheduled with a number of maintenance commands based on the required maintenance command count; and receiving a first maintenance command of the number of maintenance commands from the external controller, wherein the first maintenance command is issued by the external controller based on an interrogation of the mode registers.
Same scope
8. The method of claim 7, further comprising controlling a raw bit error rate by refreshing at least one memory cell at the memory location.
Claim 16.
Same scope
10. The method of claim 7, wherein the memory location is a first memory location, the method further comprising reading and correcting second data at a second memory location in the list during a maintenance operation.
Claim 16.
Same scope
11. The method of claim 7, wherein using the error correction provides corrected data, and the corrected data is stored in the list.
Claim 16.
Same scope
12. The method of claim 7, wherein the flagging sets a flag, the method further comprising scrubbing the data and clearing the flag after the scrubbing.
Claim 16.
Obvious in view of Halbert et al. US 2017/0060681
13. (Currently Amended) A system comprising: a controller; a first register configured to store a count; and a second register configured to store an interval; wherein the first and second registers are accessible to the controller; wherein at least one of the first or second registers indicates a maintenance requirement based on actual read/write activity.
27. A memory device configured to use a command protocol comprising a maintenance command indicative of a request of multiple maintenance operations comprising an internal management, by the memory device, of selective correction of data at one or more main memory locations, wherein: the maintenance command is exempt of indications about the one or more main memory locations; a required maintenance command count is determined based on a number of read and write commands; the memory device comprises one or more mode registers configured to store information about the required maintenance command count; a sequence of read/write commands is scheduled with a number of maintenance commands based on the required maintenance command count; and the maintenance command is issued by an external controller based on an interrogation of the mode registers.
Same scope
14. The system of claim 13, wherein at least one of the first or second registers is specific for a single bank.
Claim 27.
Same scope
16. The system of claim 13, wherein the controller is configured to periodically poll at least one of the first or second registers.
Claim 27.
Same scope
17. The system of claim 13, wherein the controller is configured to determine a number of maintenance commands based on at least one of the count or interval.
Claim 27.
Same scope
18. The system of claim 17, wherein the controller is configured to determine a number of maintenance commands based on at least one of a number of read commands or a number of write commands.
Claim 27.
Same scope
19. The system of claim 13, wherein at least one of the first or second registers stores a time lapse since a previously-executed maintenance operation.
Claim 27.
Same scope
20. The system of claim 19, wherein the time lapse is for an individual bank.
Claim 27.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,086,421 in view of Gorobets et al. US 2006/0039196 (“Gorobets”) and in further view of Huang et al. US 2017/0277471 (“Huang”).
As per independent claim 1, Gorobets teaches exit the maintenance operation mode based on completing a number of maintenance operations (“If there are no other partially competed scrub operations that need to be competed, … the processing ended [ends].” Para 0184 and FIGS. 9A-B).
Given the teaching of Gorobets, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of US Patent 12,086,421 with “exit the maintenance operation mode based on completing a number of maintenance operations”.
Gorobets may not explicitly disclose, but Huang teaches determine a required maintenance command count based on a number of read and write commands (“When one read-count value of the group read-count values RC_1 to RC_n exceeds the preset range, the controller 110 may proceed to step S250 in order to perform a scan operation to the non-volatile storage block corresponding to the logical block addresses of a corresponding logical block address group corresponding to the read-count value, so as to check the number of error bits.” Para 0032 and FIG. 2).
Given the teaching of Huang, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of US Patent 12,086,421 and Gorobets with “determine a required maintenance command count based on a number of read and write commands”.
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 12,086,421 in view of Gorobets.
As per independent claim 7, Gorobets teaches checking a status of the list in response to receiving a maintenance command (“Two entry points to the processing are shown in FIG. 9, at 115 when a scrub trigger event is detected and at 117 when a command to execute deferred scrubs is received.” Paragraph [0168]. In the step 115, the memory is monitored for a scrub trigger event, para 0169. At step 117, a command to execute deferred scrubs is received. Therefore, the checking is done in response to receiving a command to execute scrub operations).
Given the teaching of Gorobets, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of US Patent 12,086,421 with “checking a status of the list in response to receiving a maintenance command”.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 27 of U.S. Patent No. 12,086,421 in view of Halbert et al. US 2017/0060681 (“Halbert”).
As per independent claim 13, Halbert teaches wherein at least one of the first or second registers indicates a maintenance requirement based on actual read/write activity (Halbert’s error recording occurs due to read and write activity. Halbert teaches “mode register 238 includes one or more multipurpose registers to store error count information. In one embodiment, mode register 238 includes one or more fields that can be set by memory controller 220 to enable the resetting of the error count information.” Paragraph [0045]. Halbert further teaches “ECS [error check and scrub] 170 includes logic to set a mode register 144 of memory device 140 to trigger ECS mode.” Paragraph [0040]).
Given the teaching of Halbert, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of US Patent 12,086,421 with “wherein at least one of the first or second registers indicates a maintenance requirement based on actual read/write activity”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-8 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gorobets et al. US 2006/0039196 (“Gorobets”).
As per independent claim 7, Gorobets teaches A method (“A … scrub algorithm is illustrated in the flowchart of FIG. 9.” Para 0168) comprising:
in response to receiving a read command, reading data at a memory location; in response to using error correction for the read data, storing the memory location in a list; and flagging, based on a threshold, the memory location (“time constraints may affect how data is handled when ECC detects one or more errors during a read operation in response to a host read command … For example, when data is read from the memory in response to a host read command, the data may need to be corrected before being sent to the host.” Para 0186 and FIG. 9. “One or more flags may also be included in the parameters 55 that indicate status or states.” Paras 0053-0054);
checking a status of the list in response to receiving a maintenance command (“Two entry points to the processing are shown in FIG. 9, at 115 when a scrub trigger event is detected and at 117 when a command to execute deferred scrubs is received.” Paragraph [0168]. In the step 115, the memory is monitored for a scrub trigger event, para 0169. At step 117, a command to execute deferred scrubs is received. Therefore, the checking is done in response to receiving a command to execute scrub operations).
As per dependent claim 8, Gorobets discloses the method of claim 7. Gorobets teaches further comprising controlling a raw bit error rate by refreshing at least one memory cell at the memory location (“When there are too many bit errors for a scrub data read under normal conditions to be corrected by an ECC, the data can be re-read with more relaxed reference conditions in order to read cells whose stored charge levels have been shifted outside of the normal range. Once correctly verified by the ECC, the read data may then be rewritten within normal charge range levels.” Para 0020).
As per dependent claim 10, Gorobets discloses the method of claim 7. Gorobets teaches wherein the memory location is a first memory location, the method further comprising reading and correcting second data at a second memory location in the list during a maintenance operation (“If there are no other partially competed scrub operations that need to be competed, then this is determined in a step 197 and … the processing ended.” Para 0184 and FIG. 9A).
As per dependent claim 11, Gorobets discloses the method of claim 7. Gorobets teaches wherein using the error correction provides corrected data, and the corrected data is stored in the list (“All corrected data, addresses and various parameters as determined at the time of deferral are temporarily stored and later retrieved when a deferred corrective action is executed.” Para 0022).
As per dependent claim 12, Gorobets discloses the method of claim 7. Gorobets teaches wherein the flagging sets a flag, the method further comprising scrubbing the data and clearing the flag after the scrubbing (“If there are no other partially competed scrub operations that need to be competed, then this is determined in a step 197 and … the processing ended.” Para 0184 and FIG. 9A).
Claims 13-14 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Halbert et al. US 2017/0060681 (“Halbert”).
As per independent claim 13, Halbert teaches A system (“FIG. 1 is … a system in which a memory device monitors errors with an error check mode.” Para 0028) comprising:
a controller (“Memory controller 120” para 0029 and FIG. 1);
a first register configured to store a count (“ECS [Error Check and Scrub] mode includes one or more registers to store error count information.” Para 0026 and FIG. 1);
a second register configured to store an interval (“Settings of register 144 can indicate configuration for I/O settings (e.g., timing,” para 0035 and FIG. 1);
wherein the first and second registers are accessible to the controller (“registers 144 … store data for access by memory controller 120” para 0035 and FIG. 1);
wherein at least one of the first or second registers indicates a maintenance requirement based on actual read/write activity (Halbert’s error recording occurs due to read and write activity. Halbert teaches “mode register 238 includes one or more multipurpose registers to store error count information. In one embodiment, mode register 238 includes one or more fields that can be set by memory controller 220 to enable the resetting of the error count information.” Paragraph [0045]. Halbert further teaches “ECS [error check and scrub] 170 includes logic to set a mode register 144 of memory device 140 to trigger ECS mode.” Paragraph [0040]).
As per dependent claim 14, Halbert discloses the method of claim 13. Halbert teaches wherein at least one of the first or second registers is specific for a single bank (“the bank counter” para 0059).
As per dependent claim 16, Halbert discloses the method of claim 13. Halbert teaches wherein the controller is configured to periodically poll at least one of the first or second registers (“ECS 156 reads a setting of register 144 to determine if ECS mode is enabled.” Para 0041).
As per dependent claim 17, Halbert discloses the method of claim 13. Halbert teaches wherein the controller is configured to determine a number of maintenance commands based on at least one of the count or interval (“ECS [Error Check and Scrub] mode includes one or more registers to store error count information.” Para 0026 and FIG. 1. “the minimum time for the ECS Mode period is tECSc (which can be the larger of 45 CKs or 110 ns).” Para 0051).
As per dependent claim 18, Halbert discloses the method of claim 17. Halbert teaches wherein the controller is configured to determine a number of maintenance commands based on at least one of a number of read commands or a number of write commands (“The memory enters ECS mode in response to a trigger. In ECS mode, the memory device checks for errors and corrects them, while counting error information that the memory controller can read.” Para 0080 and FIG. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Halbert in view of Gorobets.
As per dependent claim 19, Halbert discloses the method of claim 13. Halbert may not explicitly disclose, but in an analogous art in the same field of endeavor, Gorobets teaches wherein at least one of the first or second registers stores a time lapse since a previously-executed maintenance operation (“the scrub operation can be initiated in response to any number of factors, such as … a time period” para 0062 of Gorobets, which may be stored in any of the mode registers 144 (FIG. 1) of Halbert).
Given the teaching of Gorobets, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Halbert with “wherein at least one of the first or second registers stores a time lapse since a previously-executed maintenance operation”. The motivation would be that the invention improves system performance by deferring the scrub operation, para 0021 of Gorobets.
As per dependent claim 20, Halbert in combination with Gorobets discloses the system of claim 19. Halbert may not explicitly disclose, but Gorobets teaches wherein the time lapse is for an individual bank (“the scrub operation can be initiated in response to any number of factors, such as … a time period” para 0062 of Gorobets. (“Settings of register 144 can indicate configuration for I/O settings (e.g., timing,” para 0035 and FIG. 1 of Halbert, where register 144 can be associated with a bank).
The same motivation that was utilized for combining Halbert and Gorobets as set forth in claim 19 is equally applicable to claim 20.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Gorobets in view of Huang et al. US 2017/0277471 (“Huang”).
As per independent claim 1, Gorobets teaches A device (“a flash memory includes a memory cell array and a controller.” Para 0045 and FIG. 1A), comprising:
scrub memory (“a buffer memory (RAM) 25 … for the temporary storage …” para 0046 and FIG. 1A. Also see para 0022 “corrected data, addresses and various parameters as determined at the time of deferral are temporarily stored”);
a controller (“controller 19” para 0046 and FIG. 1A) configured to: enter a maintenance operation mode to retrieve, from the scrub memory, information corresponding to main memory locations (“if data corrections and/or re-writes have been deferred, … The data, ECC and other information stored for one unit by the step 171 is read by a step 191.” Para 0184 and FIGS. 9A-B);
store corrected data at the main memory locations (“In a step 195, the correct data is rewritten.” Para 0184 and FIGS. 9A-B);
exit the maintenance operation mode based on completing a number of maintenance operations (“If there are no other partially competed scrub operations that need to be competed, … the processing ended [ends].” Para 0184 and FIGS. 9A-B).
Gorobets may not explicitly disclose, but in an analogous art in the same field of endeavor, Huang teaches determine a required maintenance command count based on a number of read and write commands (“When one read-count value of the group read-count values RC_1 to RC_n exceeds the preset range, the controller 110 may proceed to step S250 in order to perform a scan operation to the non-volatile storage block corresponding to the logical block addresses of a corresponding logical block address group corresponding to the read-count value, so as to check the number of error bits.” Para 0032 and FIG. 2).
Given the teaching of Huang, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Gorobets with “determine a required maintenance command count based on a number of read and write commands”. The motivation would be that the disclosed invention prevents data loss, para 0007 of Huang.
As per dependent claim 2, Gorobets in combination with Huang discloses the device of claim 1. Gorobets teaches wherein the number of maintenance operations is based on a parameter received with a maintenance command (“at 117 … a command to execute deferred scrubs is received.” Para 0168 and FIG. 9A. “If there are no other partially competed scrub operations that need to be competed, then this is determined in a step 197 and … the processing ended [ends].” Para 0184 and FIG. 9A).
As per dependent claim 4, Gorobets in combination with Huang discloses the device of claim 1. Gorobets teaches wherein the maintenance operation mode is entered in response to receiving a command, and the command is exempt of the main memory locations (“at 117 … a command to execute deferred scrubs is received.” Para 0168 and FIG. 9A).
As per dependent claim 5, Gorobets in combination with Huang discloses the device of claim 1. Gorobets teaches wherein the maintenance operation mode is entered in response to receiving a command based on hotness of data exchanged (“the system may preferably use such hot counts to make scrub decisions.” Para 0067).
As per dependent claim 6, Gorobets in combination with Huang discloses the device of claim 1. Gorobets teaches wherein the maintenance operation mode is entered in response to receiving a command based on a time lapse interval (“the scrub operation can be initiated in response to any number of factors, such as … a time period” para 0062).
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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