Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-60 rejected on the ground of nonstatutory double patenting, obviousness type, as being unpatentable over claims 1-3,5-25 of U.S. Patent No. US 12056029 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because they simply remove some limitations and applied the claim to a generic PCIe based link.
Claim 21 is exemplary
Applicant claim 21
Patent 12056029 claim 1
A device comprising: a port to couple the device to another device via a Peripheral Component Interconnect Express (PCIe)-based link;
An apparatus comprising: …
and protocol stack circuitry to transmit the Flit comprising the error on a multilane link.
an error injection register comprising flow control unit (Flit) error injection information;
an error injection configuration register comprising error injection parameter information, the error injection parameter information comprising an indication of a spacing, in terms of a number of flow control units (Flits), between occurrences of injected errors; and an error injection logic circuit to: read the error injection parameter information from the error injection configuration register,
and protocol stack circuitry to inject an error into a Flit transmitted on the link or a Flit received on the link based on the error injection information.
and inject an error into a flow control unit (Flit) based on the error injection parameter information; and protocol stack circuitry to transmit the Flit comprising the error on a multilane link.
Claims 22-59 are rejected on the ground of nonstatutory double patenting, obviousness type, as being unpatentable over claims 1-3,5-25 of U.S. Patent No. US 12056029 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because they simply remove some limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-28,30-46,48-60 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10261880 B1 (Levin) in view of US 20170019247 A1 (Iyer) and US 20180096736 A1 (Teoh).
Regarding claim 21, Levin teaches,
A device comprising:
a port to couple the device to another device via a Peripheral Component Interconnect Express (PCIe)-based link;(fig 1:130,120,112; col 2 ln 55-60 “The host server computer includes a motherboard 112 and multiple slots 114 for receiving one or more add-in cards 120. The motherboard 112 is coupled to the add-in cards 120 via a communication bus 130, such as PCie bus or other type of communication bus.”)
an error injection register comprising flow control unit (Flit) error injection information;(fig 2:260,262; col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.” Levin’s agent loads the error injection parameter information from the test located from the test address register. The agent has the error injection configuration loaded in the agent’s configuration register to run the test.) and
protocol stack circuitry to inject an error into a Transaction layer Packet transmitted on the link or a Transaction layer Packet received on the link based on the error injection information.(col 3 ln 8-20 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer…. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors …. Any desired errors can be used and included in the tests 160.” Flow control unit(Flit) are components of the "Transaction layer Packets" (TLP) that Levin is modifying and testing. Levin supports injecting many different types of errors. Which type of error is specified in the test which is interpreted as “injecting an error based on the error injection parameter information”)
However, although Levin teaches testing various types of PCIe errors in various layers(transaction, data link, and physical layers as taught in col 3 ln 8-20) Levin does not specifically teach injecting an error into a flow control unit(flit).
On the other hand, Iyer teaches
A device comprising:
a port to couple the device to another device via a Peripheral Component Interconnect Express (PCIe)-based link;(fig 1:115; par 33 “In one embodiment, controller hub 115 can include a root hub, root complex, or root controller, such as in a PCie interconnection hierarchy.”; par 53 “… As one example, UPI may be utilized in high performance computing platforms, such as workstations or servers, including in systems where PCie or another interconnect protocol is typically used to connect processors, accelerators, I/O devices, and the like… Furthermore, the individual ideas developed may be applied to other interconnects and platforms, such as PCie, MIPI, QPI, etc.”)
an error injection register comprising flow control unit (Flit) test injection information; (fig 7:”LB pattern”; par 80 “In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern.”; par 207 “In one example, the system further includes a second redriver, which includes … a linear feedback shift register to generate an expected version of the binary sequence from the seed, pattern checking logic to compare a sequence in subsequent signals received from the second device with the expected version of the binary sequence generated by the linear feedback shift register, and a transmitter to send the signals received from the second device to the first device.” Although Iyer does not intentionally inject faults, Iyer does have test configuration registers to detect faults.) and
protocol stack circuitry to inject an error into a Flit transmitted on the link or a Flit received on the link(par 59 “Flow Control is often performed on both a flit and a packet basis. Error detection and correction is also potentially performed on a flit level basis.”) based on the error injection information. (fig 14:1415; par 141 “Further, the test manager 1415 can direct further testing of the link by causing settings of loopback master 1110 or loopback slave 1115 to be adjusted (i.e., to account for corresponding detected errors), but the test manager 1415 can also communicate or send data to redrivers 1105a, b to cause settings of the transmission, amplifier, or receiving logic of the redrivers to be adjusted to correct the area.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Levin to incorporate the flit test support and link width of Iyer. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Levin -- a need for a solution for the issue of how to test links to optimize interconnect performance(Iyer par 29 “Yet, it is a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Further, a variety of different interconnects can potentially benefit from subject matter described herein.” Par 30 “The Peripheral Component Interconnect (PCI) Express (PCie) interconnect fabric architecture and QuickPath Interconnect (QPI) fabric architecture, among other examples, can potentially be improved according to one or more principles described herein, among other examples. For instance, a primary goal of PCie is to enable components”) -- with Iyer providing a known method to solve a similar problem. Iyer provides “the instructions, when executed, further cause the machine to prompt the first redriver to adjust one or more settings of the first redriver based on assessing the first, second, third, and fourth test pattern results.”(Iyer par 215)
However, although Levin teaches an address register that points directly to the error injection parameter information, Levin and Iyer do not specifically teach an error injection configuration register comprising error injection parameter information.
On the other hand, Teoh teaches
A device comprising:
a port to couple the device to another device via a Peripheral Component Interconnect Express (PCIe)-based link;(fig 1:140; par 13 “The IO controller 125 is connected to a physical layer 135 (e.g., PHY layer), where the physical layer 135 is used to transmit data over a physical medium from the IO controller 125 or to receive data from the IO controller 125. The combination of the PSF 115 and IO controller 125 function as the 10 interface 140 between the TAM 105, CTE 110, and the physical layer 135. The CTE 110 handles the data structure upstream from the IO controller 125, and generates downstream traffic from the IO controller 125 to the physical layer 135.”; par 17)
an error injection register comprising test error injection information; (fig 3 par 18 "The TAM interface 315 or JTAG interface 320 may provide control parameters or other test parameters to a control and status register (CSR) 325." par 16 " the CTE 210 initializes each test using a test register, such as a DFT register.") and
protocol stack circuitry to perform a test transmitted on the link or a a test received on the link based on the error injection information. (fig 3:300; par 17 “The CTE 210 may function as a common test driver for multiple device circuits implemented within the system 200.” par 16 " the CTE 210 initializes each test using a test register, such as a DFT register.")
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Levin and Iyer to incorporate the test running environment of Teoh. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Levin and Iyer -- a need for a solution for the issue of how to quickly and efficiently test integrated circuits(Teoh par 2 “It is desirable to reduce the time and cost required for testing ICs”) -- with Teoh providing a known method to solve a similar problem. Teoh provides “A technical solution for improving test times and costs associated with IC production includes a new functional test block integrated onto the IC.”(Teoh par 10)
Regarding claim 22, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Levin further teaches,
wherein the Flit error injection information comprises one or more bits to enable Flit error injection on transmitted or received Flits.(fig 2:260,262; col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.”)
Regarding claim 23, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Levin further teaches,
wherein the Flit error injection information comprises one or more bits indicating a number of errors to be injected.(fig 2:260,262; col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.”)
Teoh further teaches,
wherein the test information comprises one or more bits indicating a number of errors to be injected. (Par 16 “The CTE 210 communicates with the TAM 205 or JTAG interface 215 to initialize each test sequence, either directly between blocks or through PSFI 220. In an example, the CTE 210 initializes each test using a test register, such as a DFT register.”)
Regarding claim 24, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Iyer further teaches,
wherein the Flit error injection information comprises one or more bits indicating a spacing between errors to be injected. (fig 7:”LB pattern”; par 80 “In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern.”; par 207; par 78 “One device (acting as master) can send a compliance pattern to another device (slave) and the slave can loop back the pattern after re-timing it to its local clock.” A pattern requires consistent spacing. Adjusting the pattern effectively adjusts the spacing, so Iyer teaches indicating spacing by teaching expected pattern.)
Regarding claim 25, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Levin further teaches,
wherein the Flit error injection information comprises one or more bits(col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.”) indicating a Flit type on which errors are to be injected.(col 3 ln 8-23 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer, …. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors can include receiver errors and link errors. Any desired errors can be used and included in the tests 160. Other examples include payload exceeding maximum size, data length does not correspond to header, ECRC error, unsupported requests errors, etc.”)
Regarding claim 26, Levin, Iyer, and Teoh teaches,
The device of claim 25,
Levin further teaches,
wherein the one or more bits indicating the Flit type on which the errors are to be injected indicate injection on any Flit type, injection on Payload Flits.( col 3 ln 8-23 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer, …. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors can include receiver errors and link errors. Any desired errors can be used and included in the tests 160. Other examples include payload exceeding maximum size, data length does not correspond to header, ECRC error, unsupported requests errors, etc.” injection on any flit type and injection on payload flits would fall under the data link layer error category.)
Regarding claim 27, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Iyer further teaches,
wherein the Flit error injection information comprises one or more bits indicating a number of consecutive Flits that will be injected with an error. (fig 7:”LB pattern”; par 80 “In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern.”; par 207 “In one example, the system further includes a second redriver, which includes … a linear feedback shift register to generate an expected version of the binary sequence from the seed, pattern checking logic to compare a sequence in subsequent signals received from the second device with the expected version of the binary sequence generated by the linear feedback shift register, and a transmitter to send the signals received from the second device to the first device.” The test pattern specifies exactly how the data is laid out during the test.)
Regarding claim 28, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Levin further teaches,
wherein the Flit error injection information comprises one or more bits indicating an error type to be injected.(col 3 ln 8-20 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer…. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors …. Any desired errors can be used and included in the tests 160.”)
Regarding claim 30, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Iyer further teaches,
wherein the Flit error injection information comprises one or more bits indicating an error offset within the Flit.( fig 7:”LB pattern”; par 80 “In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern.”; par 207 “In one example, the system further includes a second redriver, which includes … a linear feedback shift register to generate an expected version of the binary sequence from the seed, pattern checking logic to compare a sequence in subsequent signals received from the second device with the expected version of the binary sequence generated by the linear feedback shift register, and a transmitter to send the signals received from the second device to the first device.” The test pattern specifies exactly how the data is laid out during the test.)
Regarding claim 31, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Levin further teaches,
wherein the Flit error injection information comprises one or more bits indicating an error magnitude. (fig 4:460,470; col 4 ln 58-66 “However, if the trigger flag is set, then in process block 460 the agent retrieves the test address from memory and runs the test including injecting PCie errors on the bus (470). Finally in process block 480, the host server computer can be monitored to see how it responds to the generated errors created by the tests. Thus, difficult to test errors can be effectively tested through the use of tests loaded onto standard hardware within the host server computer.” The error to be injected is defined in the test, so the magnitude of the error is based on how the test defines the error.)
Regarding claim 32, Levin, Iyer, and Teoh teaches,
The device of claim 21,
Levin further teaches,
further comprising a test error injection register comprising a test error injection information(fig 4:470; col 4 ln 58-61 “However, if the trigger flag is set, then in process block 460 the 60 agent retrieves the test address from memory and runs the test including injecting PCie errors on the bus (470).), and the protocol stack circuitry is further to inject an error into a test based on the test error injection information (col 3 ln 8-20 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer…. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors …. Any desired errors can be used and included in the tests 160.” Flow control unit(Flit) are components of the "Transaction layer Packets" (TLP) that Levin is modifying and testing.; col 3 ln 54-58 “The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.”) and transmit the test comprising the error on the link. (fig 4:470; col 4 ln 58-61 “However, if the trigger flag is set, then in process block 460 the 60 agent retrieves the test address from memory and runs the test including injecting PCie errors on the bus (470).”)
However, Levin does not specifically teach ordered sets.
On the other hand, Iyer further teaches,
further comprising an ordered set (OS)(par 92 “In one embodiment, link training can be provided and include the sending of one or more of scrambled training sequences, ordered sets, and control sequences, such as in connection with a defined supersequence.”) error injection register comprising OS error injection information(par 93 “In one embodiment, ordered sets and control sequences are not scrambled or staggered and are transmitted identically, simultaneously and completely on all lanes.”), and the protocol stack circuitry is further to start a test based on the OS error injection information and transmit the OS comprising the error on the link. (par 93 “A valid reception of an ordered set may include checking of at least a portion of the ordered set (or entire ordered set for partial ordered sets).”)
Regarding claim 33, Levin, Iyer, and Teoh teaches,
The device of claim 32,
Levin further teaches,
wherein the OS error injection information comprises one or more bits to enable OS error injection.(fig 2:260,262; col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.”)
Regarding claim 34, Levin, Iyer, and Teoh teaches,
The device of claim 32,
Levin further teaches,
wherein the OS error injection information comprises one or more bits indicating a number of errors to be injected. (fig 2:260,262; col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.”)
Teoh further teaches,
wherein the OS test information comprises one or more bits indicating a number of errors to be injected(Par 16 “The CTE 210 communicates with the TAM 205 or JTAG interface 215 to initialize each test sequence, either directly between blocks or through PSFI 220. In an example, the CTE 210 initializes each test using a test register, such as a DFT register.”)
Regarding claim 35, Levin, Iyer, and Teoh teaches,
The device of claim 32,
Iyer further teaches,
wherein the OS error injection information comprises one or more bits indicating a spacing between errors to be injected. ( fig 7:”LB pattern”; par 80 “In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern.”; par 207; par 78 “One device (acting as master) can send a compliance pattern to another device (slave) and the slave can loop back the pattern after re-timing it to its local clock.” A pattern requires consistent spacing. Adjusting the pattern effectively adjusts the spacing, so Iyer teaches indicating spacing by teaching expected pattern.)
Regarding claim 36, Levin, Iyer, and Teoh teaches,
The device of claim 32,
Levin further teaches,
wherein the OS error injection information comprises one or more bits indicating an OS type on which errors are to be injected. (col 3 ln 8-23 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer, …. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors can include receiver errors and link errors. Any desired errors can be used and included in the tests 160. Other examples include payload exceeding maximum size, data length does not correspond to header, ECRC error, unsupported requests errors, etc.”)
Regarding claim 37, Levin, Iyer, and Teoh teaches,
The device of claim 32,
Iyer further teaches,
wherein the OS error injection information comprises one or more bits indicating individual bytes where errors are to be injected.(fig 7:”LB pattern”; par 80 “In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern.”; par 207; par 78 “One device (acting as master) can send a compliance pattern to another device (slave) and the slave can loop back the pattern after re-timing it to its local clock.”)
Regarding claim 38, Levin, Iyer, and Teoh teaches,
The device of claim 32,
Iyer further teaches,
wherein the OS error injection information comprises one or more bits indicating a lane number for error injection.(par 151 “In some implementations, such margining tests can be performed in real time on a subset of lanes of the link using start test and stop test while the remaining subset carries normal traffic. The subsets can be swapped thus completing the margining of all lanes without bringing down the entire link, among other potential features.”)
Regarding claim 39, Levin, Iyer, and Teoh teaches,
A method comprising:
encoding, by Peripheral Component Interconnect Express (PCIe)-compatible protocol stack circuitry(fig 1:130,120,112; col 2 ln 55-60 “The host server computer includes a motherboard 112 and multiple slots 114 for receiving one or more add-in cards 120. The motherboard 112 is coupled to the add-in cards 120 via a communication bus 130, such as PCie bus or other type of communication bus.”), a flow control unit (Flit); (col 3 ln 8-20 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer…. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors …. Any desired errors can be used and included in the tests 160.” Flow control unit(Flit) are components of the "Transaction layer Packets" (TLP) that Levin is modifying and testing. Levin supports injecting many different types of errors. Which type of error is specified in the test which is interpreted as “injecting an error based on the error injection parameter information”)
injecting an error into the Flit(col 3 ln 8-20 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer…. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors …. Any desired errors can be used and included in the tests 160.” Flow control unit(Flit) are components of the "Transaction layer Packets" (TLP) that Levin is modifying and testing. Levin supports injecting many different types of errors. Which type of error is specified in the test which is interpreted as “injecting an error based on the error injection parameter information”) based on Transaction Layer Packet error injection information referenced by an error injection register;(fig 2:260,262; col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.” Levin’s agent loads the error injection parameter information from the test located from the test address register. The agent has the error injection configuration loaded in the agent’s configuration register to run the test.) and
transmitting the Flit on a PCIe-based link with the injected error. (fig 4:470; col 4 ln 58-61 “However, if the trigger flag is set, then in process block 460 the 60 agent retrieves the test address from memory and runs the test including injecting PCie errors on the bus (470).”)
However, although Levin teaches testing various types of PCIe errors in various layers(transaction, data link, and physical layers as taught in col 3 ln 8-20) Levin does not specifically teach injecting an error into a flow control unit(flit).
On the other hand, Iyer teaches
A method comprising:
encoding, by Peripheral Component Interconnect Express (PCIe)-compatible protocol stack circuitry(fig 1:115; par 33 “In one embodiment, controller hub 115 can include a root hub, root complex, or root controller, such as in a PCie interconnection hierarchy.”; par 53 “… As one example, UPI may be utilized in high performance computing platforms, such as workstations or servers, including in systems where PCie or another interconnect protocol is typically used to connect processors, accelerators, I/O devices, and the like… Furthermore, the individual ideas developed may be applied to other interconnects and platforms, such as PCie, MIPI, QPI, etc.”), a flow control unit (Flit); (par 59 “Flow Control is often performed on both a flit and a packet basis. Error detection and correction is also potentially performed on a flit level basis.”)
injecting an error into the Flit(par 59 “Flow Control is often performed on both a flit and a packet basis. Error detection and correction is also potentially performed on a flit level basis.”) based on Flit error injection information stored in a Flit test injection register; (fig 7:”LB pattern”; par 80 “In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern.”; par 207 “In one example, the system further includes a second redriver, which includes … a linear feedback shift register to generate an expected version of the binary sequence from the seed, pattern checking logic to compare a sequence in subsequent signals received from the second device with the expected version of the binary sequence generated by the linear feedback shift register, and a transmitter to send the signals received from the second device to the first device.” Although Iyer does not intentionally inject faults, Iyer does have test configuration registers to detect faults.) and
transmitting the Flit on a PCIe-based link with the injected error. (fig 14:1415; par 141 “Further, the test manager 1415 can direct further testing of the link by causing settings of loopback master 1110 or loopback slave 1115 to be adjusted (i.e., to account for corresponding detected errors), but the test manager 1415 can also communicate or send data to redrivers 1105a, b to cause settings of the transmission, amplifier, or receiving logic of the redrivers to be adjusted to correct the area.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Levin to incorporate the flit test support and link width of Iyer. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Levin -- a need for a solution for the issue of how to test links to optimize interconnect performance(Iyer par 29 “Yet, it is a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Further, a variety of different interconnects can potentially benefit from subject matter described herein.” Par 30 “The Peripheral Component Interconnect (PCI) Express (PCie) interconnect fabric architecture and QuickPath Interconnect (QPI) fabric architecture, among other examples, can potentially be improved according to one or more principles described herein, among other examples. For instance, a primary goal of PCie is to enable components”) -- with Iyer providing a known method to solve a similar problem. Iyer provides “the instructions, when executed, further cause the machine to prompt the first redriver to adjust one or more settings of the first redriver based on assessing the first, second, third, and fourth test pattern results.”(Iyer par 215)
However, although Levin teaches an address register that points directly to the error injection parameter information, Levin and Iyer do not specifically teach an error injection configuration register comprising error injection parameter information.
On the other hand, Teoh teaches
A method comprising:
encoding, by Peripheral Component Interconnect Express (PCIe)-compatible protocol stack circuitry, (fig 1:140; par 13 “The IO controller 125 is connected to a physical layer 135 (e.g., PHY layer), where the physical layer 135 is used to transmit data over a physical medium from the IO controller 125 or to receive data from the IO controller 125. The combination of the PSF 115 and IO controller 125 function as the 10 interface 140 between the TAM 105, CTE 110, and the physical layer 135. The CTE 110 handles the data structure upstream from the IO controller 125, and generates downstream traffic from the IO controller 125 to the physical layer 135.”; par 17)
injecting an error into the Flit based on test error injection information stored in a test error injection register; (fig 3 par 18 "The TAM interface 315 or JTAG interface 320 may provide control parameters or other test parameters to a control and status register (CSR) 325." par 16 " the CTE 210 initializes each test using a test register, such as a DFT register.") and
transmitting the Flit on a PCIe-based link with the injected error. (fig 3:300; par 17 “The CTE 210 may function as a common test driver for multiple device circuits implemented within the system 200.” par 16 " the CTE 210 initializes each test using a test register, such as a DFT register.")
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Levin and Iyer to incorporate the test running environment of Teoh. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Levin and Iyer -- a need for a solution for the issue of how to quickly and efficiently test integrated circuits(Teoh par 2 “It is desirable to reduce the time and cost required for testing ICs”) -- with Teoh providing a known method to solve a similar problem. Teoh provides “A technical solution for improving test times and costs associated with IC production includes a new functional test block integrated onto the IC.”(Teoh par 10)
Regarding claims 40-46,48-56, they are the method that the device of claims 22-28,30-38 implement and are rejected for the same reasons.
Regarding claim 57, Levin, Iyer, and Teoh teaches,
A system comprising: a first device; and a second device communicably coupled to the first device over a Peripheral Component Interconnect Express (PCIe)-based link, (fig 1:130,120,112; col 2 ln 55-60 “The host server computer includes a motherboard 112 and multiple slots 114 for receiving one or more add-in cards 120. The motherboard 112 is coupled to the add-in cards 120 via a communication bus 130, such as PCie bus or other type of communication bus.”) wherein the second device comprises:
an error injection register comprising a reference to flow control unit (Flit) error injection information; (fig 2:260,262; col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.” Levin’s agent loads the error injection parameter information from the test located from the test address register. The agent has the error injection configuration loaded in the agent’s configuration register to run the test.) and
protocol stack circuitry to inject an error into a Transaction layer Packet based on the Transaction layer Packet error injection information and transmit the Flit comprising the error to the first device over the link. (col 3 ln 8-20 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer…. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors …. Any desired errors can be used and included in the tests 160.” Flow control unit(Flit) are components of the "Transaction layer Packets" (TLP) that Levin is modifying and testing. Levin supports injecting many different types of errors. Which type of error is specified in the test which is interpreted as “injecting an error based on the error injection parameter information”)
However, although Levin teaches testing various types of PCIe errors in various layers(transaction, data link, and physical layers as taught in col 3 ln 8-20) Levin does not specifically teach injecting an error into a flow control unit(flit).
On the other hand, Iyer teaches
A system comprising: a first device; and a second device communicably coupled to the first device over a Peripheral Component Interconnect Express (PCIe)-based link, (fig 1:115; par 33 “In one embodiment, controller hub 115 can include a root hub, root complex, or root controller, such as in a PCie interconnection hierarchy.”; par 53 “… As one example, UPI may be utilized in high performance computing platforms, such as workstations or servers, including in systems where PCie or another interconnect protocol is typically used to connect processors, accelerators, I/O devices, and the like… Furthermore, the individual ideas developed may be applied to other interconnects and platforms, such as PCie, MIPI, QPI, etc.”) wherein the second device comprises:
an error injection register comprising flow control unit (Flit) test injection information(fig 7:”LB pattern”; par 80 “In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern.”; par 207 “In one example, the system further includes a second redriver, which includes … a linear feedback shift register to generate an expected version of the binary sequence from the seed, pattern checking logic to compare a sequence in subsequent signals received from the second device with the expected version of the binary sequence generated by the linear feedback shift register, and a transmitter to send the signals received from the second device to the first device.” Although Iyer does not intentionally inject faults, Iyer does have test configuration registers to detect faults.); and
protocol stack circuitry to inject an error into a Flit based on the test error injection information(par 59 “Flow Control is often performed on both a flit and a packet basis. Error detection and correction is also potentially performed on a flit level basis.”) and transmit the Flit comprising the error to the first device over the link. (fig 14:1415; par 141 “Further, the test manager 1415 can direct further testing of the link by causing settings of loopback master 1110 or loopback slave 1115 to be adjusted (i.e., to account for corresponding detected errors), but the test manager 1415 can also communicate or send data to redrivers 1105a, b to cause settings of the transmission, amplifier, or receiving logic of the redrivers to be adjusted to correct the area.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Levin to incorporate the flit test support and link width of Iyer. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Levin -- a need for a solution for the issue of how to test links to optimize interconnect performance(Iyer par 29 “Yet, it is a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Further, a variety of different interconnects can potentially benefit from subject matter described herein.” Par 30 “The Peripheral Component Interconnect (PCI) Express (PCie) interconnect fabric architecture and QuickPath Interconnect (QPI) fabric architecture, among other examples, can potentially be improved according to one or more principles described herein, among other examples. For instance, a primary goal of PCie is to enable components”) -- with Iyer providing a known method to solve a similar problem. Iyer provides “the instructions, when executed, further cause the machine to prompt the first redriver to adjust one or more settings of the first redriver based on assessing the first, second, third, and fourth test pattern results.”(Iyer par 215)
However, although Levin teaches an address register that points directly to the error injection parameter information, Levin and Iyer do not specifically teach an error injection configuration register comprising error injection parameter information.
On the other hand, Teoh teaches
A system comprising: a first device; and a second device communicably coupled to the first device over a Peripheral Component Interconnect Express (PCIe)-based link, (fig 1:140; par 13 “The IO controller 125 is connected to a physical layer 135 (e.g., PHY layer), where the physical layer 135 is used to transmit data over a physical medium from the IO controller 125 or to receive data from the IO controller 125. The combination of the PSF 115 and IO controller 125 function as the 10 interface 140 between the TAM 105, CTE 110, and the physical layer 135. The CTE 110 handles the data structure upstream from the IO controller 125, and generates downstream traffic from the IO controller 125 to the physical layer 135.”; par 17) wherein the second device comprises:
an error injection register comprising test error injection information; (fig 3 par 18 "The TAM interface 315 or JTAG interface 320 may provide control parameters or other test parameters to a control and status register (CSR) 325." par 16 " the CTE 210 initializes each test using a test register, such as a DFT register.") and
protocol stack circuitry to perform a test based on the test error injection information and transmit the test data comprising the error to the first device over the link. (fig 3:300; par 17 “The CTE 210 may function as a common test driver for multiple device circuits implemented within the system 200.” par 16 " the CTE 210 initializes each test using a test register, such as a DFT register.")
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Levin and Iyer to incorporate the test running environment of Teoh. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Levin and Iyer -- a need for a solution for the issue of how to quickly and efficiently test integrated circuits(Teoh par 2 “It is desirable to reduce the time and cost required for testing ICs”) -- with Teoh providing a known method to solve a similar problem. Teoh provides “A technical solution for improving test times and costs associated with IC production includes a new functional test block integrated onto the IC.”(Teoh par 10)
Regarding claim 58, it is the system that the device of claim 32 implements and is rejected for the same reasons.
Regarding claim 59, Levin, Iyer, and Teoh teaches,
The system of claim 57,
Levin further teaches,
wherein the first device comprises: an error injection register (fig 2:260,262; col 3 ln 52-58 “Once the flag is set, the agent can read register 272 in order to obtain an address of the test which is to be executed. The agent can then load and execute the appropriate test in order to test PCie functionality. For example, the agent 250 can inject PCie errors on to the communication bus so as to determine how the host server computer responds to the errors.” Levin’s agent loads the error injection parameter information from the test located from the test address register. The agent has the error injection configuration loaded in the agent’s configuration register to run the test.) comprising flow control unit (Flit) error injection information; (col 3 ln 8-20 “The PCie errors that can be used include transaction layer errors, data link layer errors, physical layer errors, etc. PCie is a packet-based serial bus that provides a high-speed point-to-point differential signaling link for interconnecting devices. At the transaction layer…. The data link layer errors can include one or more of the following: LCRC check failure for TLPs, sequence number checks for TLPs, LCRC check failure, data link layer protocol errors, etc. Physical layer errors …. Any desired errors can be used and included in the tests 160.” Flow control unit(Flit) are components of the "Transaction layer Packets" (TLP) that Levin is modifying and testing. Levin supports injecting many different types of errors. Which type of error is specified in the test which is interpreted as “injecting an error based on the error injection parameter information”) and
protocol stack circuitry to inject an error into a Flit received from the second device over the link based on the Flit error injection information.(fig 6:614; col 7 ln 39-47 “In process block 614 transactions are received by the host server computer including purposefully injected errors on the bus by the test code executing on the add-in card. For example, the add-in card includes an embedded processor that executes the test code in response to the trigger event from the host server computer. The test code can include software for injecting errors on the interface bus between a host server computer and the add-in card.”)
Iyer also teaches,
protocol stack circuitry to inject an error into a Flit(par 59 “Flow Control is often performed on both a flit and a packet basis. Error detection and correction is also potentially performed on a flit level basis.”) received from the second device over the link based on the Flit error injection information.(par 141 “Accordingly, through the enhanced logic of the redrivers, each leg of the link (i.e., between endpoints and redrivers) can be assessed, trained, and optimized.”; par 149 “The combination of the four pattern check results can allow error results to be detected and compared to determine in which of the legs of the loop back path (i.e., between the master 1110 and redriver 1105a, between redriver 1105a and slave device 1115, between slave device 1115 and redriver 1105b, and redriver 1105b and master device 1110) the error occurred.”)
Regarding claim 60, Levin, Iyer, and Teoh teaches,
The system of claim 59,
Iyer further teaches,
wherein the first device further comprises ordered set (OS) error injection information, (par 92 “In one embodiment, link training can be provided and include the sending of one or more of scrambled training sequences, ordered sets, and control sequences, such as in connection with a defined supersequence.”) and the protocol stack circuitry is further to inject an error into an OS received from the second device based on the OS error injection information. (par 93 “In one embodiment, ordered sets and control sequences are not scrambled or staggered and are transmitted identically, simultaneously and completely on all lanes.”; par 93 “A valid reception of an ordered set may include checking of at least a portion of the ordered set (or entire ordered set for partial ordered sets).”)
Claim(s) 29,47 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10261880 B1 (Levin), US 20170019247 A1 (Iyer), and US 20180096736 A1 (Teoh) as applied to claim 28 above, and further in view of US 20190176838 A1(Kakoee).
Regarding claim 29, Levin, Iyer, and Teoh teaches,
The device of claim 28,
However, although Iyer mentions error detection and correction performed on a flit level basis (par 59), Levin, Iyer, and Teoh do not specifically teach random injection of correctable and uncorrectable errors, correctable error injection into one forward error correction (FEC) group, or correctable error injection into three FEC groups.
On the other hand, Kakoee teaches,
A system that tests ECC error handling by injecting a fault based on ECC data and raw data.(par 5 “A system and a method for error-correction code ("ECC") error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and method may further inject a fault based on the ECC syndrome data and/or the raw data and detect, by an ECC checker, an ECC error. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.”)
wherein the one or more bits indicating an error type to be injected indicate random injection of correctable and uncorrectable errors(par 44 “For example, a particular data mask may be configured to create an ECC error relating to two bits wherein both bits are detected as erroneous but only one may be actually correctable via ECC.”; par 41), correctable error injection into one forward error correction (FEC) group(par 41 “The ECC diagnostic module 220 may be configured to detect a malfunction in the first error detection and/or correction path 202 ( e.g., detect a fault in the ECC function) for the system 200. First, the ECC diagnostic module 220 may generate test data for introducing or injecting a fault based on the raw data 227 and/or the ECC syndrome data 229. Further, the ECC diagnostic module 220 may be configured to verify that the created test data results in the ECC error being detected when such ECC error is in fact expected.”), or correctable error injection into three FEC groups.(par 45 “The ECC checker 230 may output different error status: (1) no error, (2) one-bit correctable error, (3) two-bit uncorrected error, and (4) ECC bit toggle. In such fashion, the ECC checker 230 may output various error status based on the implementation and capability of how many errors the ECC checker 230 may detect.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Levin, Iyer, and Teoh to incorporate the ECC testing techniques of Kakoee. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Levin, Iyer, and Teoh -- a need for how to use fault injection to test ECC in interconnects (Kakoee par 3 “One such problem is handling, and potentially correcting, errors within data stored in memory. Errors can occur anywhere containing data ( e.g., memory, caches, buses, interconnects, etc.).”) -- with Kakoee providing a known method to solve a similar problem. Kakoee provides “A system and a method for error-correction code ("ECC") error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and method may further inject a fault based on the ECC syndrome data and/or the raw data and detect, by an ECC checker, an ECC error. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.”(Kakoee par 5)
Regarding claim 47, it is the method that the device of claim 29 implements and is rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20180203963 A1 - Eghbal - NoC reliability tester, injects faults
US 20210050941 A1 - Das Sharma - same inventor, same applicant, published after application date. Similar invention, but claims focus more on the error detection side rather than the error injection side.
US 20190042380 A1 - Das Sharma - same inventor, more than a year before provisional
application date. similar environment, but injects crosstalk for testing instead of errors.
US 20200366587 A1 - White - injects errors into packet headers to test API dependency errors and does latency injection. Focuses on latency injection. Microservices context.
US 20200366573 A1 - White - injects errors into packet headers, and mentions injection more than reference 20200366587. Microservices context.
US 20180196103 A1 - Champoux - tests communication links between boards and records errors in an error log.
US 20200118642 A1 - Fuoco - tests a fault detection circuit, uses error correction codes in detection.
US 9432298 B1 - Smith - uses ACK and NAK messages that may requires replay of invalid TLPs
US 7010607 B1 - Bunton - The NAK tells the requestor to resend earlier frames.
US 9384108 B2 - McIlvain – Teaches "a register accessible by a user-interface for receiving a test configuration" in claim 6. Related to the configuration register limitation in claim 1.
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